Preparation method of surface structure of back contact battery

Abstract

The invention provides a preparation method of a surface structure of a back contact battery, which relates to the technical field of back contact batteries, and comprises the following steps: S1, carrying out double-sided polishing on the surface of a silicon wafer: firstly carrying out rough polishing, removing a damaged layer on the surface of the silicon wafer, then cleaning with acid and ozone, then carrying out fine polishing, then cleaning with a mixed solution of hydrogen peroxide and alkali, and then carrying out acid pickling with ozone, then cleaning with a mixed solution of acid and hydrogen peroxide, and finally washing and drying; sequentially depositing a tunneling oxide layer and amorphous silicon on a single surface at high temperature; and performing high-temperature diffusion on the surface to form a crystallized first semiconductor region and a mask layer BSG. According to the invention, the specific suede structure is formed on the front surface, and the polished surface is formed on the back isolation base region, so that high reflectivity of the back isolation base region is ensured, the specific suede structure on the front surface can be independently designed, and meanwhile, a double-surface ozone oxidation process is added; therefore, the open-circuit voltage and the short-circuit current of the cell are improved, and the photoelectric conversion efficiency of the cell is improved.

Description

Technical Field

[0001] This invention relates to the field of back contact battery technology, and more particularly to a method for preparing a back contact battery surface structure. Background Technology

[0002] Back-contact solar cells are a new type of photovoltaic device structure in which the PN junction region and metal electrodes are all located on the back of the cell. Its core feature is that there are no metal grid lines on the front. This unique design fundamentally eliminates the blocking effect of the front electrode on incident light in traditional cells, maximizing the light absorption area. The surface structure of back-contact solar cells mainly includes a light-harvesting textured layer on the front and an electrode contact area on the back. The textured structure on the front focuses on photon absorption optimization, while the back structure simultaneously undertakes the dual functions of carrier separation and collection and long-wavelength photon reflection and reuse.

[0003] Existing back-contact battery manufacturing technologies mainly employ the following approaches: 1. The front side uses a conventional pyramidal textured surface structure, with a reflectivity typically ranging from 8% to 11%; 2. The back-side PN junction isolation region uses a similar pyramidal morphology to the front side, maintaining a reflectivity of 8% to 11%; 3. The passivation system often employs an Al2O3 / SiNx stacked structure or a single SiONx thin film, prepared via plasma-enhanced chemical vapor deposition. However, while this technology is relatively mature, it has significant shortcomings in optical management and surface passivation.

[0004] Existing back-contact battery technology has three key drawbacks: First, the standard pyramid textured surface on the front side has high reflectivity, resulting in the loss of a significant portion of incident photons; second, the textured surface morphology of the back isolation region results in insufficient reflectivity and low utilization of long-wavelength photons; and finally, the high interface state density of conventional passivation films leads to excessively fast surface recombination, severely affecting minority carrier lifetime.

[0005] These defects collectively restrict further improvement in the conversion efficiency of back-contact batteries. Therefore, it is urgent to break through the existing technological bottlenecks through innovative surface structure design and material systems. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and to propose a method for preparing a back contact battery surface structure.

[0007] To achieve the above objectives, the present invention employs the following technical solution: a method for preparing a back contact battery surface structure, comprising the following steps:

[0008] S1. Double-sided polishing of the silicon wafer surface: First, rough polishing to remove the damaged layer on the silicon wafer surface, then cleaning with acid and ozone, then fine polishing, then cleaning with a mixture of hydrogen peroxide and alkali, then cleaning with ozone and acid, then cleaning with a mixture of acid and hydrogen peroxide, and finally washing with water and drying; then high-temperature deposition of tunneling oxide layer and amorphous silicon on one side; then high-temperature diffusion to form the crystallized first semiconductor region and mask layer BSG on this side;

[0009] S2. A first pattern is formed by laser engraving on the mask layer BSG, and then the first pattern area is polished to form the base area;

[0010] S3. A tunneling oxide layer and amorphous silicon are sequentially deposited on one side of the base region at high temperature, and then diffused to form a crystallized second semiconductor region and a mask layer PSG.

[0011] S4. The mask layer PSG on the first semiconductor is removed by laser; the first semiconductor region and the second semiconductor region are formed on the back side at intervals.

[0012] S5. Etching: Remove the plating areas on the front and sides.

[0013] S6. Pile forming: A special pile structure is formed on the front side using a mixture of specially formulated pile additives and alkali.

[0014] S7. Laser engraving removes the mask area at the junction of the first semiconductor and the second semiconductor to form an isolation pattern;

[0015] S8. Polishing: A mixture of alkaline solution and polishing additive is used to remove the residual mask layer on the isolation pattern to form an isolation base region. The isolation base region has a square tower base structure to isolate the first semiconductor and the second semiconductor. Then, an acid solution is used to remove the mask layer BSG on the first semiconductor and the mask layer PSG on the second semiconductor.

[0016] S9. The ozone oxidation process forms a dense silicon oxide thin layer in a specific textured structure, isolation base region, first semiconductor region and second semiconductor region.

[0017] S10, front-side deposition of front-side passivation and anti-reflection layer;

[0018] S11, Backside passivation layer deposited;

[0019] S12. Electrodes are printed on the first semiconductor and the second semiconductor, and then sintered to form conductive electrodes.

[0020] Preferably, the reflectivity of the upright pyramid structure is 9% to 11%, the reflectivity of the inverted pyramid structure is 7% to 9%, and the reflectivity of the chain pyramid structure is 5% to 8%.

[0021] Preferably, the width of the upright pyramid is 0.8-2.3 μm and the height is 0.5-1.3 μm; the width of the inverted pyramid is 1.0-2.3 μm and the height is 0.6-1.5 μm; and the width of the chain pyramid is 1.2-2.5 μm and the height is 0.7-1.8 μm.

[0022] Preferably, the isolation base region is a square tower base with a width of 10-15 μm.

[0023] Preferably, the reflectivity of the isolation base region is 40% to 45%.

[0024] Preferably, the volume concentration of sodium hydroxide is 5% to 10%, the concentration of the additive is 0% to 1%, the reaction time is 50 to 200 s, and the temperature is 70 to 90 °C; the acid solution is hydrofluoric acid, the concentration of the hydrofluoric acid solution is 2% to 8%, the reaction time is 200 to 400 s, and the temperature is 25 °C.

[0025] Preferably, the ozone concentration in the ozone oxidation process is 20-60 ppm.

[0026] Preferably, the thickness of the silicon oxide thin layer is

[0027] Preferably, the structure of the first semiconductor region is, in sequence, a silicon-based region, a first tunneling layer, a boron-doped polycrystalline silicon layer, and a thin silicon oxide layer; the structure of the second semiconductor region is, in sequence, a silicon-based region, a first tunneling layer, a phosphorus-doped polycrystalline silicon layer, and a thin silicon oxide layer; and the structure of the isolation base region is, in sequence, a silicon-based region and a thin silicon oxide layer.

[0028] Preferably, the thickness of the mask layer BSG is 10-100 nm, the thickness of the mask layer PSG is 10-100 nm, the thickness of the first tunneling layer is 0.5-2 nm, the thickness of the boron-doped polysilicon layer is 100-500 nm, and the thickness of the phosphorus-doped polysilicon layer is 100-500 nm.

[0029] Compared with the prior art, the advantages and positive effects of the present invention are as follows:

[0030] 1. This invention innovatively designs a specific textured surface structure on the front of the battery, significantly reducing the front reflectivity to an excellent level of 5%–11%, thereby greatly improving light absorption efficiency. Simultaneously, the square tower-based isolation base design on the back achieves a back reflectivity of 40%–45%, effectively improving the utilization efficiency of long-wavelength photons. This synergistic optimization of the front and back surfaces overcomes the limitations of traditional back-contact batteries in optical management.

[0031] 2. This invention creatively introduces a double-sided ozone oxidation process to form... The ultra-thin, dense silicon oxide passivation layer, combined with precisely controlled tunneling and doped polycrystalline silicon layer thicknesses, achieves excellent surface passivation and carrier transport performance. This process innovation not only solves the problem of limited effectiveness of traditional passivation films, but also significantly improves the open-circuit voltage and short-circuit current of the battery by optimizing the matching relationship of each functional layer, ultimately leading to a breakthrough improvement in photoelectric conversion efficiency. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the silicon wafer structure for a method of fabricating a back contact battery surface structure proposed in this invention;

[0033] Figure 2 This is a schematic diagram of Example 1 of the method for preparing a back contact battery surface structure according to the present invention;

[0034] Figure 3 This is a schematic diagram of Example 2 of the method for preparing a back contact battery surface structure according to the present invention;

[0035] Figure 4 This is a schematic diagram of Example 3 of the method for preparing a back contact battery surface structure proposed in this invention.

[0036] Legend: 1. Silicon wafer; 2. First tunneling layer; 3. First doped polysilicon layer; 4. Second tunneling layer; 5. Second doped polysilicon layer; 6. Specific textured structure; 7. Isolation base region; 8. Oxide layer; 9. Front passivation antireflection layer; 10. Back passivation layer; 11. Electrode. Detailed Implementation

[0037] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described below in conjunction with the accompanying drawings and embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0038] Numerous specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways than those described herein, and therefore the invention is not limited to the specific embodiments disclosed in the following specification.

[0039] Example 1, as Figure 1 and Figure 2 As shown, the present invention provides a method for preparing a back contact battery surface structure, which is obtained through the following steps:

[0040] S1. Double-sided polishing of the silicon wafer surface: First, rough polishing to remove the damaged layer on the silicon wafer surface, then cleaning with acid and ozone, followed by fine polishing, then cleaning with a mixture of hydrogen peroxide and alkali, then cleaning with ozone and acid, then cleaning with a mixture of acid and hydrogen peroxide, and finally washing with water and drying. Afterwards, a tunneling oxide layer and amorphous silicon are deposited sequentially on one side at high temperature; then, high-temperature diffusion is performed on this side to form the crystallized first semiconductor region and the mask layer BSG.

[0041] S2. A first pattern is formed by laser engraving on the mask layer BSG, and then the first pattern area is polished to form the base area;

[0042] S3. A tunneling oxide layer and amorphous silicon are sequentially deposited on one side of the base region at high temperature, and then diffused to form a crystallized second semiconductor region and a mask layer PSG.

[0043] S4. The mask layer PSG on the first semiconductor is removed by laser; the first semiconductor region and the second semiconductor region are formed on the back side at intervals.

[0044] S5. Etching: Remove the plating areas on the front and sides.

[0045] S6. Pile forming: A special pile structure is formed on the front side using a mixture of specially formulated pile additives and alkali.

[0046] S7. Laser engraving removes the mask area at the junction of the first semiconductor and the second semiconductor to form an isolation pattern;

[0047] S8. Polishing: A mixture of alkaline solution and polishing additives is used to remove the residual mask layer on the isolation pattern, forming an isolation base region. The isolation base region has a square tower-based structure, isolating the first semiconductor and the second semiconductor. Then, an acid solution is used to remove the mask layer BSG on the first semiconductor and the mask layer PSG on the second semiconductor.

[0048] S9. The ozone oxidation process forms a dense silicon oxide thin layer in a specific textured structure, an isolation base region, a first semiconductor region, and a second semiconductor region.

[0049] S10, front-side deposition of front-side passivation and anti-reflection layer.

[0050] S11, Backside passivation layer deposited.

[0051] S12. Electrodes are printed on the first semiconductor and the second semiconductor, and then sintered to form conductive electrodes.

[0052] Example 2, as Figure 3 As shown, a back contact battery surface structure is obtained through the following steps:

[0053] S1. Double-sided polishing of the silicon wafer surface: First, rough polishing to remove the damaged layer on the silicon wafer surface, then cleaning with acid and ozone, followed by fine polishing, then cleaning with a mixture of hydrogen peroxide and alkali, then cleaning with ozone and acid, then cleaning with a mixture of acid and hydrogen peroxide, and finally washing with water and drying. Afterwards, a tunneling oxide layer and amorphous silicon are deposited sequentially on one side at high temperature; then, high-temperature diffusion is performed on this side to form the crystallized first semiconductor region and the mask layer BSG.

[0054] S2. A first pattern is formed by laser engraving on the mask layer BSG, and then the first pattern area is polished to form the base area;

[0055] S3. A tunneling oxide layer and amorphous silicon are sequentially deposited on one side of the base region at high temperature, and then diffused to form a crystallized second semiconductor region and a mask layer PSG.

[0056] S4. The mask layer PSG on the first semiconductor is removed by laser; the first semiconductor region and the second semiconductor region are formed on the back side at intervals.

[0057] S5. Etching: Remove the plating areas on the front and sides.

[0058] S6. Texturing: An inverted pyramid textured surface structure is formed on the front side using a mixed solution of inverted pyramid additives and alkali. The inverted pyramid structure has a reflectivity of 8.5%, a width of 2.2 μm, and a height of 0.9 μm.

[0059] S7. Laser engraving removes the mask area at the junction of the first semiconductor and the second semiconductor to form an isolation pattern;

[0060] S8. Polishing: A mixture of alkaline solution and polishing additives is used to remove the residual mask layer on the isolation pattern, forming an isolation base region. The isolation base region has a square tower base structure with a width of 14µm and a reflectivity of 43%, isolating the first and second semiconductors. Then, an acid solution is used to remove the mask layer BSG on the first semiconductor and the mask layer PSG on the second semiconductor.

[0061] S9. The ozone oxidation process forms a dense silicon oxide thin layer in the inverted pyramid textured structure, the isolation base region, the first semiconductor region, and the second semiconductor region. The thickness of the silicon oxide thin layer is... The ozone concentration was 40 ppm.

[0062] S10, front-side deposition of front-side passivation and anti-reflection layer;

[0063] S11, Backside passivation layer deposited;

[0064] S12. Electrodes are printed on the first semiconductor and the second semiconductor, and then sintered to form conductive electrodes.

[0065] The concentration of sodium hydroxide was 8%, the concentration of polishing additive was 0.52%, the reaction time was 200 s, and the temperature was 80℃. The acid solution was hydrofluoric acid with a concentration of 6.5%, the reaction time was 350 s, and the temperature was 25℃.

[0066] The structure of the first semiconductor region consists of, in sequence, a silicon-based region, a first tunneling layer, a boron-doped polysilicon layer, and a thin silicon oxide layer. The structure of the second semiconductor region consists of, in sequence, a silicon-based region, a second tunneling layer, a phosphorus-doped polysilicon layer, and a thin silicon oxide layer. The structure of the isolation base region consists of, in sequence, an isolation base region and a thin silicon oxide layer.

[0067] The mask layer BSG has a thickness of 40 nm, and the mask layer PSG has a thickness of 50 nm. The first tunneling layer has a thickness of 1.2 nm, the boron-doped polysilicon layer has a thickness of 150 nm, the second tunneling layer has a thickness of 1.2 nm, and the phosphorus-doped polysilicon layer has a thickness of 200 nm.

[0068] Example 2 is basically the same as Example 1, except that in step S6, a mixed solution of inverted pyramid additive and alkali is used to form an inverted pyramid velvet structure on the front side.

[0069] Example 3, as Figure 4 As shown, based on Example 1, a back contact battery surface structure is obtained through the following steps:

[0070] S1. Double-sided polishing of the silicon wafer surface: First, rough polishing to remove the damaged layer on the silicon wafer surface, then cleaning with acid and ozone, followed by fine polishing, then cleaning with a mixture of hydrogen peroxide and alkali, then cleaning with ozone and acid, then cleaning with a mixture of acid and hydrogen peroxide, and finally washing with water and drying. Afterwards, a tunneling oxide layer and amorphous silicon are deposited sequentially on one side at high temperature; then, high-temperature diffusion is performed on this side to form the crystallized first semiconductor region and the mask layer BSG.

[0071] S2. A first pattern is formed by laser engraving on the mask layer BSG, and then the first pattern area is polished to form the base area;

[0072] S3. A tunneling oxide layer and amorphous silicon are sequentially deposited on one side of the base region at high temperature, and then diffused to form a crystallized second semiconductor region and a mask layer PSG.

[0073] S4. The mask layer PSG on the first semiconductor is removed by laser; the first semiconductor region and the second semiconductor region are formed on the back side at intervals.

[0074] S5. Etching: Remove the plating areas on the front and sides.

[0075] S6. Texturing: A mixed solution of chain-shaped inverted pyramid additives and alkali is used to form a chain-shaped inverted pyramid textured surface structure on the front side. The chain-shaped inverted pyramid structure has a reflectance of 7.2%, a width of 2.4 μm, and a height of 1.1 μm.

[0076] S7. Laser engraving removes the mask area at the junction of the first semiconductor and the second semiconductor to form an isolation pattern;

[0077] S8. Polishing: A mixture of alkaline solution and polishing additives is used to remove the residual mask layer on the isolation pattern, forming an isolation base region. The isolation base region has a square tower base structure with a width of 14µm and a reflectivity of 43%, isolating the first and second semiconductors. Then, an acid solution is used to remove the mask layer BSG on the first semiconductor and the mask layer PSG on the second semiconductor.

[0078] S9. The ozone oxidation process forms a dense silicon oxide thin layer in the chain-like inverted pyramid textured structure, the isolation base region, the first semiconductor region, and the second semiconductor region. The thickness of the silicon oxide thin layer is... The ozone concentration was 40 ppm.

[0079] S10, front-side deposition of front-side passivation and anti-reflection layer;

[0080] S11, Backside passivation layer deposited;

[0081] S12. Electrodes are printed on the first semiconductor and the second semiconductor, and then sintered to form conductive electrodes.

[0082] The concentration of sodium hydroxide was 8%, the concentration of polishing additive was 0.52%, the reaction time was 200 s, and the temperature was 80℃. The acid solution was hydrofluoric acid with a concentration of 6.5%, the reaction time was 350 s, and the temperature was 25℃.

[0083] The structure of the first semiconductor region consists of, in sequence, a silicon-based region, a first tunneling layer, a boron-doped polysilicon layer, and a thin silicon oxide layer. The structure of the second semiconductor region consists of, in sequence, a silicon-based region, a second tunneling layer, a phosphorus-doped polysilicon layer, and a thin silicon oxide layer. The structure of the isolation base region consists of, in sequence, an isolation base region and a thin silicon oxide layer.

[0084] The mask layer BSG has a thickness of 40 nm, and the mask layer PSG has a thickness of 50 nm. The first tunneling layer has a thickness of 1.2 nm, the boron-doped polysilicon layer has a thickness of 150 nm, the second tunneling layer has a thickness of 1.2 nm, and the phosphorus-doped polysilicon layer has a thickness of 200 nm.

[0085] Example 3 is basically the same as Example 1, except that in step S6, a mixed solution of chain-like inverted pyramid additive and alkali is used to form a chain-like inverted pyramid velvet structure on the front side.

[0086] Comparative Example 1:

[0087] The method is the same as in Example 1, except that: S8, texturing, uses a mixture of alkaline solution and conventional texturing additives to remove the residual mask layer on the isolation pattern, forming a positive pyramid structure isolation base region to isolate the first semiconductor and the second semiconductor. Then, an acid solution is used to remove the mask layer BSG on the first semiconductor and the mask layer PSG on the second semiconductor; S9, ozone oxidation process, is omitted.

[0088] Test case

[0089] The performance of the back contact batteries obtained in the above embodiments and comparative examples was tested, and the results are shown in the table.

[0090]

[0091] The results above show that, compared to Comparative Example 1, the embodiment of the present invention can form a specific textured surface morphology on the front side and a square tower-based structure in the back isolation base region. The ozone oxidation process forms a dense silicon oxide thin layer in the specific textured surface structure, the isolation base region, the first semiconductor region, and the second semiconductor region. This is beneficial for reducing the reflectivity of the front side and increasing the reflectivity of the back isolation base region, while enhancing the passivation performance of both the front and back sides, thereby improving the open-circuit voltage, short-circuit current, and battery efficiency.

[0092] Furthermore, as can be seen from Examples 1-3, the preferred embodiment of the present invention is more conducive to improving open-circuit voltage, short-circuit current, and battery efficiency.

[0093] Its overall working principle is as follows: 1. Optical management mechanism: The specific textured structure on the front of the battery significantly extends the propagation path of incident light in the silicon material through multiple light scattering. This micro-nano structure can achieve anti-reflection effect in a wide spectral range, controlling the front reflectivity at an excellent level of 5% to 11%. At the same time, the high reflectivity of the square tower base isolation area on the back effectively reflects unabsorbed long-wavelength photons back to the silicon wafer, achieving secondary light absorption.

[0094] 2. Carrier separation and transport mechanism: Selective carrier transport is achieved through a precisely controlled tunneling oxide layer, allowing majority carriers to tunnel through while blocking recombination of minority carriers. The boron-doped and phosphorus-doped polycrystalline silicon layers form a high-quality PN junction region, which generates a strong built-in electric field under illumination, enabling efficient separation and collection of photogenerated carriers.

[0095] 3. Surface passivation mechanism: The innovative ozone oxidation process... A dense silicon oxide layer is formed at an ultra-thin scale, effectively saturating the dangling bonds on the silicon surface and reducing the interface state density. This atomic-level passivation layer significantly reduces surface recombination losses while maintaining excellent carrier transport characteristics. Combined with functionalized passivation layers on the front and back sides, it achieves an all-round surface passivation effect.

[0096] 4. Electrical contact mechanism: The P-type and N-type semiconductor regions spaced apart on the back side achieve selective contact through optimized electrode design. The sintered metal electrode forms a good ohmic contact with the doped polycrystalline silicon layer, ensuring efficient carrier extraction while minimizing losses caused by contact resistance.

[0097] 5. Process synergy mechanism: Each process step achieves synergistic optimization through precise parameter control. In particular, the ozone oxidation process and the subsequent passivation layer deposition form a good interface match, ensuring the integrity and stability of the entire device structure. This process synergy allows the performance of each functional layer to be fully utilized, ultimately achieving an overall improvement in battery efficiency.

[0098] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments that can be applied to other fields. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A method for preparing a back contact battery surface structure, characterized in that, Includes the following steps: S1. Double-sided polishing of the silicon wafer surface: First, rough polishing to remove the damaged layer on the silicon wafer surface, then cleaning with acid and ozone, then fine polishing, then cleaning with a mixture of hydrogen peroxide and alkali, then cleaning with ozone and acid, then cleaning with a mixture of acid and hydrogen peroxide, and finally washing with water and drying; then high-temperature deposition of tunneling oxide layer and amorphous silicon on one side; then high-temperature diffusion to form the crystallized first semiconductor region and mask layer BSG on this side; S2. A first pattern is formed by laser engraving on the mask layer BSG, and then the first pattern area is polished to form the base area; S3. A tunneling oxide layer and amorphous silicon are sequentially deposited on one side of the base region at high temperature, and then diffused to form a crystallized second semiconductor region and a mask layer PSG. S4. The mask layer PSG on the first semiconductor is removed by laser; the first semiconductor region and the second semiconductor region are formed on the back side at intervals. S5. Etching: Remove the plating areas on the front and sides. S6. Pile forming: A special pile structure is formed on the front side using a mixture of specially formulated pile additives and alkali. S7. Laser engraving removes the mask area at the junction of the first semiconductor and the second semiconductor to form an isolation pattern; S8. Polishing: A mixture of alkaline solution and polishing additive is used to remove the residual mask layer on the isolation pattern to form an isolation base region. The isolation base region has a square tower base structure to isolate the first semiconductor and the second semiconductor. Then, an acid solution is used to remove the mask layer BSG on the first semiconductor and the mask layer PSG on the second semiconductor. S9. The ozone oxidation process forms a dense silicon oxide thin layer in a specific textured structure, isolation base region, first semiconductor region and second semiconductor region. S10, front-side deposition of front-side passivation and anti-reflection layer; S11, Backside passivation layer deposited; S12. Electrodes are printed on the first semiconductor and the second semiconductor, and then sintered to form conductive electrodes.

2. The method for preparing a back contact battery surface structure according to claim 1, characterized in that: The reflectivity of the upright pyramid structure is 9%–11%, the reflectivity of the inverted pyramid structure is 7%–9%, ​​and the reflectivity of the chain pyramid structure is 5%–8%.

3. The method for preparing a back contact battery surface structure according to claim 2, characterized in that: The width of the upright pyramid is 0.8-2.3 μm and the height is 0.5-1.3 μm; the width of the inverted pyramid is 1.0-2.3 μm and the height is 0.6-1.5 μm; and the width of the chain pyramid is 1.2-2.5 μm and the height is 0.7-1.8 μm.

4. The method for preparing a back contact battery surface structure according to claim 1, characterized in that: The isolation base area is in the shape of a square tower base, with a width of 10-15 μm.

5. The method for preparing a back contact battery surface structure according to claim 1, characterized in that: The reflectivity of the isolation base region is 40%–45%.

6. The method for preparing a back contact battery surface structure according to claim 1, characterized in that: The sodium hydroxide has a volume concentration of 5% to 10%, the additive concentration is 0% to 1%, the reaction time is 50 to 200 s, and the temperature is 70 to 90 ℃; the acid solution is hydrofluoric acid, the concentration of the hydrofluoric acid solution is 2% to 8%, the reaction time is 200 to 400 s, and the temperature is 25 ℃.

7. The method for preparing a back contact battery surface structure according to claim 1, characterized in that: The ozone concentration in the ozone oxidation process is 20-60 ppm.

8. The method for preparing a back contact battery surface structure according to claim 1, characterized in that: The thickness of the silicon oxide thin layer is 9. The method for preparing a back contact battery surface structure according to claim 1, characterized in that: The first semiconductor region has a structure consisting of a silicon-based region, a first tunneling layer, a boron-doped polycrystalline silicon layer, and a thin silicon oxide layer, in sequence; the second semiconductor region has a structure consisting of a silicon-based region, a first tunneling layer, a phosphorus-doped polycrystalline silicon layer, and a thin silicon oxide layer, in sequence; and the isolation base region has a structure consisting of a silicon-based region and a thin silicon oxide layer, in sequence.

10. The method for preparing a back contact battery surface structure according to claim 1, characterized in that: The thickness of the mask layer BSG is 10-100nm, the thickness of the mask layer PSG is 10-100nm, the thickness of the first tunneling layer is 0.5-2nm, the thickness of the boron-doped polysilicon layer is 100-500nm, and the thickness of the phosphorus-doped polysilicon layer is 100-500nm.

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