Low dropout regulator and chip

Abstract

The embodiment of the invention provides a low-dropout linear voltage regulator and a chip. The voltage regulator comprises an error amplifier, a target transistor, a target capacitor and a sampling unit, the error amplifier comprises a blocking element, the first end of the blocking element is connected with the grid electrode of the target transistor through the output end of the error amplifier, the second end of the blocking element is connected with the first end of the target capacitor, and the blocking element is used for receiving a constant voltage signal. The blocking element is a one-way conduction element under the action of the constant voltage signal; the source electrode of the target transistor is connected with a power supply, and the drain electrode of the target transistor is the output end of the voltage stabilizer; the second end of the target capacitor is connected with the drain electrode of the target transistor; and the sampling unit is connected with the drain electrode of the target transistor and the error amplifier, and inputs a feedback signal to the error amplifier according to the output voltage of the voltage stabilizer so as to control the voltage value of the output voltage of the voltage stabilizer to be within the target voltage range. According to the scheme, the transient response performance of the voltage stabilizer is optimized.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of voltage stabilizers, and in particular to a low-dropout linear voltage regulator and a chip. BACKGROUND

[0002] A low-dropout linear voltage regulator (LDO) is a new generation of integrated circuit voltage regulator, which can maintain a relatively stable output voltage and is suitable for application scenarios with high requirements for power supply stability.

[0003] The current LDO includes a power tube and an amplifier, the gate of the power tube is connected with the output end of the amplifier, the source of the power tube is connected to a power supply, the drain of the power tube is connected to the input end of the amplifier through a feedback circuit structure, the drain of the power tube is the output end of the LDO, and a capacitor for stabilizing the power tube is connected between the gate and the drain of the power tube; during use of the LDO, when the voltage of the output end of the LDO changes, the feedback circuit structure can feed back the change to the amplifier, so that the power tube adjusts the voltage output by the LDO, and thus the voltage output by the LDO can be relatively stable.

[0004] However, due to the Miller effect of the capacitor, the gate voltage of the power tube changes slowly when the power supply jumps, so that the speed of the LDO adjusting the output voltage is slow, and the transient response performance of the LDO is poor. SUMMARY

[0005] Therefore, embodiments of the present application provide a low-dropout linear voltage regulator and a chip to at least partially solve the above problems.

[0006] In a first aspect, an embodiment of the present application provides a low-dropout linear voltage regulator, comprising: an error amplifier, a target transistor, a target capacitor and a sampling unit; the error amplifier comprises a blocking element, a first end of the blocking element is connected with a gate of the target transistor through an output end of the error amplifier, a second end of the blocking element is connected with a first end of the target capacitor, the blocking element is an element for receiving a constant voltage signal, and the blocking element is a unidirectional conduction element under the action of the constant voltage signal, a unidirectional conduction direction of the blocking element is a direction from the first end of the blocking element to the second end of the blocking element; a source of the target transistor is connected with a power supply, a drain of the target transistor is an output end of the voltage regulator; a second end of the target capacitor is connected with the drain of the target transistor; the sampling unit is connected with the drain of the target transistor and the error amplifier, and is used for inputting a feedback signal to the error amplifier according to an output voltage of the voltage regulator, so that the error amplifier outputs a voltage to the gate of the target transistor according to the feedback signal, and controls a voltage value of the output voltage of the voltage regulator to be in a target voltage range.

[0007] In a second aspect, an embodiment of the present application provides a chip, comprising the voltage regulator in the first aspect.

[0008] According to the low-dropout linear voltage regulator provided in the embodiment of the present application, by using the error amplifier comprising the blocking element in the voltage regulator, the blocking element can block between the gate of the target transistor and the target capacitor. Since the blocking element is a unidirectional conduction element, the unidirectional conduction direction of the blocking element is from the first end of the blocking element to the second end of the blocking element, the first end of the blocking element is connected with the gate of the target transistor, and the second end of the blocking element is connected with the target capacitor, the blocking element can make the target capacitor and the target transistor not have a return path from the target capacitor to the target transistor, and thus, when the power supply jumps, the interference factor of the change of the gate voltage of the target transistor is less, so that the speed of the voltage regulator for adjusting the output voltage is accelerated, and the transient response performance of the voltage regulator is optimized. BRIEF DESCRIPTION OF DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments described in the embodiments of the present application, and other drawings can also be obtained by those skilled in the art according to these drawings.

[0010] Figure 1 is a schematic diagram of a low-dropout linear voltage regulator in an embodiment of the present application;

[0011] Figure 2 is a circuit diagram of a low-dropout linear regulator according to an embodiment of the present application;

[0012] Figure 3 is a circuit diagram of a low-dropout linear regulator according to another embodiment of the present application;

[0013] Figure 4 is a circuit diagram of a low-dropout linear regulator according to yet another embodiment of the present application;

[0014] Figure 5 is a circuit diagram of a low-dropout linear regulator according to still another embodiment of the present application;

[0015] Figure 6 is a circuit diagram of a pre-charge unit according to an embodiment of the present application;

[0016] Figure 7 is a circuit diagram of a low-dropout linear regulator in a first state according to an embodiment of the present application. DETAILED DESCRIPTION

[0017] Embodiments of the present application provide a low-dropout linear regulator and a chip, which are described in detail below through multiple embodiments.

[0018] Figure 1 is a schematic diagram of a low-dropout linear regulator according to an embodiment of the present application, as shown in Figure 1 The low-dropout linear regulator includes an error amplifier, a target transistor, a target capacitor, and a sampling unit. The error amplifier includes a blocking element. A first end of the blocking element is connected to a gate of the target transistor through an output end of the error amplifier. A second end of the blocking element is connected to a first end of the target capacitor. The blocking element is an element for receiving a constant voltage signal, and is a unidirectional conduction element under the action of the constant voltage signal. The unidirectional conduction direction of the blocking element is from the first end of the blocking element to the second end of the blocking element. A source of the target transistor is connected to a power supply. A drain of the target transistor is an output end of the low-dropout linear regulator. A second end of the target capacitor is connected to the drain of the target transistor. The sampling unit is connected to the drain of the target transistor and the error amplifier, and is configured to input a feedback signal to the error amplifier according to an output voltage of the low-dropout linear regulator, so that the error amplifier outputs a voltage to the gate of the target transistor according to the feedback signal, to control the voltage value of the output voltage of the low-dropout linear regulator to be within a target voltage range.

[0019] In the low-dropout linear regulator, the target capacitor is connected to the drain of the target transistor, and the sampling unit is connected to the drain of the target transistor and the error amplifier. Figure 1In the figure, A is an error amplifier, Mpower is a target transistor, Cc is a target capacitor, VDD is a power supply, V1 is an inverting input end of the error amplifier for receiving a reference voltage, a specific value of the reference voltage can be set according to actual requirements, and the embodiment of the application does not limit the specific value of the reference voltage, VO is an output end of the error amplifier, a dashed line is used to represent the connection relationship inside A, H is a sampling unit, which is a circuit structure unit of the voltage regulator except the error amplifier, the target transistor and the target capacitor, and is used to input a feedback signal to a non-inverting input end of the error amplifier according to an output voltage of the voltage regulator; a target voltage range can be set according to actual requirements, and the embodiment of the application does not limit the target voltage range.

[0020] In the embodiment of the application, by using the error amplifier including the blocking element in the voltage regulator, the blocking element can block between the gate of the target transistor and the target capacitor. Since the blocking element is a unidirectional conduction element, the unidirectional conduction direction of the blocking element is from the first end to the second end of the blocking element, the first end of the blocking element is connected to the gate of the target transistor, and the second end of the blocking element is connected to the target capacitor, the blocking element can make the target capacitor and the target transistor not have a return path from the target capacitor to the target transistor, and thus, when the power supply jumps, the change of the gate voltage of the target transistor has fewer interference factors, so that the speed of the voltage regulator for adjusting the output voltage is accelerated, and the transient response performance of the voltage regulator is optimized.

[0021] Further, since the blocking element works under the action of the constant voltage signal, the possibility of the blocking element not working normally can be reduced, so that the transient response performance of the voltage regulator is better and more stable.

[0022] In a possible implementation, the blocking element is an N-type metal oxide semiconductor field effect transistor (NMOS), so that the structure of the blocking element is simple and the cost is low.

[0023] In a possible implementation, the gate of the blocking element is used to receive the constant voltage signal, the constant voltage signal is used to control the blocking element to work in the saturation region, the first end of the blocking element is the drain of the blocking element, and the second end of the blocking element is the source of the blocking element.

[0024] The specific voltage value of the constant voltage signal is set according to the specific model and use scenario of the blocking element, and the embodiment of the application does not limit the specific voltage value of the constant voltage signal.

[0025] Therefore, the constant voltage signal can make the blocking element work in the saturation region, so that the blocking element is in a more stable working state.

[0026] In a possible implementation, as shown in FIG. 2, the voltage regulator includes a blocking element 1, an error amplifier 2, a target transistor 3, a target capacitor 4, a sampling unit 5, a power supply 6 and a reference voltage 7. Figure 2As shown, the voltage output by the sampling unit is positively correlated with the voltage output by the regulator; the error amplifier also includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor and the second transistor are both P-type metal-oxide-semiconductor field-effect transistors, and the third transistor, the fourth transistor, and the fifth transistor are all N-type metal-oxide-semiconductor field-effect transistors.

[0027] The gate of the first transistor is connected to the gate of the second transistor, and the gate of the first transistor is connected to the drain of the first transistor. The source of the first transistor is connected to the power supply, and the drain of the first transistor is connected to the drain of the third transistor. The source of the second transistor is connected to the power supply, and the drain of the second transistor is connected to the drain of the blocking element. The gate of the third transistor is used to receive a constant voltage signal, and the source of the third transistor is connected to the drain of the fourth transistor. The gate of the fourth transistor is connected to the output terminal of the sampling unit, and the source of the fourth transistor is connected to the source of the fifth transistor. The connection node between the source of the fourth transistor and the source of the fifth transistor is the tail current port of the error amplifier used to output the tail current. The gate of the fifth transistor is used to receive the first reference voltage, and the drain of the fifth transistor is connected to the source of the blocking element.

[0028] Among them, Figure 2 In this application, A, Mpower, Cc, VDD, V1 and VO have been introduced above and will not be repeated here. MN0 is a blocking element, V2 is the gate of the blocking element, used to receive the constant voltage signal VB, MP1 is the first transistor, MP2 is the second transistor, MN3 is the third transistor, MN4 is the fourth transistor, MN5 is the fifth transistor, VREF1 is the first reference voltage, and V3 is the tail current port.

[0029] In this embodiment, the blocking element inserted before the target capacitor is equivalent to a current buffer, which blocks the feedforward path and eliminates the influence of the right zero point. Furthermore, the blocking element in the voltage regulator with the above circuit structure can increase the pole at the output terminal of the voltage regulator, thereby increasing the gain-bandwidth product of the voltage regulator, improving the speed at which the voltage regulator adjusts the output voltage, and further optimizing the transient response performance of the voltage regulator.

[0030] Meanwhile, in this embodiment, the fourth and fifth transistors are independently biased by a constant voltage signal. This ensures that when the load current of the voltage regulator changes significantly, or when there is a process deviation in the voltage regulator, or when the first reference voltage of the voltage regulator changes, the blocking element and the third transistor can still remain within the normal bias range. This helps to ensure that the blocking element and the third transistor work normally and improves the stability of the voltage regulator.

[0031] In another possible implementation, such as Figure 3As shown, the voltage output by the sampling unit is positively correlated with the voltage output by the voltage stabilizer; the error amplifier further comprises a first tube, a second tube, a third tube, a fourth tube, a fifth tube, a sixth tube, a seventh tube and an eighth tube, the first tube, the second tube, the third tube and the fourth tube are all P-type metal oxide semiconductor field effect transistors, and the fifth tube, the sixth tube, the seventh tube and the eighth tube are all N-type metal oxide semiconductor field effect transistors.

[0032] The source of the first tube, the source of the second tube, the source of the third tube and the source of the fourth tube are respectively connected to a power supply; the gate of the first tube is connected to the gate of the second tube, and the drain of the first tube is connected to the drain of the fifth tube; the gate of the second tube is connected to the drain of the second tube, and the drain of the second tube is connected to the drain of the seventh tube; the gate of the third tube is connected to the gate of the fourth tube, and the gate of the third tube is connected to the drain of the third tube, and the drain of the third tube is connected to the drain of the eighth tube; the source of the fourth tube is connected to the drain of the blocking element; the gate of the fifth tube is connected to the gate of the sixth tube, and the source of the fifth tube is grounded; the drain of the sixth tube is connected to the source of the blocking element, and the source of the sixth tube is grounded; the gate of the seventh tube is used for receiving a second reference voltage, the source of the seventh tube is connected to the source of the eighth tube, and the connection node of the source of the seventh tube and the source of the eighth tube is a tail current port of the error amplifier used for outputting a tail current; the gate of the eighth tube is connected to the output end of the sampling unit.

[0033] In the formula, A, Mpower, Cc, VDD, V1, VO, MN0, V2, VB and V3 have been introduced above, and will not be described herein again, mp1 is the first tube, mp2 is the second tube, mp3 is the third tube, mp4 is the fourth tube, mn5 is the fifth tube, mn6 is the sixth tube, mn7 is the seventh tube, mn8 is the eighth tube, and VREF2 is the second reference voltage. Figure 3 In the embodiment of the present application, the output voltage swing of the error amplifier is (vdsn6+vdsn0, vdd-vdsp4), wherein vdsn6 is the drain-source voltage of the sixth tube, vdsn0 is the drain-source voltage of the blocking element, vdd is the output voltage of the power supply, and vdsn4 is the drain-source voltage of the fourth tube, that is, the minimum voltage of the gate of the target transistor can be as low as vdsn6+vdsn0, and vdsn6+vdsn0 is generally about 200 millivolts, and further, the minimum voltage of the gate of the target transistor is small, so that the variation range of the load current of the voltage stabilizer is expanded, and the bias flexibility is improved.

[0034] In addition, in the embodiment of the present application, one pole point corresponding to the voltage stabilizer is:

[0035]

[0036] ​

[0037] Wherein, p2,3 is a conjugate pole, gm2 is a transconductance of the target transistor, gm3 is a transconductance of the blocking element, cl is a capacitance value of a capacitor connected to an output terminal of the voltage regulator (for example, the output capacitor CL below), cgg is a gate capacitance of the target transistor, and the gain-bandwidth product GBW of the voltage regulator is gm1 / cc, wherein gm1 is a transconductance of the seventh and eighth pipe bodies, and cc is a capacitance value of the target capacitor. Thus, the conjugate pole and the gain-bandwidth product of the voltage regulator in the embodiment of the present application are both large, so that the speed of the voltage regulator in adjusting the output voltage is accelerated, and the transient response performance of the voltage regulator is optimized.

[0038] In a possible implementation, as shown in Figure 4 and Figure 5 , the voltage regulator further comprises a control unit and a compensation capacitor; a first end of the compensation capacitor is connected to the first end of the target capacitor through the control unit, and a second end of the compensation capacitor is connected to the second end of the target capacitor; the control unit is configured to control the first end of the compensation capacitor and the first end of the target capacitor to be disconnected when the voltage regulator is in a first state, and control the first end of the compensation capacitor and the first end of the target capacitor to be connected when the voltage regulator is in a second state.

[0039] Wherein, the load current of the voltage regulator in the first state is greater than the load current of the voltage regulator in the second state, for example, the first state is a load state, and the second state is an unloaded state, in Figure 4 and Figure 5 , KT is the control unit, and CC is the compensation capacitor.

[0040] In the embodiment of the present application, when the voltage regulator is in the second state, the control unit is controlled to connect the compensation capacitor in parallel with the target capacitor, so as to compensate the capacitance value of the target capacitor, reduce the pole corresponding to the gate of the target transistor and the gain-bandwidth product of the voltage regulator, and make the voltage regulator more stable while reducing the power consumption; when the voltage regulator is in the first state, the control unit is controlled to disconnect the branch in which the compensation capacitor is located, so that the compensation capacitor no longer compensates the target capacitor, the gain-bandwidth product is increased, and the transient response performance of the voltage regulator is improved.

[0041] In a possible implementation, as shown in Figure 4 and Figure 5 , the control unit comprises a first switch; a first end of the first switch is connected to the first end of the target capacitor, and a second end of the first switch is connected to the first end of the compensation capacitor; the first switch is configured to be opened when the voltage regulator is in the first state, and closed when the voltage regulator is in the second state, so that the structure of the control unit is relatively simple.

[0042] Wherein, in Figure 4 andFigure 5 K1 is the first switch.

[0043] In a possible implementation, as shown in Figure 4 , Figure 5 the voltage stabilizer further comprises a pre-charge unit; the pre-charge unit is connected to the first end of the compensation capacitor through the control unit, and the control unit is further configured to control the pre-charge unit to charge the compensation capacitor when the voltage stabilizer is in the first state, so that the voltage at the first end of the compensation capacitor is equal to the voltage at the first end of the target capacitor.

[0044] In the embodiment of the present application, the pre-charge unit can charge the compensation capacitor when the voltage stabilizer is in the first state, so as to reduce the possibility that the compensation capacitor charging at the moment when the first switch is closed causes the abnormal voltage at the gate of the target transistor, and improve the stability of the voltage stabilizer.

[0045] In a possible implementation, as shown in Figure 4 , Figure 5 , Figure 6 the control unit further comprises a second switch, and the pre-charge unit comprises a first resistor and a second resistor; the first end of the second switch is connected to the first end of the compensation capacitor, the second end of the second switch is connected to the first end of the first resistor, and the second end of the second switch is connected to the first end of the second resistor; the second switch is configured to be closed when the voltage stabilizer is in the first state, and to be opened when the voltage stabilizer is in the second state; the second end of the first resistor is connected to the power supply; and the second end of the second resistor is grounded.

[0046] In the above Figure 4 , Figure 5 , Figure 6 , K2 is the second switch, R1 is the first resistor, R2 is the second resistor, and a is the first end of the second switch.

[0047] The pre-charge unit is configured to charge the compensation capacitor when the voltage stabilizer is in the first state, so that the voltage at the first end of the compensation capacitor is equal to the voltage at the first end of the target capacitor. This can be achieved by controlling the time when the second switch is closed, or by selecting a first resistor and a second resistor with appropriate resistance values. The embodiment of the present application does not limit this.

[0048] Thus, the pre-charge unit has a simple structure, is easy to implement, and has a low cost.

[0049] In a possible implementation, as shown in Figure 2 , Figure 3 , Figure 4 , and Figure 5As shown in the error amplifier further comprises a sixth transistor and a seventh transistor, both of which are N-type metal oxide semiconductor field effect transistors; the gate of the sixth transistor is connected with the gate of the seventh transistor, the drain of the sixth transistor is connected with the tail current port, and the source of the sixth transistor is grounded; the gate of the seventh transistor is connected with the drain of the seventh transistor, the drain of the seventh transistor is connected with a bias current source, and the source of the seventh transistor is grounded, so that the sixth transistor and the seventh transistor can bias the current path of the error amplifier and the tail current.

[0050] wherein, Figure 2 , Figure 3 , Figure 4 and Figure 5 MN6 is the sixth transistor, MN7 is the seventh transistor, and IB is the bias current source.

[0051] In a possible implementation, as shown in Figure 2 , Figure 3 , Figure 4 and Figure 5 , the sampling unit comprises a third resistor and a fourth resistor; the first end of the third resistor is connected with the drain of the target transistor, the second end of the third resistor is connected with the first end of the fourth resistor, the connection node of the second end of the third resistor and the first end of the fourth resistor is the output end of the sampling unit, and the second end of the fourth resistor is grounded, so as to realize that the voltage output by the sampling unit is positively correlated with the voltage output by the voltage stabilizer.

[0052] wherein, Figure 2 , Figure 3 , Figure 4 and Figure 5 R3 is the third resistor, and R4 is the fourth resistor.

[0053] Optionally, the output end of the voltage stabilizer can be connected with an output capacitor grounded, and the voltage stabilizer is taken as an example in the above Figure 5 , the output end of the voltage stabilizer is connected with an output capacitor, the first end of the output capacitor is connected with the output end of the voltage stabilizer, and the second end of the output capacitor is grounded, so as to obtain the voltage stabilizer as shown in Figure 7 .

[0054] wherein, Figure 7 CL is the output capacitor.

[0055] Optionally, the voltage stabilizer in the first state is that the output end of the voltage stabilizer is connected with a load, and the voltage stabilizer in the second state is that the output end of the voltage stabilizer is not connected with a load, for example, as shown in Figure 7 , the output end of the voltage stabilizer is connected with a load current source ILOAD, one end of ILOAD is connected with the output end of the voltage stabilizer, and the other end is grounded, so that the voltage stabilizer is in the first state.

[0056] The application further provides a chip comprising the voltage stabilizer.

[0057] It should be noted that the chip of the embodiment comprises the voltage stabilizer in the foregoing embodiment and has corresponding beneficial effects, which are not described herein again.

[0058] It should be noted that, in this document, the terms such as first and second are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0059] Not all steps and modules in the above flowcharts and system structure diagrams are necessary, and some steps or modules can be ignored according to actual needs. The execution order of each step is not fixed and can be adjusted as needed. The system structure described in each of the above embodiments can be a physical structure or a logical structure, that is, some modules can be implemented by the same physical entity, or some modules can be implemented by multiple physical entities, or can be implemented by some components in multiple independent devices.

[0060] In each of the above embodiments, a hardware module can be implemented mechanically or electrically. For example, a hardware module can include a permanent and dedicated circuit or logic (such as a dedicated processor, FPGA or ASIC) to complete the corresponding operation. A hardware module can also include programmable logic or circuit (such as a general-purpose processor or other programmable processor), which can be temporarily set by software to complete the corresponding operation. The specific implementation method (mechanical method, or dedicated permanent circuit, or temporarily set circuit) can be determined based on cost and time considerations.

[0061] The application has been described in detail above through the accompanying drawings and preferred embodiments, however, the application is not limited to these disclosed embodiments, and based on the above multiple embodiments, those skilled in the art can know that the code review means in different embodiments can be combined to obtain more embodiments of the application, and these embodiments are also within the protection scope of the application.

Claims

1. A low-dropout linear regulator, characterized in that, include: Error amplifier, target transistor, target capacitor, and sampling unit; The error amplifier includes a blocking element. The first end of the blocking element is connected to the gate of the target transistor through the output terminal of the error amplifier. The second end of the blocking element is connected to the first end of the target capacitor. The blocking element is a component for receiving a constant voltage signal, and the blocking element is a unidirectional conducting element under the action of the constant voltage signal. The unidirectional conducting direction of the blocking element is from the first end of the blocking element to the second end of the blocking element. The source of the target transistor is connected to a power supply, and the drain of the target transistor is the output terminal of the voltage regulator. The second terminal of the target capacitor is connected to the drain of the target transistor; The sampling unit is connected to the drain of the target transistor and to the error amplifier. It is used to input a feedback signal to the error amplifier according to the output voltage of the regulator, so that the error amplifier outputs a voltage to the gate of the target transistor according to the feedback signal, thereby controlling the output voltage of the regulator to be within the target voltage range.

2. The voltage regulator according to claim 1, characterized in that, The blocking element is an N-type metal-oxide-semiconductor field-effect transistor.

3. The voltage regulator according to claim 2, characterized in that, The gate of the blocking element is used to receive the constant voltage signal, which is used to control the blocking element to operate in the saturation region. The first end of the blocking element is the drain of the blocking element, and the second end of the blocking element is the source of the blocking element.

4. The voltage regulator according to claim 3, characterized in that, The voltage output by the sampling unit is positively correlated with the voltage output by the regulator; the error amplifier further includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor, wherein the first transistor and the second transistor are both P-type metal-oxide-semiconductor field-effect transistors, and the third transistor, the fourth transistor, and the fifth transistor are all N-type metal-oxide-semiconductor field-effect transistors. The gate of the first transistor is connected to the gate of the second transistor, and the gate of the first transistor is connected to the drain of the first transistor. The source of the first transistor is connected to the power supply, and the drain of the first transistor is connected to the drain of the third transistor. The source of the second transistor is connected to the power supply, and the drain of the second transistor is connected to the drain of the blocking element; The gate of the third transistor is used to receive the constant voltage signal, and the source of the third transistor is connected to the drain of the fourth transistor. The gate of the fourth transistor is connected to the output terminal of the sampling unit, and the source of the fourth transistor is connected to the source of the fifth transistor. The connection node between the source of the fourth transistor and the source of the fifth transistor is the tail current port of the error amplifier for outputting the tail current. The gate of the fifth transistor is used to receive the first reference voltage, and the drain of the fifth transistor is connected to the source of the blocking element.

5. The voltage regulator according to claim 3, characterized in that, The voltage output by the sampling unit is positively correlated with the voltage output by the regulator; the error amplifier further includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are all P-type metal-oxide-semiconductor field-effect transistors, and the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all N-type metal-oxide-semiconductor field-effect transistors; The sources of the first, second, third, and fourth transistors are respectively connected to the power supply; the gate of the first transistor is connected to the gate of the second transistor, and the drain of the first transistor is connected to the drain of the fifth transistor; the gate of the second transistor is connected to the drain of the second transistor, and the drain of the second transistor is connected to the drain of the seventh transistor; the gate of the third transistor is connected to the gate of the fourth transistor, and the gate of the third transistor is connected to the drain of the third transistor, and the drain of the third transistor is connected to the drain of the eighth transistor; the source of the fourth transistor is connected to the drain of the blocking element. The gate of the fifth transistor is connected to the gate of the sixth transistor, and the source of the fifth transistor is grounded; the drain of the sixth transistor is connected to the source of the blocking element, and the source of the sixth transistor is grounded; the gate of the seventh transistor is used to receive the second reference voltage, and the source of the seventh transistor is connected to the source of the eighth transistor. The connection node between the source of the seventh transistor and the source of the eighth transistor is the tail current port of the error amplifier for outputting the tail current; The gate of the eighth transistor is connected to the output terminal of the sampling unit.

6. The voltage regulator according to claim 4 or 5, characterized in that, The voltage regulator also includes a control unit and a compensation capacitor; The first terminal of the compensation capacitor is connected to the first terminal of the target capacitor through the control unit, and the second terminal of the compensation capacitor is connected to the second terminal of the target capacitor. The control unit is used to disconnect the circuit between the first terminal of the compensation capacitor and the first terminal of the target capacitor when the voltage regulator is in the first state, and to connect the first segment of the compensation capacitor and the first terminal of the target capacitor when the voltage regulator is in the second state, wherein the load current when the voltage regulator is in the first state is greater than the load current when the voltage regulator is in the second state.

7. The voltage regulator according to claim 6, characterized in that, The control unit includes a first switch; The first terminal of the first switch is connected to the first terminal of the target capacitor, and the second terminal of the first switch is connected to the first terminal of the compensation capacitor. The first switch is used to open when the voltage regulator is in a first state and close when the voltage regulator is in a second state.

8. The voltage regulator according to claim 7, characterized in that, The voltage regulator also includes a pre-charge unit; The pre-charging unit is connected to the first terminal of the compensation capacitor through the control unit. The control unit is also used to control the pre-charging unit to charge the compensation capacitor when the voltage regulator is in the first state, so that the voltage at the first terminal of the compensation capacitor is equal to the voltage at the first terminal of the target capacitor.

9. The voltage regulator according to claim 8, characterized in that, The control unit further includes a second switch, and the pre-charging unit includes a first resistor and a second resistor; The first end of the second switch is connected to the first end of the compensation capacitor, the second end of the second switch is connected to the first end of the first resistor, and the second end of the second switch is connected to the first end of the second resistor. The second switch is used to close when the voltage regulator is in the first state and open when the voltage regulator is in the second state. The second end of the first resistor is connected to the power supply; The second terminal of the second resistor is grounded.

10. The voltage regulator according to claim 4 or 5, characterized in that, The error amplifier further includes a sixth transistor and a seventh transistor, both of which are N-type metal-oxide-semiconductor field-effect transistors; The gate of the sixth transistor is connected to the gate of the seventh transistor, the drain of the sixth transistor is connected to the tail current port, and the source of the sixth transistor is grounded. The gate of the seventh transistor is connected to the drain of the seventh transistor, the drain of the seventh transistor is connected to a bias current source, and the source of the seventh transistor is grounded.

11. The voltage regulator according to claim 4 or 5, characterized in that, The sampling unit includes a third resistor and a fourth resistor; The first end of the third resistor is connected to the drain of the target transistor, the second end of the third resistor is connected to the first end of the fourth resistor, the connection node between the second end of the third resistor and the first end of the fourth resistor is the output terminal of the sampling unit, and the second end of the fourth resistor is grounded.

12. A chip, characterized in that, Includes the voltage regulator as described in any one of claims 1-11.

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