Verification platform code checking method and device, electronic equipment and storage medium

Abstract

The invention discloses a verification platform code checking method and device, electronic equipment and a storage medium, and relates to the technical field of chip verification, and the method comprises the steps: obtaining a to-be-checked and verified platform code, and determining a target checking rule configuration file based on the to-be-checked and verified platform code; analyzing the to-be-checked and verified platform code to obtain an abstract syntax tree corresponding to the to-be-checked and verified platform code; based on the abstract syntax tree, generating a dependency graph of components in the to-be-checked and verified platform code; and based on the target check rule configuration file, the abstract syntax tree and the dependency graph, performing static check on the to-be-checked and verified platform code to obtain an error check report of the to-be-checked and verified platform code. The technical problem of low inspection efficiency caused by lack of customized inspection processes and inspection rules in related technologies is solved, and the technical effect of improving the inspection efficiency is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip verification, in particular to a verification platform code checking method and device, electronic equipment and storage medium. BACKGROUND

[0002] Chip verification is a key step in the chip design process, aiming to find potential defects in the design code by writing verification code and building a verification platform. The verification platform is usually built based on SystemVerilog or UVM syntax rules, which is the basis for ensuring the correct operation of the test environment. Checking the verification platform code is a key step to ensure the efficiency and accuracy of the chip verification process.

[0003] In related technologies, the checking of the verification platform code relies on simulation tools, lacks customized checking processes and checking rules, and has low checking efficiency. SUMMARY

[0004] The present application provides a verification platform code checking method, device, electronic equipment and storage medium to at least solve the problem that the checking of the verification platform code in related technologies relies on simulation tools, lacks customized checking processes and checking rules, and has low checking efficiency.

[0005] The present application provides a verification platform code checking method, comprising:

[0006] obtaining the verification platform code to be checked;

[0007] determining a target checking rule configuration file based on the verification platform code to be checked;

[0008] parsing the verification platform code to be checked to obtain an abstract syntax tree corresponding to the verification platform code to be checked;

[0009] generating a dependency graph of components in the verification platform code to be checked based on the abstract syntax tree;

[0010] performing static checking on the verification platform code to be checked based on the target checking rule configuration file, the abstract syntax tree and the dependency graph, and obtaining an error checking report of the verification platform code to be checked.

[0011] The present application also provides a verification platform code checking device, comprising:

[0012] a first obtaining module for obtaining the verification platform code to be checked;

[0013] a first determining module for determining a target checking rule configuration file based on the verification platform code to be checked;

[0014] The second obtaining module is configured to parse the to-be-checked verification platform code to obtain an abstract syntax tree corresponding to the to-be-checked verification platform code.

[0015] The generating module is configured to generate a dependency graph of components in the to-be-checked verification platform code based on the abstract syntax tree.

[0016] The third obtaining module is configured to perform static checking on the to-be-checked verification platform code based on the target checking rule configuration file, the abstract syntax tree and the dependency graph to obtain an error checking report of the to-be-checked verification platform code.

[0017] The present application further provides an electronic device, comprising a memory configured to store a computer program, and a processor configured to execute the computer program to implement the steps of any of the verification platform code checking methods.

[0018] The present application further provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of any of the verification platform code checking methods.

[0019] The present application further provides a computer program product, comprising a computer program, and the computer program is executed by a processor to implement the steps of any of the verification platform code checking methods.

[0020] According to the present application, the to-be-checked verification platform code is obtained, the target checking rule configuration file is determined based on the to-be-checked verification platform code, the to-be-checked verification platform code is parsed to obtain an abstract syntax tree corresponding to the to-be-checked verification platform code, the dependency graph of components in the to-be-checked verification platform code is generated based on the abstract syntax tree, and the static checking is performed on the to-be-checked verification platform code based on the target checking rule configuration file, the abstract syntax tree and the dependency graph to obtain an error checking report of the to-be-checked verification platform code. Without relying on a simulation tool, the static checking of the to-be-checked verification platform code is automatically implemented through a customized checking process and checking rule, and therefore, the technical problem of low checking efficiency caused by the fact that the checking of the verification platform code relies on the simulation tool and lacks the customized checking process and checking rule can be solved, and the technical effect of improving the checking efficiency is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0022] Figure 1A structural schematic diagram of a verification platform code checking system provided by an embodiment of the present application is provided.

[0023] Figure 2 A flowchart of a verification platform code checking method provided by an embodiment of the present application is provided.

[0024] Figure 3 A flowchart of another verification platform code checking method provided by an embodiment of the present application is provided.

[0025] Figure 4 A schematic diagram of a checking rule configuration file provided by an embodiment of the present application is provided.

[0026] Figure 5 A flowchart of another verification platform code checking method provided by an embodiment of the present application is provided.

[0027] Figure 6 A structural schematic diagram of a verification platform code checking device provided by an embodiment of the present application is provided.

[0028] Figure 7 A structural schematic diagram of an electronic device provided by an embodiment of the present application is provided. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, any other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0030] It should be noted that, in the description of the present application, the terms “comprise”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0031] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0032] Chip verification is a key step in the chip device process, and the goal is to find potential defects in the design code. Verification personnel need to write verification code based on the design under test and build a verification platform (TestBench). The verification platform is usually built based on SystemVerilog or Universal Verification Methodology (UVM) syntax rules, which is the basis for ensuring the correct operation of the test environment.

[0033] After the verification platform is built, the verification platform code and the design under test need to be compiled and simulated. For example, in the three-step simulation process of the VCS tool chain, the verification platform code and the design under test need to pass all checks before elaboration (static analysis) before the subsequent simulation can begin.

[0034] Checking the verification platform code is a key step to ensure the efficiency and accuracy of the chip verification process. During the early stages of verification, verification personnel need to invest time and effort in debugging their verification environment, i.e., the verification platform code, to ensure that elaboration passes. This usually requires verification personnel to check logs after dynamic compilation, repeatedly modify and improve the environment, and necessary checks include: design version and IP version matching, basic syntax compilation passing, warning information not coming from RTL code defects, test function point matching, etc.

[0035] In the later stages of verification, the verification platform code also needs to be checked before being put into the library to ensure the stability of regression testing and the reusability of the verification platform, and to reduce the waste of simulation resources.

[0036] In related technologies, the method of checking the verification platform code is dynamic, i.e., after all verification components are basically complete, the entire verification platform code is compiled once, and after solving the code defects, it is compiled again, and this process is repeated until the verification environment is perfected. When there are many early verification environment problems, it often needs to be compiled multiple times, which consumes a lot of time for verification personnel to check the verification platform code statically, and the checking efficiency is low. Moreover, the checking of the verification platform code relies on the simulation tool, and the checking of the simulation tool is usually based on pure syntax analysis, lacks checking of initial configuration, and has no customized code checking rules. In large verification environments, each subsystem environment often needs individualized code checking rules. In the later stages of verification, the verification platform code also needs corresponding automated checking before being put into the library to improve code quality and environment reusability. That is, in related technologies, due to the complexity of Systemverilog or UVM syntax, no corresponding code checking rules are defined for the verification platform code in different verification stages. Therefore, the method of checking the verification platform code in related technologies lacks customized checking processes and checking rules, resulting in low checking efficiency.

[0037] To solve the above problems, the embodiment of the present application provides a verification platform code checking method, device, electronic equipment and storage medium. The method comprises: obtaining a to-be-checked verification platform code; determining a target checking rule configuration file based on the to-be-checked verification platform code; parsing the to-be-checked verification platform code to obtain an abstract syntax tree corresponding to the to-be-checked verification platform code; generating a dependency graph of a component in the to-be-checked verification platform code based on the abstract syntax tree; and performing static checking on the to-be-checked verification platform code based on the target checking rule configuration file, the abstract syntax tree and the dependency graph to obtain an error checking report of the to-be-checked verification platform code. The method provided by the above solution does not need to rely on a simulation tool, allows different checking rules to be set for the verification environment building period and the code storage period, automatically implements the static checking of the to-be-checked verification platform code through the customized checking process and checking rules, discovers problems of the verification platform in advance, reduces the waste of verification resources, speeds up the building of the verification platform, and thus improves the checking efficiency and the verification efficiency.

[0038] In combination with a specific application environment architecture or a specific hardware architecture on which the verification platform code checking method is executed, the specific application environment architecture or the specific hardware architecture is described herein.

[0039] The verification platform code checking method, device, electronic equipment and storage medium provided by the embodiment of the present application are suitable for checking the verification platform code. For example, Figure 1As shown, a structural diagram of a verification platform code checking system based on which the embodiments of the present application are implemented is shown, and the verification platform code checking system comprises a rule configuration module, a static analysis engine, a rule checking engine, a version management module and an error processing module. The rule configuration module is configured to manage different verification stages and an integrable rule library, the rule library comprising checking rule configuration files corresponding to different verification platform codes, the checking rule configuration files comprising syntax rules, function rules, configuration and rules and custom rules. It should be noted that the checking rule configuration files in YAML format are provided through an inheritance mechanism. The user is allowed to dynamically adjust the threshold values of the rules in the checking rule configuration files according to the verification stages (such as the verification environment setup stage and the code library stage). All the rules can be loaded into the rule checking engine through the loader method of the automatic tool. The static analysis engine is configured to parse the verification platform code (SystemVerilog / UVM syntax format) to be checked to generate an abstract syntax tree (AST), and to generate a dependency graph based on the abstract syntax tree. Specifically, the PySlang open source library is used to process the code, analyze the include files and package relationships, extract key code structures, and generate the abstract syntax tree and the dependency graph. The key code structures include module / class definitions, signal connection relationships, configuration parameters and the like. The rule checking engine is configured to determine the target checking rule configuration file corresponding to the verification platform code to be checked from the rule library, perform multi-level rule checking according to the priority, i.e., in the order of configuration rules→ syntax rules→ function rules→ custom rules, and perform static checking on the verification platform code to be checked based on the abstract syntax tree and the dependency graph, so as to preferentially process high-priority errors (such as version conflicts). The version management module is configured to perform consistency checking on the versions of the dependent items in the verification platform code based on the configuration rules, including design code, IP core, simulation model and SRAM initialization file path checking. The module prevents the simulation results from being distorted due to version mismatch. The module obtains the version value of the design to be tested in the verification platform code to be checked from the static analysis engine, compares the version value with the expected version value from the configuration rules, and performs configuration checking. The error processing module is configured to obtain the checking results of the rule checking engine and the version management module, generate a hierarchical error report in html format based on the checking results, associate the error files and the code line numbers and provide repair suggestions. The errors of the redundant type, the conflict type and the abnormal type are classified and reported respectively.

[0040] The embodiments of the present application provide a verification platform code checking method applied to the verification platform code checking system described above, Figure 2 A flowchart of the verification platform code checking method provided by the embodiments of the present application is shown in Figure 2 The flowchart comprises the following steps.

[0041] In step S201, the verification platform code to be checked is obtained.

[0042] In step S202, based on the to-be-checked verification platform code, a target checking rule configuration file is determined.

[0043] It can be understood that the to-be-checked verification platform code in different verification stages corresponds to different checking rule configuration files, and the checking rule configuration file includes syntax rules, function rules, configuration rules and custom rules, which are set by technical personnel in advance.

[0044] In step S203, the to-be-checked verification platform code is parsed to obtain an abstract syntax tree corresponding to the to-be-checked verification platform code.

[0045] The to-be-checked verification platform code is parsed by a python open source library PySlang to construct the abstract syntax tree.

[0046] In step S204, based on the abstract syntax tree, a dependency graph of components in the to-be-checked verification platform code is generated.

[0047] The components in the to-be-checked verification platform code include variables, modules, classes, interfaces, signals, etc. The hierarchical structure and connection relationship of the components are obtained, and the dependency graph is generated according to the hierarchical structure and connection relationship of the components, so as to check the unconnected ports or un-instantiated components or objects.

[0048] In step S205, based on the target checking rule configuration file, the abstract syntax tree and the dependency graph, the to-be-checked verification platform code is statically checked to obtain an error checking report of the to-be-checked verification platform code.

[0049] Based on the target checking rule configuration file, the abstract syntax tree nodes and the dependency graph are traversed to identify errors in the to-be-checked verification platform code, such as syntax errors, version number conflicts, interface mismatches, etc. Based on the identified errors, an error checking report is generated.

[0050] The verification platform code checking method provided in the embodiments of the present application comprises the following steps: obtaining to-be-checked verification platform code; determining a target checking rule configuration file based on the to-be-checked verification platform code; parsing the to-be-checked verification platform code to obtain an abstract syntax tree corresponding to the to-be-checked verification platform code; generating a dependency graph of components in the to-be-checked verification platform code based on the abstract syntax tree; and performing static checking on the to-be-checked verification platform code based on the target checking rule configuration file, the abstract syntax tree and the dependency graph, to obtain an error checking report of the to-be-checked verification platform code. Without relying on simulation tools, the static checking of the to-be-checked verification platform code is automatically implemented through customized checking processes and checking rules, so that the technical problem of the related art that the checking of the verification platform code relies on simulation tools, lacks customized checking processes and checking rules and has low checking efficiency can be solved, and the technical effect of improving the checking efficiency is achieved.

[0051] The embodiments of the present application provide a verification platform code checking method, Figure 3 The flowchart of the verification platform code checking method provided in the embodiments of the present application is shown in Figure 3 The flowchart comprises the following steps:

[0052] In step S301, to-be-checked verification platform code is obtained. For details, refer to step S201 of the embodiment shown in Figure 2 which will not be repeated here.

[0053] In step S302, a target checking rule configuration file is determined based on the to-be-checked verification platform code. For details, refer to step S202 of the embodiment shown in Figure 2 which will not be repeated here.

[0054] In step S303, the to-be-checked verification platform code is parsed to obtain an abstract syntax tree corresponding to the to-be-checked verification platform code. For details, refer to step S203 of the embodiment shown in Figure 2 which will not be repeated here.

[0055] In step S304, a dependency graph of components in the to-be-checked verification platform code is generated based on the abstract syntax tree. For details, refer to step S204 of the embodiment shown in Figure 2 which will not be repeated here.

[0056] In step S305, the to-be-checked verification platform code is checked statically based on the target checking rule configuration file, the abstract syntax tree and the dependency graph, to obtain an error checking report of the to-be-checked verification platform code.

[0057] Specifically, step S305 comprises the following steps:

[0058] Step S3051, according to the rule order of the configuration rules, syntax rules, function rules and custom rules in the target check rule configuration file, based on the abstract syntax tree and the dependency graph, the configuration check, syntax check, function check and custom check are performed on the to-be-checked verification platform to identify the first priority error, the second priority error, the third priority error and the fourth priority error in the to-be-checked verification platform code.

[0059] Among them, the configuration check can check the inconsistency of the design version with the expected configuration. The syntax check can check the syntax error, naming specification failure, repeated code and other problems. The function check can check the port connection problem. The custom check can check the error of unmatched annotations or custom low priority check items.

[0060] Step S3052, based on the identified first priority error, second priority error, third priority error, fourth priority error in the to-be-checked verification platform code and the error check report output path in the target check rule configuration file, output the error check report of the to-be-checked verification platform code.

[0061] Among them, the first priority error is determined based on the configuration check, the second priority error is determined based on the syntax check, the third priority error is determined based on the function check, and the fourth priority error is determined based on the custom check; the first priority is higher than the second priority, the second priority is higher than the third priority, and the third priority is higher than the fourth priority; the higher the priority of the error, the greater the impact on the effectiveness, integrity and promotion efficiency of the to-be-tested design verification; the configuration check includes design version number check, IP version number check, model (model) version check and initialization file path verification of the storage module (SRAM) of the to-be-tested design; the syntax check is used for syntax check based on Systemverilog or UVM syntax standard, including variable declaration check, declaration statement check and class instantiation check; the function check includes connection integrity check of the to-be-tested design port and the component responsible for generating the excitation signal and driving the to-be-tested design port, i.e. DUT port and driver connection integrity check, coverage rate of the to-be-tested design function and matching degree check of the requirement document of the to-be-tested design, and connectivity check of the configuration parameter, i.e. config_db connectivity check; the custom check includes indentation format check, custom coverage group naming specification check, i.e. whether the coverage group naming conforms to the custom coverage group naming specification, custom assertion naming specification check, i.e. whether the assertion naming conforms to the custom assertion naming specification, and custom checker naming specification check, i.e. whether the checker naming conforms to the custom checker naming specification.

[0062] Exemplarily, Figure 4 The schematic diagram of the check rule configuration file provided by the embodiment of the application is as follows:Figure 4 As shown, the check rule configuration file includes verification stage information: stage 1: environment setup. It also includes syntax rules, function rules, configuration rules and custom rules. The syntax rules include naming specification as snake naming; and indentation space number as 2 spaces. The function rules include: interface integrity check: find unconnected interfaces and throw a warning; and coverage model minimum threshold set to 80%. The configuration rules include checking whether the version meets the expectation, where the expected version is 1.2; and checking whether the path of the SARM file is. / sram / init.hex, i.e., checking whether the path of the SARM initialization file is. / sram / init.hex. The custom rules include assertion naming specification check, which is performed by regular expression matching check to determine whether the assertion naming meets the specification. If not, an error of the corresponding error level is triggered.

[0063] The verification platform code checking method provided by the embodiments of the present application divides the check rules into four layers, i.e., configuration rules, syntax rules, function rules and custom rules, to avoid confusion of different properties and to achieve fine-grained identification of errors. The errors are sorted according to priority to ensure that verification resources are preferentially invested in key issues and to avoid investment of a large amount of computing resources in running invalid simulation.

[0064] In some optional embodiments, before determining the target check rule configuration file based on the verification platform code to be checked, the verification platform code checking method further includes:

[0065] Step a1, for any verification platform code, a check rule configuration file of the verification platform code is generated based on verification stage information of the verification platform code.

[0066] The verification stage information can be the early stage of environment establishment or the late stage of environment storage. The syntax rules, configuration rules, function rules and custom rules of the verification platform code are generally different in different verification stages. Therefore, the syntax rules, configuration rules, function rules and custom rules corresponding to the verification platform code are set based on different verification stages, and then the check rule configuration file of the verification platform code is generated.

[0067] Step a2, the check rule configuration file of the verification platform code is associated with the verification platform code based on address information of the verification platform code.

[0068] The address information of the verification platform code can be engineering directory information of the verification platform code.

[0069] The above step S302 includes:

[0070] Step b1, based on the verification platform code to be checked, the check rule configuration file associated with the verification platform code to be checked is determined as the target check rule configuration file.

[0071] It can be understood that the check rule configuration file is located in the rule library.

[0072] In some optional embodiments, the step S3052 comprises:

[0073] Step c1, dividing the first priority error, the second priority error and the third priority error according to the error type to obtain the error of different error types under different priorities.

[0074] Among them, the error type includes Abundant_Item, Alarm_Item, Execpt_Item and Error_Item.

[0075] The first priority error is usually the error class and the exception class, such as version conflict, interface exception class.

[0076] The second priority error, the third priority error and the fourth priority error are usually redundant and alarm, such as redundant code, non-standard naming, etc.

[0077] Step c2, based on the error of different error types under different priorities, backtracking the abstract syntax tree and the dependency graph, and determining the position information of the error code in the to-be-checked verification platform code.

[0078] That is, for any error type error under any priority, the abstract syntax tree and the dependency graph are backtracked to locate the error code and obtain the position information of the associated file and the error code.

[0079] That is, when the to-be-checked verification platform code has errors, the error node can be traced back from the abstract syntax tree, and based on the error node, the position of the error code is recorded, including the file position, line number and error reason, error type, etc.

[0080] Step c3, based on the error of different error types under different priorities and the position information of the error code in the to-be-checked verification platform code, generating an error check report of the to-be-checked verification platform code.

[0081] Among them, the error of different error types under different priorities and the position information of the error code in the corresponding to-be-checked verification platform code are saved as a dataclass class, stored in the database by entries and updated in real time to generate an error check report at a specified location, and the report format is html format.

[0082] Step c4, based on the error check report output path in the target check rule configuration file, outputting the error check report of the to-be-checked verification platform code.

[0083] The verification platform code checking method provided by the embodiments of the present application can help the user to accurately locate the error code in the verification platform code to be checked and solve the error in time, thereby improving the efficiency of chip verification.

[0084] In some optional embodiments, the verification platform code checking method further includes:

[0085] In step d1, if the error checking report indicates that the verification platform code to be checked has the first priority error, the verification process based on the verification platform code to be checked is stopped until the first priority error is repaired.

[0086] The verification platform code checking method provided by the embodiments of the present application can save hours or even days of simulation time by stopping the verification process in time when the first priority error exists, thereby avoiding the problem accumulation leading to the later rework and ensuring the correctness of the verification environment.

[0087] In some optional embodiments, the verification platform code checking method further includes:

[0088] In step e1, if the error checking report indicates that the verification platform code to be checked has no first priority error but has a second priority error or a third priority error or a fourth priority error, the verification process based on the verification platform code to be checked is continued, and the error in the error checking report is reported for repair.

[0089] The verification platform code checking method provided by the embodiments of the present application can avoid the simulation stagnation caused by small problems (such as non-standard naming) by not stopping the verification process when only the second priority error or the third priority error or the fourth priority error exists, thereby improving the efficiency of chip verification.

[0090] In some optional embodiments, the verification platform code checking method further includes:

[0091] In step f1, if the error checking report indicates that the verification platform code to be checked has no first priority error but the number of second priority errors exceeds a first preset number threshold or the number of third priority errors exceeds a second preset number threshold or the number of fourth priority errors exceeds a third preset number threshold, the verification process based on the verification platform code to be checked is stopped until the second priority error or the third priority error or the fourth priority error is repaired.

[0092] It can be understood that if the error check report represents that there is no error of the first priority in the to-be-checked verification platform code, but the number of errors of the second priority does not exceed the first preset number threshold, the number of errors of the third priority does not exceed the second preset number threshold, and the number of errors of the fourth priority does not exceed the third preset number threshold, the verification process based on the to-be-checked verification platform code is continued to be executed, and it is reported that the errors contained in the error check report are suggested to be repaired.

[0093] The first preset number threshold, the second preset number threshold, and the third preset number threshold are set by a technician and are not specifically limited here.

[0094] The verification platform code checking method provided by the embodiment of the application stops the verification process when the number of errors of different priorities exceeds the preset threshold, prevents a large number of derived errors from being generated by continuing to execute the verification process, and improves system security and reliability.

[0095] In some optional embodiments, the verification platform code checking method further includes:

[0096] In the case where the error check report represents that there is an error of the first priority in the to-be-checked verification platform code, if the error is that the design version number in the to-be-checked verification platform code does not match the expected design version number in the configuration rule, the expected design version number is extracted from the configuration rule, and the to-be-checked verification platform code is updated based on the expected design version number to repair the error.

[0097] In the case where the error check report represents that there is an error of the first priority in the to-be-checked verification platform code, if the error is that the initialization file path of the SRAM of the to-be-tested design is incorrect, the correct initialization file path of the SRAM of the to-be-tested design is extracted from the configuration rule, and the to-be-checked verification platform code is updated based on the correct initialization file path of the SRAM of the to-be-tested design to repair the error.

[0098] The verification platform code checking method provided by the embodiment of the application automatically repairs the corresponding error according to the corresponding repair suggestion in the case where the error check report represents that there is an error of the first priority in the to-be-checked verification platform code, which significantly improves verification efficiency, quality, and resource utilization.

[0099] An embodiment of the application provides a verification platform code checking method, Figure 5 A flowchart of the verification platform code checking method provided by the embodiment of the application is shown in Figure 5 The flowchart includes:

[0100] A customized checking rule is written. Specifically, a checking rule configuration file of different verification platform code is defined in a YAML format, which contains necessary keyword information such as a verification stage: setup for a pre-environment establishment stage and release for a post-environment storage stage. An optional item is engineering directory information of the verification platform code, and an error checking report output path.

[0101] A source code syntax tree is parsed based on PySlang. That is, the PySlang library is used to parse the verification platform code to be checked, and an abstract syntax tree is generated.

[0102] Syntax tree nodes are traversed to obtain a dependency graph. Specifically, key information in the abstract syntax tree is extracted, such as module / class definition, signal connection relationship, configuration parameters such as version information, and the like, a position and reference relationship of variable, class, and interface declaration are constructed, a dependency relationship directed graph and a dependency graph are generated, and are used for dependency analysis.

[0103] It is determined whether the rule checking passes or not, such as directly generating a code checking report. If not, the problem node is backtracked, risk analysis and evaluation are performed, and a code checking report is generated.

[0104] Specifically, based on the target checking rule configuration file corresponding to the verification platform code to be checked, a hierarchical structure is used for code checking. First, configuration checking is performed, and design version, IP version, and SARM initialization file path are sequentially compared and checked. The checked version conflict and path error are classified as a first priority error. Second, syntax checking is performed to determine whether the parsed abstract syntax tree matches the SystemVerilog / UVM syntax specification. Third, function checking is performed, including interface integrity, bit width matching, coverage threshold checking, and the like. Finally, custom checking is performed.

[0105] After the checking is completed, if there is an error, that is, the rule checking does not pass, error code positioning is performed based on the error, a code checking report, that is, an error checking report, is generated based on the position information of the error code and the type and priority of the error. It can be understood that if there is no error, the code checking report is empty.

[0106] The verification platform code checking method provided in the embodiments of the present application can realize automatic code checking and reporting by calling an automation script, save simulation tool repeated compilation and TestBench code review time, not only save the time and energy of engineers, but also improve the chip verification efficiency.

[0107] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and necessary general hardware platform, of course, it can also be realized by hardware, but in many cases the former is a better embodiment.

[0108] Embodiments of this application also provide a verification platform code inspection device, such as... Figure 6 As shown, the code inspection device of the verification platform includes:

[0109] The first acquisition module 601 is used to acquire the code of the platform to be checked and verified.

[0110] The first determining module 602 is used to determine the target inspection rule configuration file based on the code of the verification platform to be inspected.

[0111] The second acquisition module 603 is used to parse the code of the verification platform to be checked and obtain the abstract syntax tree corresponding to the code of the verification platform to be checked.

[0112] Module 604 is used to generate a dependency graph of components in the code of the platform to be checked and verified, based on an abstract syntax tree.

[0113] The third acquisition module 605 is used to perform static checks on the code of the verification platform to be checked based on the target inspection rule configuration file, abstract syntax tree and dependency graph, and obtain the error inspection report of the code of the verification platform to be checked.

[0114] In some optional implementations, the verification platform code inspection apparatus further includes:

[0115] The first generation unit is used to generate an inspection rule configuration file for any verification platform code based on the verification stage information of the verification platform code.

[0116] The association unit is used to associate the verification platform code's inspection rule configuration file with the verification platform code based on the address information of the verification platform code.

[0117] The first determining module 602 includes:

[0118] The first determining unit is used to determine the inspection rule configuration file associated with the platform code to be inspected as the target inspection rule configuration file based on the platform code to be inspected.

[0119] In some alternative implementations, the third acquisition module 605 includes:

[0120] The identification unit is used to perform configuration checks, syntax checks, function checks, and custom checks on the verification platform to be checked, based on the rule order of configuration rules, syntax rules, function rules, and custom rules in the target inspection rule configuration file and the abstract syntax tree and dependency graph, in order to identify first-priority errors, second-priority errors, third-priority errors, and fourth-priority errors in the code of the verification platform to be checked.

[0121] The first output unit is configured to output the error check report of the to-be-checked verification platform code based on the error check report output path in the target check rule configuration file and the identified first-priority error, second-priority error, third-priority error, fourth-priority error, and target check rule configuration file.

[0122] In some optional embodiments, the first output unit comprises:

[0123] The first obtaining unit is configured to divide the first-priority error, second-priority error, and third-priority error according to error types, and obtain errors of different error types at different priorities.

[0124] The second determining unit is configured to backtrack the abstract syntax tree and the dependency graph based on the errors of different error types at different priorities, and determine position information of error code in the to-be-checked verification platform code.

[0125] The second generating unit is configured to generate the error check report of the to-be-checked verification platform code based on the errors of different error types at different priorities and the position information of the error code in the to-be-checked verification platform code.

[0126] The second output unit is configured to output the error check report of the to-be-checked verification platform code based on the error check report output path in the target check rule configuration file.

[0127] In some optional embodiments, the verification platform code checking apparatus further comprises:

[0128] The first stopping execution unit is configured to stop executing the verification process based on the to-be-checked verification platform code if the error check report indicates that the to-be-checked verification platform code has the first-priority error, until the first-priority error is repaired.

[0129] In some optional embodiments, the verification platform code checking apparatus further comprises:

[0130] The reporting unit is configured to continue executing the verification process based on the to-be-checked verification platform code and report the suggestion of repairing the errors contained in the error check report if the error check report indicates that the to-be-checked verification platform code does not have the first-priority error but has the second-priority error, third-priority error, or fourth-priority error.

[0131] In some optional embodiments, the verification platform code checking apparatus further comprises:

[0132] The second stop execution unit is configured to stop the execution of the verification process based on the to-be-verified platform code if the error check report indicates that no error of the first priority exists in the to-be-verified platform code, but the number of errors of the second priority exceeds the first preset number threshold, or the number of errors of the third priority exceeds the second preset number threshold, or the number of errors of the fourth priority exceeds the third preset number threshold, until the errors of the second priority, the errors of the third priority, or the errors of the fourth priority are repaired.

[0133] The features of the embodiments of the verification platform code checking device can be understood with reference to the related descriptions of the embodiments of the verification platform code checking method, which will not be repeated here.

[0134] The embodiments of the present application also provide an electronic device, as shown in the accompanying drawings, comprising a processor 701 and a memory 702, wherein the memory 702 stores a computer program, and the processor 701 is configured to run the computer program to execute the steps in any of the above-mentioned verification platform code checking method embodiments. Figure 7

[0135] The embodiments of the present application also provide a computer readable storage medium, which stores a computer program, wherein the computer program is configured to execute the steps in any of the above-mentioned verification platform code checking method embodiments when running.

[0136] In an example embodiment, the above-mentioned computer readable storage medium can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0137] The embodiments of the present application also provide a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the steps in any of the above-mentioned verification platform code checking method embodiments.

[0138] The embodiments of the present application also provide another computer program product, which comprises a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps in any of the above-mentioned verification platform code checking method embodiments.

[0139] ​Those skilled in the art will further realize that the mere concepts, teachings, and embodiments described herein are merely meant to provide an enabling description of the claimed application. Accordingly, modifications and / or additions, other than those explicitly described herein, can be obvious to those skilled in the art in the light of this disclosure. The claimed application is intended to embrace all such modifications and / or additions.

[0140] The above provides a verification platform code checking method, device, electronic equipment and storage medium. The principles and implementation modes of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the method and its core idea. It should be pointed out that for those skilled in the art, without departing from the principles of the present application, some improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A method of verifying platform code checks, the method comprising: The method comprises the following steps: acquiring a to-be-inspected verification platform code; determining a target inspection rule configuration file based on the to-be-inspected verification platform code; parsing the to-be-inspected verification platform code to obtain an abstract syntax tree corresponding to the to-be-inspected verification platform code; generating a dependency graph of components in the to-be-inspected verification platform code based on the abstract syntax tree; performing static inspection on the to-be-inspected verification platform code based on the target inspection rule configuration file, the abstract syntax tree and the dependency graph to obtain an error inspection report of the to-be-inspected verification platform code.

2. The method of claim 1, wherein, Before determining the target inspection rule configuration file based on the to-be-inspected verification platform code, the method further comprises the following steps: generating an inspection rule configuration file of any verification platform code based on verification stage information of the verification platform code; associating the inspection rule configuration file of the verification platform code with the verification platform code based on address information of the verification platform code; determining the inspection rule configuration file associated with the to-be-inspected verification platform code as the target inspection rule configuration file based on the to-be-inspected verification platform code. performing static inspection on the to-be-inspected verification platform code based on the target inspection rule configuration file, the abstract syntax tree and the dependency graph to obtain an error inspection report of the to-be-inspected verification platform code, comprises the following steps:

3. The method of claim 1, wherein, performing configuration inspection, syntax inspection, function inspection and custom inspection on the to-be-inspected verification platform based on the abstract syntax tree and the dependency graph in the rule order of configuration rules, syntax rules, function rules and custom rules in the target inspection rule configuration file, to identify first-priority errors, second-priority errors, third-priority errors and fourth-priority errors in the to-be-inspected verification platform code; outputting the error inspection report of the to-be-inspected verification platform code based on the identified first-priority errors, second-priority errors, third-priority errors, fourth-priority errors in the to-be-inspected verification platform code and an error inspection report output path in the target inspection rule configuration file. ​ The first priority error is determined based on a configuration check, the second priority error is determined based on a syntax check, the third priority error is determined based on a function check, and the fourth priority error is determined based on a custom check; the first priority is higher than the second priority, the second priority is higher than the third priority, and the third priority is higher than the fourth priority; the higher the priority of the error, the greater the influence on the effectiveness, integrity and promotion efficiency of the design under test verification; the configuration check includes design version number check, model version check and initialization file path verification of the storage module of the design under test; the syntax check includes variable declaration check, declaration statement check and class instantiation check; the function check includes connection integrity check of the design under test port and the component responsible for generating the excitation signal and driving the design under test port, coverage rate of the design under test function and matching degree check of the design under test requirement document, and configuration parameter connectivity check; the custom check includes indentation format check, custom coverage group naming specification check, custom assertion naming specification check and custom checker naming specification check.

4. The method of claim 3, wherein, The error check report of the to-be-checked verification platform code is output based on the identified first priority error, second priority error, third priority error, fourth priority error in the to-be-checked verification platform code and the error check report output path in the target check rule configuration file, and the error check report of the to-be-checked verification platform code is output. The first priority error, the second priority error and the third priority error are divided according to error types, and different error types under different priorities are obtained; Based on different error types under different priorities, the abstract syntax tree and the dependency graph are backtracked to determine the location information of the error code in the to-be-checked verification platform code; Based on different error types under different priorities and the location information of the error code in the to-be-checked verification platform code, the error check report of the to-be-checked verification platform code is generated; The error check report of the to-be-checked verification platform code is output based on the error check report output path in the target check rule configuration file.

5. The method of claim 1, wherein, The method further comprises: If the error check report indicates that the to-be-checked verification platform code has a first priority error, stop executing the verification process based on the to-be-checked verification platform code until the first priority error is repaired.

6. The method of claim 1, wherein, The method further comprises: If the error check report indicates that the to-be-checked verification platform code does not have a first priority error, but has a second priority error or a third priority error or a fourth priority error, continue to execute the verification process based on the to-be-checked verification platform code and report the suggestion to repair the error in the error check report.

7. The method of claim 1, wherein, The method further comprises: If the error checking report represents that there is no error of the first priority in the to-be-checked verification platform code, but the number of errors of the second priority exceeds the first preset number threshold, or the number of errors of the third priority exceeds the second preset number threshold, or the number of errors of the fourth priority exceeds the third preset number threshold, the verification process based on the to-be-checked verification platform code is stopped until the errors of the second priority, the third priority or the fourth priority are repaired.

8. A verifying platform code checking apparatus, characterized by, The method comprises the steps of: The first acquisition module is configured to acquire to-be-checked verification platform code. The first determination module is configured to determine a target checking rule configuration file based on the to-be-checked verification platform code. The second acquisition module is configured to parse the to-be-checked verification platform code to obtain an abstract syntax tree corresponding to the to-be-checked verification platform code. The generation module is configured to generate a dependency graph of components in the to-be-checked verification platform code based on the abstract syntax tree. The third acquisition module is configured to perform static checking on the to-be-checked verification platform code based on the target checking rule configuration file, the abstract syntax tree and the dependency graph, and obtain an error checking report of the to-be-checked verification platform code.

9. An electronic device, comprising: The method comprises the steps of: The memory is configured to store a computer program. The processor is configured to implement the steps of the verification platform code checking method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the steps of the verification platform code checking method according to any one of claims 1 to 7.

Images