Pixel circuit and active array

Abstract

The invention discloses a pixel circuit and an active array. The pixel circuit comprises a storage capacitor, a charging circuit and an output circuit. The charging circuit is coupled with the first end and the second end of the storage capacitor so as to periodically change the potential of the first end and the second end of the storage capacitor to maintain the storage voltage. The output circuit is coupled between the first system voltage and the second system voltage, and receives the potentials of the first end and the second end from the storage capacitor so as to output the first system voltage or the second system voltage. The output circuit includes an output transistor, a first terminal of which outputs a first system voltage in response to a change in potential of a first terminal of the storage capacitor, or outputs a second system voltage in response to a change in potential of a second terminal of the storage capacitor, a second terminal of which is coupled to the second system voltage, and a control terminal of which is coupled to the second terminal of the storage capacitor, therefore, the voltage of the control end of the output transistor is stabilized.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a pixel circuit and an active array. BACKGROUND

[0002] In the application of medical detection devices and Bio-chips, the pixel circuit controls the wettability of droplets by electric field to achieve precise manipulation of Digital Microfluidics (DMF), which is widely used in biochemical analysis and detection. On the other hand, in the technology of E-paper, the pixel circuit controls the distribution of electronic ink or electrophoretic particles by electric field to change the display state of the pixel.

[0003] However, in practical applications, such pixel circuits often face problems such as insufficient driving force, driving voltage attenuation, and leakage current leading to charge loss, which affect the accuracy of droplet manipulation and the stability of display quality. SUMMARY

[0004] Therefore, an embodiment of the present disclosure provides a pixel circuit, which includes a storage capacitor, a charging circuit, and an output circuit. The charging circuit is coupled to the first end and the second end of the storage capacitor and is configured to periodically change the potential of the first end and the second end of the storage capacitor, so that the storage capacitor maintains a storage voltage. The output circuit is coupled between a first system voltage and a second system voltage and is configured to receive the potential of the first end and the second end from the storage capacitor to determine whether to output the first system voltage or the second system voltage, wherein the output circuit includes an output transistor. The first end of the output transistor changes the potential of the first end of the storage capacitor to output the first system voltage, and changes the potential of the second end of the storage capacitor to output the second system voltage. The second end of the output transistor is coupled to the second system voltage, and the control end thereof is coupled to the second end of the storage capacitor, so as to stabilize the voltage of the control end of the output transistor by the storage capacitor.

[0005] According to an embodiment of the present disclosure, the charging circuit includes a first transistor and a second transistor. The first end of the first transistor receives a first scan signal, the second end of the first transistor is coupled to the first end of the storage capacitor, and the control end thereof receives a gate signal. The first end of the second transistor is coupled to the second end of the storage capacitor, the second end of the second transistor receives a second scan signal, and the control end thereof receives the gate signal, wherein the second scan signal is an inverse signal of the first scan signal.

[0006] According to embodiments of the present disclosure, the output circuit further includes a third transistor and a first capacitor. The first end of the third transistor receives the first system voltage, the second end of the third transistor is coupled to the first end of the output transistor, and the control end of the third transistor is coupled to the first end of the storage capacitor. The first end of the first capacitor receives the first system voltage, and the second end of the first capacitor is coupled to the control end of the third transistor to stabilize the voltage at the control end of the third transistor.

[0007] According to embodiments of the present disclosure, during the gate signal is triggered interval in the first frame, the first scan signal is low logic level corresponding to the high logic level of the gate signal, and the second scan signal is high logic level corresponding to the high logic level of the gate signal.

[0008] According to embodiments of the present disclosure, during the gate signal is triggered interval in the first frame, the first transistor is turned on according to the gate signal and the first scan signal, and the second transistor is turned on according to the gate signal and the second scan signal to transmit the second scan signal to the second end of the storage capacitor.

[0009] According to embodiments of the present disclosure, the third transistor is turned off corresponding to the turn-on of the first transistor, and the output transistor is turned on according to the second scan signal transmitted to the second end of the storage capacitor, and outputs the second system voltage during the first frame.

[0010] According to embodiments of the present disclosure, during the gate signal is triggered interval in the second frame, the first scan signal is high logic level corresponding to the high logic level of the gate signal, and the second scan signal is low logic level corresponding to the high logic level of the gate signal.

[0011] According to embodiments of the present disclosure, during the gate signal is triggered interval in the second frame, the first transistor is turned on according to the gate signal and the first scan signal, and the second transistor is turned on according to the gate signal and the second scan signal to transmit the first scan signal to the first end of the storage capacitor.

[0012] According to embodiments of the present disclosure, the output transistor is turned off corresponding to the turn-on of the second transistor, and the third transistor is turned on according to the first scan signal transmitted to the first end of the storage capacitor, and outputs the first system voltage during the second frame.

[0013] Embodiments of the present disclosure provide an active array including a plurality of pixel circuits as described above and a plurality of pixel electrodes. The pixel circuits are arranged in an array, and the pixel electrodes are each electrically connected to the pixel circuits to be driven by the first system voltage and the second system voltage periodically output by the pixel circuits. BRIEF DESCRIPTION OF DRAWINGS

[0014] To make the above and other features and advantages of the present application more comprehensible, the following will provide a more detailed description of the present application.

[0015] Figure 1 A schematic diagram of a pixel circuit according to an embodiment of the present application;

[0016] Figure 2 A schematic diagram of an internal architecture of a pixel circuit according to an embodiment of the present application;

[0017] Figure 3 A timing diagram of driving signals of a pixel circuit according to an embodiment of the present application;

[0018] Figure 4 An operation diagram of a gate signal triggered interval during a first frame of operation of a pixel circuit according to an embodiment of the present application; and

[0019] Figure 5 An operation diagram of a gate signal triggered interval during a second frame of operation of a pixel circuit according to an embodiment of the present application.

[0020]

Symbol Description

[0021] 100: Pixel circuit

[0022] 110: Charging circuit

[0023] 120: Output circuit

[0024] C ST : Storage capacitor

[0025] C H : First capacitor

[0026] F N : First frame

[0027] F N+1 : Second frame

[0028] F N+2 : Third frame

[0029] GT: Gate signal

[0030] N1: First end

[0031] N2: Second end

[0032] P: Pixel electrode

[0033] S1: First scan signal

[0034] S2: Second scan signal

[0035] T1: first transistor

[0036] T2: second transistor

[0037] T3: third transistor

[0038] TS: output transistor

[0039] t gh : high logic level interval

[0040] VCC: first system voltage

[0041] VE: drive voltage

[0042] VSS: second system voltage

[0043] VGH, VCCT, VCCE: high logic level

[0044] VGL, VSST, VSSE: low logic level DETAILED DESCRIPTION

[0045] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided application. The embodiments of components and configurations described herein are not intended to be exhaustive or limited to the precise forms disclosed. Additionally, the various embodiments and / or components described herein are not intended to be limited to the specific combinations of components and / or features described. Rather, the embodiments and / or components described herein are intended to be examples of one or more aspects of the application.

[0046] Reference will now be made to Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a pixel circuit 100 according to an embodiment of the present application. The pixel circuit 100 includes a charging circuit 110, a storage capacitor C ST , and an output circuit 120 to generate a drive voltage VE to drive a pixel electrode P. The embodiment of the present application also includes an active array composed of a plurality of pixel circuits 100 arranged in an array, and each of the pixel circuits 100 is coupled to a corresponding pixel electrode P to drive the pixel electrode P according to the drive voltage VE output by the output circuit 120.

[0047] The charging circuit 110 is coupled to a first terminal N1 and a second terminal N2 of the storage capacitor C ST , and is configured to periodically vary the potential of the first terminal N1 and the second terminal N2 of the storage capacitor C ST , so that the storage capacitor C ST maintains a storage voltage. For example, during a first frame in which the pixel circuit 100 operates, the charging circuit 110 varies the potential of the first terminal N1 and the second terminal N2 of the storage capacitor C STThe potential of the second terminal N2; during the operation of pixel circuit 100 in the second frame, charging circuit 110 changes the storage capacitor C. ST The potential of the first terminal N1; while during the operation of pixel circuit 100 in the third frame, charging circuit 110 changes the storage capacitor C. ST The potential of the second terminal N2. Similarly, corresponding to the frame switching, the charging circuit 110 periodically changes the storage capacitor C. ST The potentials of the first terminal N1 and the second terminal N2.

[0048] It is worth noting that, although the storage capacitor C ST The potentials of the first terminal N1 and the second terminal N2 change periodically with frame switching; however, the storage capacitor C ST In steady state, the potential difference (i.e., storage voltage) across its two ends remains a fixed value, but the direction of the potential difference flips as the frame switches.

[0049] Output circuit 120 is coupled between the first system voltage VCC and the second system voltage VSS, and has an output terminal to generate a drive voltage VE. Output circuit 120 stores the voltage through capacitor C. ST The system receives the potentials of the first terminal N1 and the second terminal N2, and determines whether to output a first system voltage VCC or a second system voltage VSS based on the potentials of the first terminal N1 or the second terminal N2. In an embodiment of the present invention, the second system voltage VSS is less than the first system voltage VCC, wherein the first system voltage VCC is a positive voltage to serve as the positive voltage amplitude of the driving voltage VE, and the second system voltage VSS is a negative voltage to serve as the negative voltage amplitude of the driving voltage VE.

[0050] Output circuit 120 includes output transistor TS. A first terminal of output transistor TS is coupled to pixel electrode P and configured to pass through charging circuit 110 and storage capacitor C. ST The operation of the output circuit 120 generates a driving voltage VE, which in turn drives the pixel electrode P. The second terminal of the output transistor TS is coupled to the second system voltage VSS, and the control terminal of the output transistor TS is coupled to the storage capacitor C. ST The second end, through the storage capacitor C ST The voltage at the control terminal of the stable output transistor TS is stabilized. Specifically, the storage capacitor C... ST By directly coupling the control terminal of the output transistor TS, the voltage at the control terminal of the output transistor TS can be stabilized, thereby reducing the amplitude attenuation of the output drive voltage VE (for example, during the negative voltage amplitude period when the stable drive voltage VE is the second system voltage VSS).

[0051] In detail, in the storage capacitor C STthe potential of the first end N1 of the storage capacitor C ST the potential of the first end N1 of the storage capacitor C

[0052] Please refer to Figure 2 , Figure 2 Fig. 1 is a schematic diagram of an internal architecture of a pixel circuit 100 according to an embodiment of the present application. The pixel circuit 100 comprises a charging circuit 110 and an output circuit 120. The charging circuit 110 comprises a first transistor T1 and a second transistor T2. The first end of the first transistor T1 receives a first scan signal S1, the second end of the first transistor T1 is coupled to the first end N1 of a storage capacitor C ST , and the control end of the first transistor T1 receives a gate signal GT. The first end of the second transistor T2 is coupled to the second end N2 of the storage capacitor C ST , the second end of the second transistor T2 receives a second scan signal S2, and the control end of the second transistor T2 receives the gate signal GT.

[0053] The output circuit 120 further comprises a third transistor T3 and a first capacitor C H . The first end of the third transistor T3 receives a first system voltage VCC, the second end of the third transistor T3 is coupled to the first end of an output transistor TS, and the control end of the third transistor T3 is coupled to the first end N1 of the storage capacitor C ST . The first end of the first capacitor C H receives the first system voltage VCC, and the second end of the first capacitor C H is coupled to the control end of the third transistor T3, so as to stabilize the voltage of the control end of the third transistor T3 by the first capacitor C H . In particular, the first capacitor C H is directly coupled to the control end of the third transistor T3, so as to stabilize the voltage of the control end of the third transistor T3, thereby reducing the amplitude decay of the output driving voltage VE (e.g., stabilizing the positive voltage amplitude period of the driving voltage VE when the driving voltage VE is the first system voltage VCC). In the embodiment of the present application, the first transistor T1, the second transistor T2, the third transistor T3 and the output transistor TS are all N-type transistors.

[0054] In the embodiment of the present application, the storage capacitor C ST serves as the main capacitor for stabilizing the driving voltage VE, and its capacitance value is designed to be greater than that of the first capacitor C H , so as to avoid the amplitude decay of the driving voltage VE. In the embodiment of the present application, the storage capacitor C STThe capacitance value is greater than that of the first capacitor C. H The capacitance value is at least six times higher to maintain a high driving voltage VE and avoid amplitude attenuation of the driving voltage VE. In one embodiment, based on layout area and cost considerations, the storage capacitor C... ST and the first capacitor C H The total capacitance is 1 picofarad (pF), where the storage capacitor C ST The capacitance value is, for example, 0.9 picofarads (pF), the first capacitor C H The capacitance value is, for example, 0.1 picofarads (pF) to design the difference between the two capacitance values ​​to be at least six times, while satisfying the condition that the sum of the capacitance values ​​is 1 picofarad (pF).

[0055] Please refer to Figure 3 , Figure 3 This is a timing diagram of the driving signals of the pixel circuit 100 illustrated according to an embodiment of the present invention, and in conjunction with... Figure 4 and Figure 5 The pixel circuits 100 shown operate in the first frame F N and the second frame F N+1 A schematic diagram illustrating the operation of the gate signal GT during the triggering interval provides a better understanding of the invention. Figure 4 and Figure 5 In the diagram, a transistor marked with an "X" indicates that it is in the off state, while a transistor without an "X" indicates that it is in the on state.

[0056] It should be understood that the operation of pixel circuit 100 will be similar to that in the first frame F. N and the second frame F N+1 The operation during this period is generally cyclical. For example, pixel circuit 100 operates in the third frame F. N+2 Operations and operations in the first frame F N The operation is the same at the same time to generate a drive voltage VE with a negative voltage amplitude (second system voltage VSSE), while pixel circuit 100 operates in the fourth frame F. N+3 (Not shown) Operations and operations in the second frame F N+1 The operation is the same as before, to generate a drive voltage VE with a positive voltage amplitude (first system voltage VCCE).

[0057] In an embodiment of the present invention, the second scan signal S2 is the inverted signal of the first scan signal S1, and it is worth noting that the gate signal GT is triggered once during each frame and has a high logic level range t. gh In the first frame F NDuring the period when the gate signal GT is triggered, the first scan signal S1 corresponds to a low logic level (e.g., VSST) for a high logic level (e.g., VGH) of the gate signal GT, and the second scan signal S2 corresponds to a high logic level (e.g., VCCT) for a high logic level of the gate signal GT; while in the second frame F N+1 During the period when the gate signal GT is triggered, the first scan signal S1 is at a high logic level corresponding to the high logic level of the gate signal GT, and the second scan signal S2 is at a low logic level corresponding to the high logic level of the gate signal GT.

[0058] In the low logic level (e.g., VGL) range where the gate signal GT is not triggered, the first scan signal S1 and the second scan signal S2 follow in the high logic level range t. gh The state constantly switches between high and low logic levels (e.g., switching between VCCT and VSST).

[0059] In embodiments of the present invention, although the high logic level of the driving voltage VE is additionally labeled as VCCE, it is essentially the same as the first system voltage VCC, and although the low logic level of the driving voltage VE is additionally labeled as VSSE, it is essentially the same as the second system voltage VSS. The aforementioned "essentially" means that, considering the on-resistance of the transistor and line losses, the two values ​​may have slight deviations.

[0060] like Figure 4 As shown, corresponding to the first frame F N The high logic level range t of the gate signal GT during the period gh The first transistor T1 is turned on based on the voltage difference between the gate signal GT and the first scan signal S1, and the second transistor T2 is turned on based on the voltage difference between the gate signal GT and the second scan signal S2, so as to transmit the second scan signal S2 to the storage capacitor C. ST The second terminal N2 makes the storage capacitor C ST The second terminal N2 is a positive voltage VCCT.

[0061] The conduction of the first transistor T1 causes the first scan signal S1 to be written to the control terminal of the third transistor T3, causing the storage capacitor C to... ST When the first terminal N1 is at a negative voltage VSST, the third transistor T3 is turned off accordingly. The conduction of the second transistor T2 causes the second scan signal S2 to be written to the control terminal of the output transistor TS, and the output transistor TS is turned on accordingly, outputting the second system voltage VSS at the first terminal of the output transistor TS.

[0062] like Figure 5 As shown, corresponding to the second frame F N+1 The high logic level range t of the gate signal GT during the period gh, the first transistor T1 is turned on according to the voltage difference between the gate signal GT and the first scanning signal S1, and the second transistor T2 is turned on according to the voltage difference between the gate signal GT and the second scanning signal S2, so as to transmit the first scanning signal S1 to the first end N1 of the storage capacitor C ST , and the first end N1 of the storage capacitor C ST is a positive voltage VCCT.

[0063] The turn-on of the second transistor T2 causes the second scanning signal S2 to be written into the control end of the output transistor TS, so that the second end N2 of the storage capacitor C ST is a negative voltage VSST, and the output transistor TS is correspondingly turned off. The turn-on of the first transistor T1 causes the first scanning signal S1 to be written into the control end of the third transistor T3, so that the third transistor T3 is correspondingly turned on and outputs the first system voltage VCC at the first end of the output transistor TS.

[0064] It is worth noting that when the pixel circuit 100 operates in the first frame F N , since the storage capacitor C ST is directly coupled to the control end of the output transistor TS, the attenuation of the second system voltage VSS of the driving voltage VE can be avoided; and when the pixel circuit 100 operates in the second frame F N+1 , the charging path of the storage capacitor C ST only needs to pass through the first transistor T1 and the second transistor T2, so that the driving force of the first system voltage VCC of the driving voltage VE can be improved. In the case that the second system voltage VSS is less attenuated and the driving force of the first system voltage VCC is sufficient, the pixel circuit can improve the accuracy of droplet control or the stability of display quality.

[0065] In summary, the pixel circuit of the present application can effectively solve the problems of insufficient driving force, driving voltage attenuation and charge loss caused by leakage current of the known pixel circuit by shortening the charging path of the storage capacitor and directly coupling the storage capacitor to the control end of the output transistor.

[0066] Although the present application has been disclosed with various embodiments as above, it is not intended to limit the present application, and those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present application, so the protection scope of the present application shall be subject to the appended claims.

Claims

1. A pixel circuit, comprising: Storage capacitors; A charging circuit is coupled to a first terminal and a second terminal of the storage capacitor and configured to periodically change the potential of the first terminal and the second terminal of the storage capacitor so that the storage capacitor maintains a storage voltage. as well as An output circuit, coupled between a first system voltage and a second system voltage, and configured to receive the potentials of the first and second terminals from the storage capacitor, to determine whether to output the first system voltage or the second system voltage, wherein the output circuit includes: An output transistor has a first terminal that outputs a first system voltage in response to a potential change at the first terminal of the storage capacitor, or outputs a second system voltage in response to a potential change at the second terminal of the storage capacitor. Its second terminal is coupled to the second system voltage, and its control terminal is coupled to the second terminal of the storage capacitor, so as to stabilize the voltage at the control terminal of the output transistor by means of the storage capacitor.

2. The pixel circuit of claim 1, wherein the charging circuit comprises: A first transistor, having a first terminal receiving a first scan signal, a second terminal coupled to the first terminal of the storage capacitor, and a control terminal receiving a gate signal; and The second transistor has a first terminal coupled to the second terminal of the storage capacitor, the second terminal receiving a second scan signal, and its control terminal receiving the gate signal, wherein the second scan signal is the inverted signal of the first scan signal.

3. The pixel circuit as claimed in claim 2, wherein the output circuit further comprises: A third transistor has a first terminal receiving the first system voltage, a second terminal coupled to the first terminal of the output transistor, and a control terminal coupled to the first terminal of the storage capacitor; and A first capacitor has a first terminal receiving the first system voltage and a second terminal coupled to the control terminal of the third transistor to stabilize the voltage at the control terminal of the third transistor.

4. The pixel circuit of claim 3, wherein during the first frame period when the gate signal is triggered, the first scan signal is at a low logic level corresponding to the high logic level of the gate signal, and the second scan signal is at a high logic level corresponding to the high logic level of the gate signal.

5. The pixel circuit of claim 4, wherein during the gate signal triggering interval of the first frame, the first transistor is turned on according to the gate signal and the first scan signal, and the second transistor is turned on according to the gate signal and the second scan signal to transmit the second scan signal to the second terminal of the storage capacitor.

6. The pixel circuit of claim 5, wherein the third transistor is turned off in response to the conduction of the first transistor, and the output transistor is turned on in accordance with the second scan signal transmitted to the second terminal of the storage capacitor, and outputs the second system voltage during the first frame.

7. The pixel circuit of claim 3, wherein during the second frame, when the gate signal is triggered, the first scan signal is at a high logic level corresponding to the high logic level of the gate signal, and the second scan signal is at a low logic level corresponding to the high logic level of the gate signal.

8. The pixel circuit of claim 7, wherein during the gate signal triggering interval of the second frame, the first transistor is turned on according to the gate signal and the first scan signal, and the second transistor is turned on according to the gate signal and the second scan signal to transmit the first scan signal to the first terminal of the storage capacitor.

9. The pixel circuit of claim 8, wherein the output transistor is turned off in response to the conduction of the second transistor, and the third transistor is turned on in accordance with the first scan signal transmitted to the first terminal of the storage capacitor, and outputs the first system voltage during the second frame.

10. An active array comprising: Multiple pixel circuits as claimed in claim 1, wherein the pixel circuits are arranged in an array; and Multiple pixel electrodes are each coupled to the pixel circuit to be driven by the first system voltage and the second system voltage periodically output by the pixel circuit.

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