High-precision power supply output correction method based on digital pre-distortion technology

Abstract

The invention discloses a high-precision power supply output correction method based on a digital pre-distortion technology, and relates to the technical field of power electronics, and the method comprises the steps: integrating an electricity-heat-magnetism real-time combined observer, and inputting parameters including a power supply output voltage, a current, a power device junction temperature, a magnetic element surface temperature, an environment temperature, and an input voltage ripple; using a hierarchical memory depth pre-distortion compensator to generate an anti-phase pre-distortion signal containing long time domain thermal constant compensation and short time domain capacitance energy storage compensation based on modeling engine output; based on a double-ring adaptive updating module, an inner ring updates electrical parameters, including on resistance and dead time, by taking a switching period as a reference, and an outer ring updates thermomagnetic parameters, including thermal resistance and a magnetic core saturation point, in a minute-level period; and the DAC is connected in series with a pre-distortion signal output end through an anti-interference execution channel, and comprises a noise shaping DAC and a driving stage for delay matching. According to the invention, through an electric-thermal-magnetic three-field combined observation architecture, the limitation of traditional single physical field monitoring is broken through.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, specifically to a high-precision power output correction method based on digital predistortion technology. Background Technology

[0002] In fields such as aerospace, medical equipment, and precision measuring instruments, the stability and accuracy of power output directly affect system performance, including signal acquisition errors and equipment lifespan. In the new energy field, such as photovoltaic inverters and energy storage systems, the requirements for power conversion efficiency and output harmonic suppression are increasing.

[0003] Causes of power supply output distortion include the influence of nonlinear components, such as power devices and transformers in the power supply, which are prone to nonlinear distortion when operating with large signals; load changes and interference, such as dynamic loads or electromagnetic interference, which can cause distortion of output voltage and current waveforms; and temperature and aging effects, such as the drift of power supply characteristics caused by changes in component parameters with temperature or aging after long-term use.

[0004] The introduction of digital predistortion technology has improved the power output distortion problem. Digital predistortion technology is mature in the field of communications, and its approach of pre-compensating for nonlinear characteristics can be applied to power correction scenarios to achieve high-precision dynamic adjustment.

[0005] Existing technologies still have room for iteration, mainly due to the complexity of nonlinear modeling. This leads to time-dependent distortion caused by factors such as capacitor energy storage and thermal time constants in the power supply, resulting in excessive complexity of Volterra series models. Electrical, thermal, and magnetic parameters interact with each other, making it difficult for a single electrical model to accurately describe them. For example, temperature changes cause MOSFET conduction characteristics to drift. Aging, load jumps, and other factors cause dynamic changes in model parameters, requiring support from highly robust adaptive algorithms. Summary of the Invention

[0006] To address the aforementioned technical problems, a high-precision power output correction method based on digital predistortion technology is provided. This technical solution solves the complexity problem of the aforementioned nonlinear modeling.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] A high-precision power output correction method based on digital predistortion technology includes:

[0009] S1, an integrated real-time electro-thermal-magnetic joint observer, with input parameters including power supply output voltage, current, power device junction temperature, magnetic component surface temperature and ambient temperature, and input voltage ripple;

[0010] S2. Using a hierarchical memory deep predistortion compensator, based on the modeling engine output, an inverse predistortion signal is generated that includes long-term thermal constant compensation and short-term capacitance energy storage compensation.

[0011] S3. Based on the dual-loop adaptive update module, the inner loop updates electrical parameters, including on-resistance and dead time, with the switching cycle as the reference, and the outer loop updates thermal and magnetic parameters, including thermal resistance and core saturation point, with a minute-level cycle.

[0012] S4, through the anti-interference execution channel, is connected in series to the predistortion signal output terminal, including the noise shaping DAC and the driver stage delay matching.

[0013] Preferably, S1 specifically includes:

[0014] Electrical parameter acquisition and output voltage detection employ a differential probe combined with a 16-bit Σ-Δ ADC and a 120dB common-mode rejection ratio circuit; a dynamic digital comb filter is used to suppress high-frequency switching noise; load current detection utilizes a shunt and a temperature drift compensation current mirror circuit, incorporating a junction temperature compensation algorithm; input voltage ripple extraction employs a 10MHz cutoff frequency high-frequency ripple detection channel; and carrier frequency correlation calculation technology is used to couple the ripple amplitude and switching frequency into a composite variable.

[0015] Thermal parameter fusion: By monitoring the junction temperature of power devices and using non-contact measurement with an infrared thermal imager of a predetermined band, a thermal network inversion model is established, in which an aging compensation factor is introduced for power loss; Magnetic component temperature tracking: An NTC patch sensor is mounted on the surface of the magnetic core, and a temperature-saturation point correlation model is established by combining a thermal accumulation integral algorithm; Ambient temperature reference calibration: Ambient temperature is monitored using a digital temperature sensor, and thermal resistance parameters are calibrated online.

[0016] Preferably, S1 specifically includes:

[0017] Magnetic parameter analysis: The rate of change of magnetic flux is captured by the induced voltage using a Rogowski coil, and the magnetic flux is restored by a temperature drift compensation integrator. The magnetic core cross-sectional area temperature is then used for calibration. Magnetic saturation point prediction: The saturation point is dynamically calculated based on the peak offset of the ripple spectrum. Recalibration is triggered when the rate of change of load current exceeds a predetermined threshold.

[0018] By outputting a six-dimensional state vector through the observer, a triple coupling is constructed: electrothermal coupling, which correlates junction temperature difference with current derivative to quantify transient characteristics of conduction loss; thermomagnetic coupling, in which the core temperature integral term reflects the heat accumulation effect and dynamically corrects the core loss model; and electromagnetic coupling, in which the ripple-frequency product term modulates the flux change rate to establish an input disturbance suppression channel.

[0019] Preferably, S2 specifically includes:

[0020] A hierarchical memory mechanism with a short-time domain compensation layer is used to establish a second-order differential model to address the transient energy storage effect of the output capacitor.

[0021]

[0022] In the formula, V pd_cap K represents the output voltage of the short-time domain compensation layer. c These are coefficients related to load jumps, used for dynamic calibration of load jumps; K is the second derivative of the load current, representing the rate at which the load current changes with time; da The coefficient is related to the dielectric absorption effect of ceramic capacitors; This is an integral term used to describe the output voltage V over the past 5 microseconds. out (τ) The cumulative effect after exponential decay on the current compensation voltage; V out (τ) represents the output voltage at time τ; e -(t-τ) / τda It is an exponential decay factor used to simulate the forgetting characteristics of the dielectric absorption effect in ceramic capacitors.

[0023] Preferably, S2 specifically includes:

[0024] The long-term compensation layer addresses the drift distortion caused by the thermal time constant.

[0025]

[0026] In the formula, V pd_thermal This is the voltage compensation amount caused by thermal effects in the long-time domain compensation layer, used to correct drift distortion caused by the thermal time constant; α T The coefficient is temperature-dependent, reflecting the degree to which temperature changes affect voltage drift; T j β is the junction temperature, i.e., the temperature of the junction inside a semiconductor device; 298 is the reference temperature, in Kelvin, here referring to 25 degrees Celsius; T The coefficient represents the heat accumulation effect, which characterizes the impact of heat accumulation generated by the load current on voltage drift. This is an integral term used to calculate the integral of the square of the load current over the past time interval τth(t) with respect to time; I load (τ) represents the load current at time τ. The integrand in the integral term is the square of the load current, reflecting the square relationship between the load current magnitude and the voltage drift. τth(t) is the thermal time constant, i.e., the aging decay model, used to describe the time scale of the thermal accumulation effect, that is, how long in the past the heat generated by the load current will have a significant impact on the current voltage compensation. The expression is τth(t). th (t)=τ th0 ·e -λt (λ=10-6 h -1 ), τ th0 The initial thermal time constant is λ = 10. -6 h -1 The aging decay coefficient, expressed in hours, represents the rate at which the thermal time constant decays exponentially with time, where t is a time variable used to represent the current moment.

[0027] Preferably, S2 specifically includes:

[0028] Short-time capacitance compensation employs nonlinear ESR modeling and monitors capacitor temperature in real time using infrared thermal imaging; dielectric absorption effect compensation addresses the issue that charge retention in ceramic capacitors leads to voltage recovery lag, causing ringing during load surges. The compensation algorithm utilizes a relaxation integral kernel function to reconstruct the impact of historical voltage; hardware acceleration involves deploying a convolutional operator on an FPGA.

[0029] Long-term thermal compensation and thermo-electric coupling modeling are divided into on-resistance drift and core saturation compensation; real-time aging tracking is carried out by using a thermal resistance degradation model to quantify the aging degree of the device based on the junction temperature rise rate and a lifespan prediction algorithm.

[0030] Preferably, S3 specifically includes:

[0031] The inner-loop electrical parameters are updated, with the update cycle strictly synchronized with the switching frequency of the power devices. The update is based on real-time junction temperature correction and dynamic compensation of on-resistance. The junction temperature is obtained from infrared thermal imaging data from the S1 observer. Dead time prediction is adaptively adjusted based on the derivative of the load current.

[0032] Preferably, S3 specifically includes:

[0033] The outer ring thermomagnetic parameters are updated, with the update cycle based on a predetermined time interval; the thermal resistance degradation model is combined with the cumulative aging over operating time; the core saturation point is calibrated by combining temperature integration and ripple spectrum.

[0034] Preferably, S4 specifically includes:

[0035] The noise-shaping DAC features a 128x oversampling architecture and employs a 5th-order Δ-Σ modulator to quantize the 16-bit predistorted signal to a 1-bit bitstream, shifting the quantization noise to a predetermined frequency band; temperature drift compensation is achieved through a built-in temperature sensor that corrects the reference voltage in real time.

[0036] Driver-level delay matching, adaptive delay line, dynamically adjusts transmission delay based on load current derivative; negative delay cancellation technology, pre-activates driver-level when the rate of change of load current is detected to be greater than a predetermined threshold.

[0037] Preferably, S4 specifically includes:

[0038] Anti-interference enhancement design, common-mode noise suppression, triple protection mechanism including symmetrical spiral traces, common-mode choke, and transconductance feedback loop; power jitter isolation, implementation of graded voltage regulation strategy and active cancellation principle;

[0039] Timing synchronization, clock tree phase calibration, including multi-node phase-locked loops and DLL-based phase interpolators; temperature-voltage compensation, and establishing lookup tables to correct VCO gain nonlinearity;

[0040] Driver-level transmission delay matching, four-channel differential balance, and a serpentine winding equal-length design.

[0041] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0042] This invention constructs a multi-physics real-time monitoring network using an electro-thermal-magnetic joint observer (S1). In the electrical layer, a differential sampling topology and a self-calibrated current mirror are used to achieve a voltage / current detection accuracy of ±0.05% within a 200kHz bandwidth. In the thermal layer, the junction temperature gradient of the power device is captured in real time through infrared thermal imaging, and a three-dimensional thermal distribution model is established by combining the temperature feedback of the magnetic core NTC. In the magnetic layer, the operating point of the magnetic core is inferred based on the ripple spectrum characteristics, and the transient magnetic flux change is reconstructed through Rogowski coils.

[0043] The problem of cross-scale distortion coupling is solved by using a hierarchical memory predistorter (S2). Short-time domain compensation addresses the transient energy storage effect of the output capacitor by establishing a relaxation integral model that includes nonlinear ESR and dielectric absorption to eliminate ringing caused by load step. Long-time domain compensation uses the thermal resistance degradation equation and the core saturation temperature drift model to perform feedforward correction on parameter shifts caused by material aging, achieving global distortion suppression.

[0044] The adaptive update module (S3) constructs a parameter self-evolution closed loop. The inner loop provides real-time compensation of the on-resistance, which is strictly synchronized with the switching frequency, and predicts the dead time by combining the load current derivative to eliminate switching transient voltage overshoot. The outer loop diagnoses the device aging status by measuring the junction temperature rise rate and recalibrates the magnetic saturation operating point by combining ripple spectrum offset.

[0045] The execution channel (S4) ensures lossless transmission of the predistorted signal. In the signal conversion layer, a 128x oversampling Δ-Σ architecture quantizes the predistorted signal into a 1-bit stream, achieving a 110dB dynamic range with a temperature-compensated reference source. In the timing control layer, a four-channel serpentine winding design with an adaptive delay line compresses the driver stage transmission deviation to sub-nanosecond levels. In the noise suppression layer, triple common-mode protection (spiral trace / nanocrystalline choke / transconductance feedback) achieves a 146dB common-mode rejection ratio, and a graded voltage regulation strategy attenuates power supply noise by -60dB. This safeguards the integrity of microvolt-level signals even in environments with strong electromagnetic interference. Attached Figure Description

[0046] Figure 1 This is a flowchart of a high-precision power output correction method based on digital predistortion technology. Detailed Implementation

[0047] The following description is intended to disclose the invention and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art.

[0048] Reference Figure 1 As shown, a high-precision power output correction method based on digital predistortion technology includes:

[0049] A high-precision power output correction method based on digital predistortion technology includes:

[0050] S1, an integrated real-time electro-thermal-magnetic joint observer, with input parameters including power supply output voltage, current, power device junction temperature, magnetic component surface temperature and ambient temperature, and input voltage ripple;

[0051] S2. Using a hierarchical memory deep predistortion compensator, based on the modeling engine output, an inverse predistortion signal is generated that includes long-term thermal constant compensation and short-term capacitance energy storage compensation.

[0052] S3. Based on the dual-loop adaptive update module, the inner loop updates electrical parameters, including on-resistance and dead time, with the switching cycle as the reference, and the outer loop updates thermal and magnetic parameters, including thermal resistance and core saturation point, with a minute-level cycle.

[0053] S4, through the anti-interference execution channel, is connected in series to the predistortion signal output terminal, including the noise shaping DAC and the driver stage delay matching.

[0054] It should be noted that the combined electro-thermal-magnetic observation is achieved through a six-dimensional state vector:

[0055]

[0056] In the formula, V is a six-dimensional state vector used to comprehensively characterize the real-time state of the system under the coupling effects of multiple physical fields such as electricity, heat, and magnetism; out The output voltage is a key state quantity of the system in terms of electrical properties, reflecting the voltage level at the circuit's output terminal. T represents the rate of change of the load current, measured in A / μs, and reflects the rate at which the load current changes over time. j -T a T is the difference between the junction temperature and the ambient temperature. j T represents the junction temperature of a semiconductor device. a Indicates ambient temperature; ∫(T) mag -Ta )dτ is the integral of the difference between the core temperature and the ambient temperature over time, where T mag This indicates the temperature of the magnetic core; dB / dt∣ rms Here, B represents the effective value of the rate of change of magnetic flux density; This refers to the fluctuation or deviation of the input voltage, usually expressed in per-unit values ​​or other relative quantities.

[0057] Real-time integration of switching losses, core saturation, and thermal accumulation effects breaks through the limitations of traditional single-physical-quantity observation.

[0058] Nonlinear mutual interference decoupling is achieved by using a gradient descent algorithm to separate coupled variables, such as the cross-effects of on-resistance temperature drift and core saturation, which improves the compensation accuracy by more than 5 times.

[0059] Full-scale temporal coverage:

[0060] Short-time domain (ns~μs), capacitor dielectric absorption compensation (τ) da =1.2μs) and dead time dynamic prediction (t dead ∝∣dI / dt∣ 0.7 Collaborative suppression of switch ringing.

[0061] Long-term (s~kh) thermal resistance degradation model and core saturation point drift compensation achieve 10-year accuracy maintenance.

[0062] S1 specifically includes:

[0063] Electrical parameter acquisition and output voltage detection employ a differential probe combined with a 16-bit Σ-Δ ADC and a 120dB common-mode rejection ratio circuit; a dynamic digital comb filter is used to suppress high-frequency switching noise; load current detection utilizes a shunt and a temperature drift compensation current mirror circuit, incorporating a junction temperature compensation algorithm; input voltage ripple extraction employs a 10MHz cutoff frequency high-frequency ripple detection channel; and carrier frequency correlation calculation technology is used to couple the ripple amplitude and switching frequency into a composite variable.

[0064] Thermal parameter fusion: By monitoring the junction temperature of power devices and using non-contact measurement with an infrared thermal imager of a predetermined band, a thermal network inversion model is established, in which an aging compensation factor is introduced for power loss; Magnetic component temperature tracking: An NTC patch sensor is mounted on the surface of the magnetic core, and a temperature-saturation point correlation model is established by combining a thermal accumulation integral algorithm; Ambient temperature reference calibration: Ambient temperature is monitored using a digital temperature sensor, and thermal resistance parameters are calibrated online.

[0065] Magnetic parameter analysis: The rate of change of magnetic flux is captured by the induced voltage using a Rogowski coil, and the magnetic flux is restored by a temperature drift compensation integrator. The magnetic core cross-sectional area temperature is then used for calibration. Magnetic saturation point prediction: The saturation point is dynamically calculated based on the peak offset of the ripple spectrum. Recalibration is triggered when the rate of change of load current exceeds a predetermined threshold.

[0066] By outputting a six-dimensional state vector through the observer, a triple coupling is constructed: electrothermal coupling, which correlates junction temperature difference with current derivative to quantify transient characteristics of conduction loss; thermomagnetic coupling, in which the core temperature integral term reflects the heat accumulation effect and dynamically corrects the core loss model; and electromagnetic coupling, in which the ripple-frequency product term modulates the flux change rate to establish an input disturbance suppression channel.

[0067] It should be noted that the electrical parameters were acquired as follows:

[0068] High-fidelity voltage detection with a differential probe architecture and fully symmetrical shielded trace design, combined with a common-mode rejection ratio (CMRR) enhancement circuit, achieves a 120dB rejection ratio at 1MHz, eliminating power-to-ground loop interference. The probe bandwidth is extended to 50MHz to meet the high-speed switching requirements of GaN / SiC devices.

[0069] The dynamic comb filter is a digital filter bank with adjustable frequency that attenuates the third harmonic (750kHz) by 60dB at a switching frequency of 250kHz, while preserving the fundamental frequency and low-frequency modulation signals.

[0070] Current sensing temperature drift suppression, current image compensation, and a temperature drift compensation circuit based on BJT matching pairs are constructed; the junction temperature T is controlled by... j Real-time correction of mirror ratio, maintaining an accuracy of ±0.05% within the range of -40℃ to 125℃; junction temperature compensation algorithm, establishing a shunt resistance model;

[0071] Ripple detection is carrier frequency related, with a high-frequency ripple channel. The 10MHz cutoff frequency detection circuit uses a current feedback amplifier (CFA) with a slew rate of 3000V / μs and a settling time of <15ns. An EMI filter (cutoff frequency 30MHz) is deployed at the input stage to suppress radio frequency interference.

[0072] Thermal parameter fusion:

[0073] Non-contact junction temperature monitoring with optimized infrared thermal imaging utilizes a 3.9-4.2μm band InGaAs sensor (0.1℃ resolution) to directly measure the chip junction temperature through the silicone encapsulation layer. Environmental radiation interference is eliminated through a multispectral fusion algorithm.

[0074] Core temperature tracking is achieved through NTC sensor deployment. A thin-film NTC (size 1.0×0.5mm) is attached to the edge of the core air gap, resulting in a thermal response time of <100ms. A constant current source excitation (100μA) is used to reduce the self-heating effect, and the influence of wire resistance is eliminated through four-wire measurement.

[0075] Ambient temperature calibration, online thermal resistance calibration, dynamic correction based on Newton's law of cooling, ambient temperature T a The thermal resistance value is monitored by a digital sensor (accuracy ±0.3℃) and updated every 60 seconds.

[0076] Analysis of magnetic parameters:

[0077] High-precision magnetic flux reproduction, Rogowski coil design, double-strand twisted wire winding (turns ratio 1:100), paired with a low-drift integrator, temperature compensation coefficient is calibrated in real time through Pt100 thin film resistor; cross-sectional area temperature drift correction, the cross-sectional area of ​​the magnetic core expands with temperature, avoiding magnetic flux calculation errors caused by thermal deformation.

[0078] Dynamic prediction of magnetic saturation point, detection of spectral peak shift, FFT analysis of output voltage (4096 points, Hanning window) to capture abrupt changes in third harmonic amplitude; recalibration trigger mechanism, with the load current change rate threshold set to |dI. load / dt|>50A / μs, with a response within 200ns achieved through an FPGA hardware comparator.

[0079] Triple coupling mechanism:

[0080] Electrothermal coupling (junction temperature-current derivative correlation), transient modeling of conduction loss, real-time thermal resistance correction, when |dI / dt|>100A / μs, the thermal resistance is temporarily adjusted to 1.15Rth to compensate for the heat transfer hysteresis under large current gradient;

[0081] Thermomagnetic coupling (temperature integral - magnetic loss correlation), thermal accumulation effect compensation, defining the temperature integral term of core loss, dynamically correcting the coefficients of the Steinmetz equation, aging early warning mechanism, triggering a derating strategy when the core loss temperature > 2000℃·s to prevent irreversible degradation of the core.

[0082] Electromagnetic coupling (ripple-frequency modulation) and disturbance suppression channels are used to generate feedforward compensation signals through composite variables to offset magnetic flux jumps caused by input voltage fluctuations; frequency-varying damping is enhanced by injecting active damping at the resonant frequency point to suppress magnetic saturation caused by high-frequency oscillations.

[0083] S2 specifically includes:

[0084] A hierarchical memory mechanism with a short-time domain compensation layer is used to establish a second-order differential model to address the transient energy storage effect of the output capacitor.

[0085]

[0086] In the formula, V pd_cap K represents the output voltage of the short-time domain compensation layer. c These are coefficients related to load jumps, used for dynamic calibration of load jumps; K is the second derivative of the load current, representing the rate at which the load current changes with time; da The coefficient is related to the dielectric absorption effect of ceramic capacitors; This is an integral term used to describe the output voltage V over the past 5 microseconds. out (τ) The cumulative effect after exponential decay on the current compensation voltage; V out (τ) represents the output voltage at time τ; e -(t-τ) / τda It is an exponential decay factor used to simulate the forgetting characteristics of the dielectric absorption effect in ceramic capacitors;

[0087] The long-term compensation layer addresses the drift distortion caused by the thermal time constant.

[0088]

[0089] In the formula, V pd_thermal This is the voltage compensation amount caused by thermal effects in the long-time domain compensation layer, used to correct drift distortion caused by the thermal time constant; α T The coefficient is temperature-dependent, reflecting the degree to which temperature changes affect voltage drift; T j β is the junction temperature, i.e., the temperature of the junction inside a semiconductor device; 298 is the reference temperature, in Kelvin, here referring to 25 degrees Celsius; T The coefficient represents the heat accumulation effect, which characterizes the impact of heat accumulation generated by the load current on voltage drift. This is an integral term used to calculate the integral of the square of the load current over the past time interval τth(t) with respect to time; I load (τ) represents the load current at time τ. The integrand in the integral term is the square of the load current, reflecting the square relationship between the load current magnitude and the voltage drift. τth(t) is the thermal time constant, i.e., the aging decay model, used to describe the time scale of the thermal accumulation effect, that is, how long in the past the heat generated by the load current will have a significant impact on the current voltage compensation. The expression is τth(t). th (t)=τ th0 ·e -λt (λ=10 -6 h -1 ), τ th0 The initial thermal time constant is λ = 10. -6 h -1The aging decay coefficient, in units of one hour, represents the rate at which the thermal time constant decays exponentially with time, where t is a time variable used to represent the current moment;

[0090] Short-time capacitance compensation employs nonlinear ESR modeling and monitors capacitor temperature in real time using infrared thermal imaging; dielectric absorption effect compensation addresses the issue that charge retention in ceramic capacitors leads to voltage recovery lag, causing ringing during load surges. The compensation algorithm utilizes a relaxation integral kernel function to reconstruct the impact of historical voltage; hardware acceleration involves deploying a convolutional operator on an FPGA.

[0091] Long-term thermal compensation and thermo-electric coupling modeling are divided into on-resistance drift and core saturation compensation; real-time aging tracking is carried out by using a thermal resistance degradation model to quantify the aging degree of the device based on the junction temperature rise rate and a lifespan prediction algorithm.

[0092] It should be noted that the hardware-accelerated architecture, FPGA convolutional processor, deploys 32-channel parallel computing units, uses the Winograd algorithm to optimize the convolutional kernel, consumes 15% of the DSP module, has a latency of <20ns, and a throughput of 1.28×10^9 multiply-accumulate operations per second.

[0093] Dynamic reconstruction automatically switches between three convolutional kernel sizes (3×3 / 5×5 / 7×7) based on the load change rate |dI / dt|.

[0094] Cross-timescale coordination, time-varying integral window control, dynamic time constant adjustment, and long-time domain integral window shrinking with running time avoid error accumulation caused by fixed window;

[0095] Transient-steady-state switching logic, triggered by load change rate, when |dI load When / dt|>50A / μs, the short-time domain compensation weight is increased to 85%, and the long-time domain integration is paused to prevent interference from sudden changes in thermal parameters;

[0096] The steady-state locking mechanism restores the full integration window and recalibrates the initial conditions after |dI / dt| < 5 A / μs for 200 ms.

[0097] S3 specifically includes:

[0098] The inner loop electrical parameters are updated, with the update cycle strictly synchronized with the switching frequency of the power devices. The update is based on real-time correction of junction temperature and dynamic compensation of on-resistance. The junction temperature is obtained from infrared thermal imaging data from the S1 observer. Dead time is predicted and adaptively adjusted according to the derivative of the load current.

[0099] The outer ring thermomagnetic parameters are updated, with the update cycle based on a predetermined time interval; the thermal resistance degradation model is combined with the cumulative aging over operating time; the core saturation point is calibrated by combining temperature integration and ripple spectrum.

[0100] It should be noted that the inner ring electrical parameters have been updated:

[0101] The switching cycle synchronization mechanism uses a hardware-level phase-locked loop (PLL) to lock the update cycle to the switching cycle T. sw Integer multiples of (usually 1×T) sw 2×T sw Clock jitter <±20ps, ensuring accurate alignment of power transistor switching events at a 250kHz switching frequency (Tsw=4μs);

[0102] Real-time interrupt response: Zero-crossing events are detected by the FPGA hardware comparator, and parameter updates are completed within 200ns after the switching transistor is turned off, avoiding interference with the freewheeling process.

[0103] Dynamic compensation of on-resistance, multi-pulse online calibration, injecting 10mA micro-current during dead time, measuring on-voltage drop to deduce resistance value;

[0104] Dead time prediction algorithm with adaptive adjustment of current derivative. When |dI / dt|>100A / μs, negative delay compensation is activated to eliminate the reverse recovery charge effect of GaN devices.

[0105] Outer ring thermomagnetic parameters updated:

[0106] Thermal resistance degradation modeling and aging accumulation quantification are based on the Arrhenius-EM model; junction temperature rise rate diagnosis is performed, and an aging coefficient is defined, triggering thermal resistance recalibration when the aging coefficient > 5%;

[0107] Core saturation point calibration, temperature-ripple joint calibration saturation point dynamic correction formula:

[0108] B sat =B0·[1-1.1×10 -3 ∫(T mag -353)dτ]-K f ·Δf ripple

[0109] In the formula, B sat B0 is the saturation flux density of the magnetic core after calibration; B0 is the initial saturation flux density of the magnetic core; ∫(T mag -353)dτ is the integral term of the core temperature difference with respect to time; K f Δf is the dynamic correction coefficient for the saturation point, with a value of 0.15; ripple Ripple spectral offset rate;

[0110] Recalibration trigger conditions are met to activate the function:

[0111] If |dI / dt| > 50A / μs (hardware interrupt response), and the cumulative running time reaches 60 minutes, Δf ripple >3%.

[0112] Dual-ring collaboration, cross-ring data interaction mechanism

[0113] Inner loop → outer loop parameter transfer

[0114] Passing parameters Update cycle effect <![CDATA[(dT j / dt) max ]]> Every 4μs Core input for outer ring aging diagnosis $ dI / dt _{\text{peak}}$

[0115] Parameter transfer from outer loop to inner loop

[0116] Passing parameters Update cycle effect Rth(t) Every 60 minutes Internal junction temperature inversion model correction Bsat Event triggered Dynamic adjustment benchmark for dead time compensation

[0117] The safety protection strategy, through compensation circuit breaker logic, when the predistortion signal amplitude is |V pd |>0.3V dc hour:

[0118] V pd ←sign(V pd )·min(0.28V dc ,∣V pd ∣)

[0119] In the formula, V pd V represents the predistorted signal amplitude, indicating the signal amplitude used for compensation in the system. dc For DC voltage; sign(V) pd ) is a symbolic function used to preserve V. pd The sign of the positive or negative value; min(0.28V) dc ,∣V pd |) To take the smaller value function, compare 0.28 times the DC voltage and V. pd Take the smaller of the two absolute values ​​to avoid the power transistor entering the linear region.

[0120] The parameter freeze mechanism pauses outer loop updates during load mutations (|dI / dt|>200A / μs) to prevent miscalibration.

[0121] S4 specifically includes:

[0122] The noise-shaping DAC features a 128x oversampling architecture and employs a 5th-order Δ-Σ modulator to quantize the 16-bit predistorted signal to a 1-bit bitstream, shifting the quantization noise to a predetermined frequency band; temperature drift compensation is achieved through a built-in temperature sensor that corrects the reference voltage in real time.

[0123] Driver-level delay matching, adaptive delay line, dynamically adjusts transmission delay based on load current derivative; negative delay cancellation technology, pre-activates driver-level when the rate of change of load current is detected to be greater than a predetermined threshold.

[0124] Anti-interference enhancement design, common-mode noise suppression, triple protection mechanism including symmetrical spiral traces, common-mode choke, and transconductance feedback loop; power jitter isolation, implementation of graded voltage regulation strategy and active cancellation principle;

[0125] Timing synchronization, clock tree phase calibration, including multi-node phase-locked loops and DLL-based phase interpolators; temperature-voltage compensation, and establishing lookup tables to correct VCO gain nonlinearity;

[0126] Driver-level transmission delay matching, four-channel differential balance, and a serpentine winding equal-length design.

[0127] It should be noted that the noise-shaping DAC:

[0128] The architecture features a 128x oversampling factor, a 5th-order Δ-Σ modulation core, and a cascaded integrator feedback (CIFF) structure. Its transfer function is:

[0129]

[0130] In the formula, H(z) is the noise transfer function, which describes the transmission characteristics of the noise signal in the system, that is, how the input noise is shaped and transmitted to the output through the system; z -1 The unit delay operator, used in discrete-time signal processing, represents the delay of one sampling period; 1-z -1 It is a difference operator that represents the difference between two consecutive sampled values ​​of the signal, i.e., x(n)-x(n-1);

[0131] The noise transfer function quantizes a 16-bit predistorted signal in the 0-5V range into a 1-bit bitstream, achieving a signal-to-noise ratio of 110dB within a 20MHz bandwidth;

[0132] Quantization noise frequency shifting, through zero-point optimization, pushes noise energy to the >50MHz frequency band (suppression ratio 120dB) to avoid overlap with the power switching frequency band (20-500kHz);

[0133] Reference voltage temperature drift compensation:

[0134] Temperature-voltage closed-loop correction, the reference voltage source adopts a bandgap structure, and the built-in PTAT current source is calibrated in real time. The drift is <±2ppm / ℃ across the entire temperature range (-40~125℃).

[0135] Driver-level latency matching:

[0136] Adaptive delay line, load current derivative response, dynamic adjustment model for propagation delay, activates the nonlinear compensation term +0.15e when |dI / dt|>80A / μs. -t / 100ns ns;

[0137] The negative delay cancellation technology, a pre-activated drive mechanism, is based on load current change rate prediction and uses charge pre-injection by the GaN driver to cancel the storage effect of the output capacitor.

[0138] Four-channel differential balance

[0139] The serpentine winding design with equal length uses 7-layer PCB redundant winding, with a length matching error of <0.05mm (equivalent timing difference ±0.16ps);

[0140] Anti-interference enhancement design:

[0141] Triple common-mode noise suppression, symmetrical spiral routing, and drive signal lines laid out in an Archimedean spiral (line width / spacing = 3:1) cancel the loop antenna effect and reduce radiated EMI by 18dBμV / m.

[0142] The common-mode choke was optimized by using a nanocrystalline magnetic core (initial permeability μi≥80,000), and the impedance ZCM>2kΩ at a frequency of 100MHz.

[0143] A transconductance feedback loop (OTA) is used to construct an operational transconductance amplifier with gm≥0.2S, and an inverting common-mode current is injected in real time, which improves the common-mode rejection ratio (CMRR) to 146dB@1MHz;

[0144] Power supply jitter isolation, graded voltage regulation strategy:

[0145] hierarchy voltage regulator Noise suppression index use Level 1 LDO (LT3045) PSRR = 110dB @ 100kHz DAC reference power supply Level 2 π-type filter Attenuation -60dB@10MHz Driver IC Digital Power Supply Level 3 Active cancellation circuit Suppression ratio 45dB Power stage gate drive

[0146] Timing synchronization:

[0147] Multi-node phase-locked loop (PLL), phase interpolator design, based on an 8-bit phase interpolator of delay phase-locked loop (DLL), with a resolution Δφ = 360 / 256 ≈ 1.4;

[0148] Temperature-voltage compensation, VCO gain nonlinearity correction, and establishment of a two-dimensional lookup table (LUT):

[0149]

[0150]

[0151] Continuous compensation is achieved through polynomial interpolation, with VCO frequency drift <±50ppm.

[0152] Implementation steps:

[0153] Step 1: Hardware self-calibration

[0154] Upon power-up, the electro-thermal-magnetic joint observer (S1) is activated to perform zero-point calibration on the voltage / current sampling channels; the infrared thermal imaging module performs automatic focus adjustment to ensure that the spatial resolution for power device junction temperature monitoring reaches 0.1mm. 2 ;

[0155] Step 2: Environmental Parameter Collection

[0156] Simultaneously read ambient temperature, input voltage ripple spectrum, and initial temperature of magnetic components to construct a thermal network baseline model;

[0157] Step 3: Multiphysics Field Synchronous Acquisition

[0158] Electrical layer: Captures output voltage / current transient waveforms at a 2MHz sampling rate (16-bit ADC);

[0159] Thermal layer: The junction temperature distribution map of the power device is refreshed every 100μs (3D temperature field reconstruction);

[0160] Magnetic layer: The rate of change of magnetic flux is calculated in real time using Rogowski coils (accuracy ±1.5mT);

[0161] Step 4: Joint Status Diagnosis

[0162] Input electrical / thermal / magnetic data into the coupled modeling engine, and output capacitance energy storage coefficient, thermal resistance degradation factor, and magnetic saturation offset;

[0163] Step 5: Short-time domain capacitance compensation

[0164] A relaxation integral kernel function is constructed based on the capacitor energy storage coefficient to calculate the μs-level transient voltage compensation (suppressing ringing); the ESR nonlinear model is dynamically corrected by combining infrared temperature data.

[0165] Step 6: Long-term thermomagnetic compensation

[0166] The thermal resistance degradation equation is used to predict the aging drift (time scale: hours → years), and the anti-hysteresis pre-distortion component is generated based on the magnetic saturation offset.

[0167] Step 7: Signal Synthesis

[0168] By superimposing short-time domain and long-time domain compensation amounts, a 16-bit inverted predistortion digital signal is generated.

[0169] Step 8: Inner loop electrical parameters refresh (nanosecond level)

[0170] Perform the following in each switching cycle (e.g., 4μs@250kHz): update the on-resistance compensation coefficient based on the real-time junction temperature, and predict the dead time (dynamic range: 40~150ns) based on the load current derivative.

[0171] Step 9: Update outer ring thermomagnetic parameters (minute-level)

[0172] Execute periodically (e.g., every 60 minutes) or when triggered by an event: Analyze the junction temperature rise rate to diagnose the device aging level and recalibrate the core saturation point using ripple spectrum characteristics;

[0173] Step 10: High-fidelity digital-to-analog conversion

[0174] The 128x oversampling Δ-ΣDAC converts the predistorted signal into a 1-bit bitstream (110dB dynamic range), and the built-in temperature sensor corrects the reference voltage in real time (drift <±2ppm / ℃).

[0175] Step 11: Driver-level timing control

[0176] Adaptive delay line dynamically matches the transmission path (four-channel deviation < ±0.25ns), and activates negative delay pre-drive when the load current change rate is detected to be >100A / μs;

[0177] Step 12: Multi-level noise suppression

[0178] Common-mode triple protection: spiral trace layout + nanocrystalline choke + transconductance feedback loop (146dBCMRR); graded voltage regulation strategy to isolate power supply jitter (PSRR>110dB@100kHz);

[0179] Step 13: Real-time closed-loop control

[0180] After the predistortion signal is injected into the power stage, the actual output waveform is acquired through the S1 observer; the residual between the target waveform and the actual waveform is compared and fed back to the S2 compensator for gain fine-tuning;

[0181] Step 14: Fault Circuit Breaker

[0182] Protection is triggered when the predistortion signal amplitude exceeds the threshold (>30% Vdc):

[0183] The parameters are frozen and updated; the system switches to traditional PID mode and triggers an alarm.

[0184] Step 15: Aging Adaptation

[0185] The outer ring update module automatically increases the thermal compensation weight (annual scale adjustment) based on the coefficient; environmental adaptability: when the ambient temperature changes by more than 10°C, the calibration process in step one is forcibly rerun; data traceability: all parameter update records are encrypted and stored for iterative training of the lifetime prediction model.

[0186] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention. The scope of protection claimed by the appended claims and their equivalents is defined.

Claims

1. A high-precision power output correction method based on digital predistortion technology, characterized in that, include: S1, an integrated real-time electro-thermal-magnetic joint observer, with input parameters including power supply output voltage, current, power device junction temperature, magnetic component surface temperature and ambient temperature, and input voltage ripple; S2. Using a hierarchical memory deep predistortion compensator, based on the modeling engine output, an inverse predistortion signal is generated that includes long-term thermal constant compensation and short-term capacitance energy storage compensation. S3. Based on the dual-loop adaptive update module, the inner loop updates electrical parameters, including on-resistance and dead time, with the switching cycle as the reference, and the outer loop updates thermal and magnetic parameters, including thermal resistance and core saturation point, with a minute-level cycle. S4, through the anti-interference execution channel, is connected in series to the predistortion signal output terminal, including the noise shaping DAC and the driver stage delay matching.

2. The high-precision power output correction method based on digital predistortion technology according to claim 1, characterized in that, S2 specifically includes: A hierarchical memory mechanism with a short-time domain compensation layer is used to establish a second-order differential model to address the transient energy storage effect of the output capacitor. In the formula, V pd_cap K represents the output voltage of the short-time domain compensation layer. c These are coefficients related to load jumps, used for dynamic calibration of load jumps; K is the second derivative of the load current, representing the rate at which the load current changes with time; da The coefficient is related to the dielectric absorption effect of ceramic capacitors; This is an integral term used to describe the output voltage V over the past 5 microseconds. out (τ) The cumulative effect after exponential decay on the current compensation voltage; V out (τ) represents the output voltage at time τ; e -(t-τ) / τda It is an exponential decay factor used to simulate the forgetting characteristics of the dielectric absorption effect in ceramic capacitors.

3. The high-precision power output correction method based on digital predistortion technology according to claim 2, characterized in that, S2 specifically includes: The long-term compensation layer addresses the drift distortion caused by the thermal time constant. In the formula, V pd_thermal This is the voltage compensation amount caused by thermal effects in the long-time domain compensation layer, used to correct drift distortion caused by the thermal time constant; α T The coefficient is temperature-dependent, reflecting the degree to which temperature changes affect voltage drift; T j β is the junction temperature, i.e., the temperature of the junction inside a semiconductor device; 298 is the reference temperature, in Kelvin, here referring to 25 degrees Celsius; T The coefficient represents the heat accumulation effect, which characterizes the impact of heat accumulation generated by the load current on voltage drift. This is an integral term used to calculate the integral of the square of the load current over the past time interval τth(t) with respect to time; I load (τ) represents the load current at time τ. The integrand in the integral term is the square of the load current, reflecting the square relationship between the load current magnitude and the voltage drift. τth(t) is the thermal time constant, i.e., the aging decay model, used to describe the time scale of the thermal accumulation effect, that is, how long in the past the heat generated by the load current will have a significant impact on the current voltage compensation. The expression is τth(t). th (t)=τ th0 ·e -λt (λ=10 -6 h -1 ), τ th0 The initial thermal time constant is λ = 10. -6 h -1 The aging decay coefficient, expressed in hours, represents the rate at which the thermal time constant decays exponentially with time, where t is a time variable used to represent the current moment.

4. The high-precision power output correction method based on digital predistortion technology according to claim 3, characterized in that, S2 specifically includes: Short-time capacitance compensation employs nonlinear ESR modeling and monitors capacitor temperature in real time using infrared thermal imaging; dielectric absorption effect compensation addresses the issue that charge retention in ceramic capacitors leads to voltage recovery lag, causing ringing during load surges. The compensation algorithm utilizes a relaxation integral kernel function to reconstruct the impact of historical voltage; hardware acceleration involves deploying a convolutional operator on an FPGA. Long-term thermal compensation and thermo-electric coupling modeling are divided into on-resistance drift and core saturation compensation; real-time aging tracking is carried out by using a thermal resistance degradation model to quantify the aging degree of the device based on the junction temperature rise rate and a lifespan prediction algorithm.

5. A high-precision power output correction method based on digital predistortion technology according to claim 4, characterized in that, S1 specifically includes: Electrical parameter acquisition and output voltage detection employ a differential probe combined with a 16-bit Σ-Δ ADC and a 120dB common-mode rejection ratio circuit; a dynamic digital comb filter is used to suppress high-frequency switching noise; load current detection utilizes a shunt and a temperature drift compensation current mirror circuit, incorporating a junction temperature compensation algorithm; input voltage ripple extraction employs a 10MHz cutoff frequency high-frequency ripple detection channel; and carrier frequency correlation calculation technology is used to couple the ripple amplitude and switching frequency into a composite variable. Thermal parameter fusion: By monitoring the junction temperature of power devices and using non-contact measurement with an infrared thermal imager of a predetermined band, a thermal network inversion model is established, in which an aging compensation factor is introduced for power loss; Magnetic component temperature tracking: An NTC patch sensor is mounted on the surface of the magnetic core, and a temperature-saturation point correlation model is established by combining a thermal accumulation integral algorithm; Ambient temperature reference calibration: Ambient temperature is monitored using a digital temperature sensor, and thermal resistance parameters are calibrated online.

6. A high-precision power output correction method based on digital predistortion technology according to claim 5, characterized in that, S1 specifically includes: Magnetic parameter analysis: The rate of change of magnetic flux is captured by the induced voltage using a Rogowski coil, and the magnetic flux is restored by a temperature drift compensation integrator. The magnetic core cross-sectional area temperature is then used for calibration. Magnetic saturation point prediction: The saturation point is dynamically calculated based on the peak offset of the ripple spectrum. Recalibration is triggered when the rate of change of load current exceeds a predetermined threshold. By outputting a six-dimensional state vector through the observer, a triple coupling is constructed: electrothermal coupling, which correlates junction temperature difference with current derivative to quantify transient characteristics of conduction loss; thermomagnetic coupling, in which the core temperature integral term reflects the heat accumulation effect and dynamically corrects the core loss model; and electromagnetic coupling, in which the ripple-frequency product term modulates the flux change rate to establish an input disturbance suppression channel.

7. A high-precision power output correction method based on digital predistortion technology according to claim 6, characterized in that, S3 specifically includes: The inner-loop electrical parameters are updated, with the update cycle strictly synchronized with the switching frequency of the power devices. The update is based on real-time junction temperature correction and dynamic compensation of on-resistance. The junction temperature is obtained from infrared thermal imaging data from the S1 observer. Dead time prediction is adaptively adjusted based on the derivative of the load current.

8. A high-precision power output correction method based on digital predistortion technology according to claim 7, characterized in that, S3 specifically includes: The outer ring thermomagnetic parameters are updated, with the update cycle based on a predetermined time interval; the thermal resistance degradation model is combined with the cumulative aging over operating time; the core saturation point is calibrated by combining temperature integration and ripple spectrum.

9. A high-precision power output correction method based on digital predistortion technology according to claim 8, characterized in that, S4 specifically includes: The noise-shaping DAC features a 128x oversampling architecture and employs a 5th-order Δ-Σ modulator to quantize the 16-bit predistorted signal to a 1-bit bitstream, shifting the quantization noise to a predetermined frequency band; temperature drift compensation is achieved through a built-in temperature sensor that corrects the reference voltage in real time. Driver-level delay matching, adaptive delay line, dynamically adjusts transmission delay based on load current derivative; negative delay cancellation technology, pre-activates driver-level when the rate of change of load current is detected to be greater than a predetermined threshold.

10. A high-precision power output correction method based on digital predistortion technology according to claim 9, characterized in that, S4 specifically includes: Anti-interference enhancement design, common-mode noise suppression, triple protection mechanism including symmetrical spiral traces, common-mode choke, and transconductance feedback loop; power jitter isolation, implementation of graded voltage regulation strategy and active cancellation principle; Timing synchronization, clock tree phase calibration, including multi-node phase-locked loops and DLL-based phase interpolators; temperature-voltage compensation, and establishing lookup tables to correct VCO gain nonlinearity; Driver-level transmission delay matching, four-channel differential balance, and a serpentine winding equal-length design.

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