Digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input

Abstract

The invention discloses a digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input. The digital-to-analog converter interface circuit comprises an ESD protection circuit, a DEMUX multiplexer, an MUX multiplexer, an LVDS receiver, an inverter chain and a digital logic circuit. The output end of the ESD protection circuit is connected with the DEMUX demultiplexer; the digital logic circuit is used for generating a synchronous control signal according to an external mode switching signal and coordinating the working state of each module; the DEMUX demultiplexer distributes an input signal output by the ESD protection circuit to a corresponding signal processing path under the action of a control signal output by the digital logic circuit; the LVDS receiver receives the LVDS signal, converts the LVDS signal into a single-ended CMOS signal, and outputs the single-ended CMOS signal to the MUX multiplexer; the inverter chain is used for receiving a CMOS signal; and the MUX multiplexer outputs a control signal according to the digital logic circuit, so that one of the two paths of input signals is selected to be output to the DAC core circuit. According to the invention, LVDS / CMOS dual-mode input is efficiently supported in a single chip, and meanwhile, the requirements of high speed, low power consumption and time sequence consistency are met.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, specifically relating to a digital-to-analog converter (DAC) interface circuit with dual-mode input compatibility, particularly suitable for applications that simultaneously support LVDS high-speed differential signals and CMOS single-ended signal inputs. This interface circuit enables integrated compatibility design of LVDS and CMOS signals, meeting the needs of modern electronic systems for multi-rate signal processing. Background Technology

[0002] As a key component connecting digital and analog signals, the compatibility and flexibility of the interface circuit of a digital-to-analog converter (DAC) directly affect the complexity and cost of system design. In modern electronic systems, digital signal input interfaces primarily use two standards: LVDS and CMOS signals.

[0003] LVDS interface: With its low power consumption, high speed, and strong anti-interference capabilities, it is widely used in long-distance transmission, video processing, and communication equipment. For example, the dual-port LVDS interface of Analog Devices' AD9739 RF DAC supports a high sampling rate of 2500Msps.

[0004] CMOS interfaces are characterized by their simple structure, low cost, and low voltage compatibility, and are commonly used in low-speed applications such as consumer electronics and embedded control.

[0005] With the surge in demand for multi-rate signal processing in fields such as 5G communication and medical imaging, the DAC front-end interface needs to be adapted to both Gbps-level LVDS high-speed streams and 100Mbps-level CMOS low-speed control signals. However, the significant differences between the two signals in terms of electrical characteristics, processing mechanisms and power consumption requirements make it difficult for the existing single-mode interface architecture to meet the requirements of integrated design.

[0006] Existing technologies have failed to effectively achieve integrated compatibility design between LVDS and CMOS signals. The core challenge lies in the fundamental conflict between the electrical characteristics of the two types of signals.

[0007] 1. Differences in signal form and processing mechanism: LVDS uses differential pairs to transmit low-swing signals, typically 350mV, relies on a dedicated receiver for level conversion, and requires matching 100Ω transmission line impedance to suppress signal reflection; while CMOS signals are single-ended full-swing signals, requiring edge shaping and drive enhancement through an inverter chain. The input impedance, amplification mechanism, and noise margin requirements of the two are completely different, making it difficult to reuse traditional circuit architectures.

[0008] 2. The trade-off between power consumption and performance: To achieve high-speed amplification, LVDS receivers require analog circuits with high bias current, typically operating at 10–15 mA. However, the dynamic power consumption of the inverter chain in the CMOS path increases linearly with frequency. Traditional designs cannot effectively shut down high-speed circuits in low-speed mode, resulting in excessively high redundant power consumption, which is unacceptable for battery-powered devices.

[0009] 3. Increased compatibility complexity: Even if a few solutions attempt to achieve dual-mode input capability of the DAC interface, they face the challenge of increased compatibility complexity, including the synchronization problem of control logic and the parasitic effects of layout design.

[0010] In summary, existing technologies, limited by differences in signal characteristics, power consumption optimization bottlenecks, and the complexity of compatibility design, have not yet achieved a DAC interface circuit that can efficiently support LVDS / CMOS dual-mode input within a single chip while simultaneously meeting the requirements of high speed, low power consumption, and timing consistency. Therefore, a novel interface architecture with switchable modes, self-isolated paths, and dynamic power consumption optimization is designed to break through the application boundaries of traditional single-mode designs and meet current needs. Summary of the Invention

[0011] A brief overview of embodiments of the invention is provided below to provide a basic understanding of certain aspects of the invention. It should be understood that this overview is not an exhaustive summary of the invention. It is not intended to identify key or essential parts of the invention, nor is it intended to limit the scope of the invention. Its purpose is merely to present certain concepts in a simplified form as a prelude to the more detailed description that follows.

[0012] To address the issues of insufficient compatibility with a single interface and complex mode switching control in existing technologies, this invention provides a digital-to-analog converter interface circuit that supports LVDS / CMOS dual-mode input. Through configurable signal path switching and dynamic power consumption optimization mechanisms, it overcomes the application limitations of traditional DAC interfaces that only support a single signal type, while also solving the problems of timing mismatch and redundant power consumption during dual-mode switching.

[0013] According to one aspect of this application, a digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input is provided, which includes an ESD protection circuit, a DEMUX multiplexer, a MUX multiplexer, an LVDS receiver, an inverter chain, and digital logic circuits.

[0014] The ESD protection circuit receives the input signal at its input terminal and connects to the DEMUX multiplexer at its output terminal. This ESD protection circuit provides electrostatic discharge protection for the input signal, preventing damage to the DEMUX multiplexer and its internal circuitry by clamping overvoltage and releasing overcurrent, thus ensuring the reliability and stability of the interface circuitry.

[0015] The digital logic circuit is used to generate synchronization control signals based on external mode switching signals to coordinate the working states of each module. The synchronization control signals include the SEL1 signal for controlling the input distribution of the DEMUX multiplexer, the LVDS_PD signal for controlling the LVDS to enter power-down mode, and the SEL2 signal for controlling the MUX to make selections.

[0016] The DEMUX multiplexer, under the action of the digital logic circuit output control signal SEL1, distributes the input signal output by the ESD protection circuit to the corresponding signal processing path. Its input is connected to the output of the ESD protection circuit, and the output includes: a first output branch OUT1, connected to the input of the inverter chain for transmitting single-ended CMOS signals; and a second output branch OUT2, connected to the differential input of the LVDS receiver for transmitting differential LVDS signals. In high sampling rate mode, the input signal is switched to the second output branch OUT2, enabling the LVDS signal path; in low sampling rate mode, the input signal is switched to the first output branch OUT1, enabling the CMOS signal path.

[0017] The LVDS receiver receives LVDS signals, converts them into single-ended CMOS signals, and outputs them to the MUX multiplexer. The positive input receives the INP signal, and the negative input receives the INN signal. In high sampling rate mode, the receiver receives the LVDS signal, converts it to a CMOS level signal, and outputs it to the first input of the MUX. In low sampling rate mode, the LVDS receiver enable signal LVDS_PD puts the receiver into a power-down state, and its output is in a high-impedance state to avoid interference with the CMOS signal path.

[0018] The inverter chain receives CMOS signals, with its input connected to a DEMUX multiplexer and its output connected to a MUX multiplexer. It buffers, shapes, and enhances the single-ended CMOS signal. In low sampling rate mode, the input receives a single-ended CMOS signal, which, after processing by N stages of inverters, outputs a standard CMOS signal that meets the input requirements of the MUX multiplexer to its second input. The delay characteristics of this inverter chain are precisely designed to ensure matching with the total delay of the LVDS signal path in high sampling rate mode, achieving timing consistency for dual-mode input.

[0019] The MUX multiplexer is used to select one output signal from two input signals to the DAC core circuit under the control of the digital logic circuit output control signal SEL2. Its input terminals connect to the inverter chain of the LVDS receiver output and the INP signal input branch. In high sampling rate mode, it selects the LVDS output signal to output to the DAC core circuit; in low sampling rate mode, it selects the output signal of the INP input branch inverter chain to output to the DAC core circuit.

[0020] Further, the ESD protection circuit includes a first ESD protection circuit and a second ESD protection circuit; the DEMUX multiplexer includes a first DEMUX multiplexer and a second DEMUX multiplexer (DEMUX2); the inverter chain includes a first inverter chain (INP branch) and a second inverter chain (INN branch); the SEL1 signal is also used for topology switching of the high-speed analog switch in the first ESD protection circuit and for switching the conduction state of the NMOS transistor M1 in the second ESD protection circuit; the first ESD protection circuit receives the input signal and the SEL1 signal at its input terminal and its output terminal is connected to the first DEMUX multiplexer; the second ESD protection circuit receives the input signal and the SEL1 signal at its input terminal and its output terminal is connected to the second DEMUX multiplexer; the output terminal of the first DEMUX multiplexer includes:

[0021] First output branch OUT1: Connected to the input of the first inverter chain, used to transmit single-ended CMOS signals;

[0022] The second output branch OUT2 is connected to the positive differential input of the LVDS receiver and is used to transmit differential LVDS signals.

[0023] The outputs of the second DEMUX multiplexer include:

[0024] First output branch OUT1: Connected to the input of the second inverter chain, it is used only as an impedance matching load when a single-ended CMOS signal is input, and does not transmit the actual signal;

[0025] The second output branch OUT2 is connected to the negative differential input of the LVDS receiver and is used to transmit differential LVDS signals.

[0026] Furthermore, the first ESD protection circuit includes a high-speed analog switch, an LVDS-ESD protection circuit, and a CMOS-ESD protection circuit. The common terminal of the high-speed analog switch is connected to the positive terminal of INP and the SEL1 signal. The S1 terminal of the high-speed analog switch is connected to the LVDS-ESD protection circuit, and the S2 terminal of the high-speed analog switch is connected to the CMOS-ESD protection circuit. When SEL1 = 1, the high-speed analog switch switches the INP branch to the S1 terminal, forming LVDS differential protection. When SEL1 = 0, the high-speed analog switch switches the INP branch to the S2 terminal, forming CMOS single-ended protection.

[0027] The second ESD protection circuit includes an LVDS-ESD protection circuit and an NMOS transistor. The gate of the NMOS transistor is connected to the SEL1 signal, the drain of the NMOS transistor is connected to the output terminal of the LVDS-ESD protection circuit, and the source of the NMOS transistor is grounded.

[0028] The SEL1 signal is sent to the first ESD protection circuit and the second ESD protection circuit. The protection circuit will be switched in the INP branch (first ESD protection circuit), and the M1 transistor will be turned on in the INN branch (second ESD protection circuit). The INN branch is grounded to eliminate the uncertain state.

[0029] This digital-to-analog converter interface circuit, which supports LVDS / CMOS dual-mode input, has two operating modes:

[0030] High sampling rate mode: When the external mode switching signal MODE is high, the interface circuit enters high sampling rate mode, which is suitable for LVDS differential signal input scenarios. The specific process is as follows:

[0031] S1, ESD Protection Stage: The LVDS differential signal first passes through the dedicated LVDS protection unit of the ESD protection circuit to ensure that overvoltage / overcurrent in the input signal is suppressed within a safe range.

[0032] S2, Signal Distribution Stage: The differential signal processed by the ESD protection circuit enters the DEMUX multiplexer. Under the control of the digital logic circuit output control signal SEL1, DEMUX directs the signal to the second output terminal OUT2, which is directly connected to the differential input terminal of the LVDS receiver.

[0033] S3, Signal Conversion Stage: The LVDS receiver is activated by the enable signal LVDS_PD, converting the differential signal into a single-ended CMOS signal.

[0034] S4, Signal Selection Stage: Under the control of the control signal SEL2, the MUX multiplexer selects the output signal of the LVDS receiver and transmits the signal to the DAC core circuit.

[0035] Low sampling rate mode: When the external mode switching signal MODE is low, the interface circuit switches to low sampling rate mode to adapt to single-ended CMOS signal input, which is connected through the INP interface. The specific process is as follows:

[0036] S1, ESD Protection Stage: The CMOS single-ended signal first passes through the dedicated CMOS protection unit of the ESD protection circuit, which can suppress high-frequency noise and clamp the input voltage within a safe range.

[0037] S2, Signal Distribution Stage: Under the control of the control signal SEL1, the first DEMUX multiplexer directs the ESD output signal to the first output terminal OUT1 and connects it to the first inverter chain. At the same time, the digital logic circuit cuts off the self-bias current of the LVDS receiver through the LVDS_PD signal, causing it to enter a deep power-down state and reduce system power consumption.

[0038] S3, Signal Conditioning Stage: The CMOS signal enters the inverter chain for shaping and drive enhancement: the first-stage inverter matches the DEMUX output impedance to reduce signal reflection; the intermediate-stage inverter optimizes the rise / fall time to eliminate edge jitter; the final-stage inverter provides drive current to ensure stable signal drive of the MUX input capacitor.

[0039] S4, Signal Selection Stage: Under the control of the control signal SEL2, the MUX multiplexer selects the CMOS signal output from the inverter chain and outputs it to the DAC core circuit.

[0040] The high sampling rate mode supports LVDS signal transmission of ≥500MSPS; the low sampling rate mode supports CMOS signal transmission of ≤125MSPS. In the low sampling rate mode, the digital logic circuit adjusts the bias current of the LVDS receiver to put the LVDS receiver into a power-down mode.

[0041] Furthermore, the switching operation between low sampling rate mode (or CMOS mode, the mode with CMOS signal input) and high sampling rate mode (or LVDS mode, the mode with LVDS differential signal input) satisfies the following timing constraints:

[0042] The wake-up time for switching from low sampling rate mode to high sampling rate mode is ≤100ns;

[0043] The shutdown delay when switching from high sampling rate mode to low sampling rate mode is ≤50ns.

[0044] Furthermore, the selection operation of the MUX multiplexer is strictly synchronized with the allocation operation of the DEMUX multiplexer, and digital logic circuitry ensures that the SEL1 and SEL2 signal states are consistent. When the system switches from high sampling rate mode to low sampling rate mode, the falling edge of the SEL2 signal precedes the falling edge of the LVDS_PD signal by at least 2ns, ensuring that the MUX multiplexer has switched to the inverter chain output path before the LVDS receiver is completely turned off, avoiding signal interruption. This timing design ensures that the data loss time during dual-mode switching is ≤500ps, meeting the dynamic response requirements of most high-speed DACs.

[0045] Furthermore, the inverter chain is a signal conditioning circuit composed of multiple inverters connected in series, each inverter containing both a PMOS transistor and an NMOS transistor; the parameter configuration of the inverter chain satisfies:

[0046] The input capacitor of the first-stage inverter is matched with the output impedance of the DEMUX multiplexer to suppress reflections and distortion during signal transmission;

[0047] The output drive capability of the final stage inverter is matched with the input load of the MUX multiplexer to ensure that the signal can stably drive the subsequent circuitry.

[0048] The aspect ratio of two adjacent inverters is designed according to a progressive amplification structure, so that the signal can achieve edge shaping and enhanced driving capability after passing through the inverter chain;

[0049] The overall transmission delay is coordinated with the delay of the LVDS receiver path to meet the timing consistency requirements of the digital-to-analog converter core circuit for dual-mode input signals.

[0050] The present invention adopts the above-described solution and has the following advantages:

[0051] 1. By integrating a reconfigurable signal processing path, it supports dynamic switching between LVDS high-speed differential signals and CMOS single-ended signals. It can be compatible with different types of data sources without additional level conversion circuits, breaking through the limitation of traditional single-mode interfaces that only support a single signal type. It significantly improves the adaptability of the DAC interface to multi-rate signals and simplifies the complexity of system-level signal adaptation.

[0052] 2. With the help of digital logic circuit control, the core module of the non-active signal path can be switched to a low power state, and the power consumption of redundant circuits can be reduced through mutual exclusion gating mechanism and progressive amplification design. The energy efficiency optimization in low speed mode is significant, making it suitable for portable devices with strict requirements for battery life.

[0053] 3. By precisely matching the transmission delay of different signal paths and optimizing the mode switching timing, the setup and hold times of the DAC input signal are ensured to meet the requirements of high-speed conversion, fundamentally avoiding timing mismatch problems caused by the difference in delay between LVDS and CMOS paths, and effectively improving the accuracy of digital-to-analog conversion.

[0054] The advantages of this invention compared to the prior art are:

[0055] (1) The digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input of the present invention, by integrating a reconfigurable signal processing path, supports dynamic switching input between LVDS high-speed differential signals and CMOS single-ended signals, and can be compatible with different types of data sources without additional level conversion circuits. Compared with other technologies, it breaks through the limitation of traditional single-mode interfaces that only support a single signal type, significantly improves the adaptability of the DAC interface to multi-rate signals, and simplifies the system-level signal adaptation complexity from the hardware level.

[0056] (2) The digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input of the present invention, with the help of digital logic circuit control, can switch the core module of the non-active signal path, such as the LVDS receiver, into a low-power state, and reduce the power consumption of redundant circuits through a mutual exclusion gating mechanism and progressive amplification design. Compared with the shortcomings of traditional dual-mode solutions where high-speed modules cannot be effectively shut down, the present invention has more significant energy efficiency optimization in low-speed mode, and is especially suitable for portable devices with strict requirements for battery life.

[0057] (3) The digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input of the present invention ensures that the setup time and hold time of the DAC input signal meet the high-speed conversion requirements by accurately matching the transmission delay of different signal paths and optimizing the mode switching timing. In view of the timing mismatch problem caused by the difference in delay between LVDS and CMOS paths in traditional design, the present invention fundamentally avoids the risk of signal distortion and effectively improves the digital-to-analog conversion accuracy through the collaborative design of circuit parameters.

[0058] Compared to traditional solutions, this invention breaks through the technical bottleneck of balancing performance, power consumption, and compatibility in dual-mode LVDS and CMOS input. The essential difference between this invention and existing technologies lies in its systematic breakthrough of the traditional dual-mode interface design paradigm. Through in-depth innovation in circuit architecture, module functions, and collaborative mechanisms, it achieves a balance between high performance and low power consumption. Existing technologies typically use independent links to process LVDS and CMOS signals, such as a single DEMUX paired with dual signal paths, resulting in high hardware redundancy and difficulty in dynamic switching. In contrast, this invention features a unique dual-DEMUX parallel + ESD dual-protection topology architecture. By using DEMUX1 / DEMUX2 to select either the LVDS receiver or the inverter chain in real time, hardware reuse is increased by over 50%. Simultaneously, the ESD protection topology integrates 100Ω differential matching (LVDS mode) and 50Ω single-ended matching (CMOS mode) in the INP branch, resolving the contradiction of "high-speed distortion and insufficient low-speed protection" in traditional single-protection circuits, and reducing chip area by 30% compared to traditional solutions.

[0059] In terms of module functionality, existing LVDS receivers mostly have a fixed common-mode range, largely limited to 1.2V±0.2V. Although this invention does not directly process CMOS signals, it expands the common-mode range through rail-to-rail preamplification, forming a "high-speed / low-speed dedicated channel" with the inverter chain, avoiding the delay loss of traditional "cascaded conversion". The inverter chain adopts a three-stage width-to-length ratio gradient configuration, with the input stage → intermediate stage → output stage increasing in a ratio of 1:2:4. This improves the driving capability by 4 times at low sampling rates, while reducing static power consumption by 30%, solving the problem of "high power consumption under light load and weak driving under heavy load" in traditional solutions.

[0060] In terms of control logic, existing dual-mode systems rely on software timing control or additional synchronization circuits. This invention achieves zero-blind-zone switching through a three-level hardware coordination mechanism: utilizing the characteristic that the ESD analog switch switching speed is faster than the DEMUX channel switching, a "protection first" hardware-level timing redundancy is formed; full-link coordination is achieved through only three signals: SEL1 (path selection), SEL2 (output selection), and LVDS_PD (power-down control), reducing the number of control signals by 50% and reducing logic complexity by 70% compared to traditional solutions.

[0061] In terms of collaborative operation, in low sampling rate mode, the LVDS receiver reduces power consumption by 90% through deep power-down of LVDS_PD, and the inverter chain activates the driving capability on demand, forming a dynamic power consumption model of "high-speed module sleep + low-speed module light load". In contrast, the traditional solution has a redundant power consumption of more than 40% due to the continuous operation of the module. The ESD module switching and DEMUX path switching are synchronized by hardware signal chain (SEL1 → analog switch → DEMUX) to ensure that the protection topology is reconstructed before the signal path during mode switching, eliminating the 5-10ns protection blind zone in the traditional solution.

[0062] These systemic innovations break through the technical barriers of existing technologies that cannot simultaneously achieve "performance, power consumption, and compatibility," enabling the present invention to achieve qualitative breakthroughs in key indicators such as chip area, power consumption control, and signal processing efficiency, providing a highly integrated and low-power solution for multi-mode signal processing.

[0063] This invention achieves close collaboration and performance breakthroughs through innovative design of inter-module connection methods and control logic: the dual DEMUX dynamic path allocation and ESD dual protection topology are synchronously switched at the hardware level through the SEL1 signal, forming a "protection first" link reconstruction mechanism; the digital logic circuit is controlled by the three signals SEL1 / SEL2 / LVDS_PD in a simplified manner, and the inherent delay difference between ESD and DEMUX is used to achieve timing coordination, breaking the asynchronous control bottleneck of traditional solutions, enabling each module to achieve zero blind zone coordination in dual-mode switching, and significantly improving integration and power efficiency.

[0064] This invention achieves technical effects unattainable by existing technologies through innovative designs such as dual-DEMUX dynamic path allocation, ESD dual-protection topology, and simplified three-signal control. In terms of data transmission rate, the LVDS receiver supports high-speed transmission with significantly reduced latency, while existing technologies, due to their single-link design, struggle to meet high-speed requirements. Regarding power consumption control, redundant power consumption is significantly reduced in low-sampling-rate mode, whereas traditional solutions suffer from high energy consumption due to continuous module operation. In terms of signal integrity and timing consistency, hardware-level timing difference enables "zero-blind-zone" switching, ensuring stable signal transmission, whereas existing technologies suffer from protection blind zones and poor signal quality. These differences stem from a systemic breakthrough at the architectural level, completely solving the industry problems of poor compatibility and power consumption performance imbalance in traditional dual-mode interfaces, demonstrating significant technological innovation. Attached Figure Description

[0065] The present invention can be better understood by referring to the description given below in conjunction with the accompanying drawings, in which the same or similar reference numerals are used throughout the drawings to denote the same or similar parts. These drawings, together with the following detailed description, are incorporated in and form part of this specification, and are used to further illustrate preferred embodiments of the invention and explain the principles and advantages of the invention. In the drawings:

[0066] Figure 1 This is a schematic block diagram of the digital-to-analog converter interface circuit of the present invention;

[0067] Figure 2 This is a schematic diagram of the working principle of the digital-to-analog converter interface circuit of the present invention;

[0068] Figure 3 This is a simulation diagram of the single-ended 125M CMOS signal input in the low sampling rate mode of the digital-to-analog converter interface circuit of the present invention;

[0069] Figure 4 This is a simulation diagram of a 500 MLVDS signal input in high sampling rate mode of the digital-to-analog converter interface circuit of the present invention;

[0070] Figure 5 This is a schematic block diagram of the ESD protection circuit in the digital-to-analog converter interface circuit of the present invention.

[0071] Figure 6 This is a block diagram of the LVDS receiver in the digital-to-analog converter interface circuit of the present invention. Detailed Implementation

[0072] Embodiments of the present invention will now be described with reference to the accompanying drawings. Elements and features described in one drawing or embodiment of the invention may be combined with elements and features shown in one or more other drawings or embodiments. It should be noted that, for clarity, representations and descriptions of components and processes unrelated to the present invention and known to those skilled in the art have been omitted from the drawings and description.

[0073] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0074] Existing technologies have failed to effectively achieve integrated compatibility design between LVDS and CMOS signals. The core challenge lies in the fundamental conflict in the electrical characteristics of the two signal types: differences in signal form and processing mechanisms. LVDS uses differential pairs to transmit low-swing signals, typically with a swing of 350mV, relying on a dedicated receiver for level conversion and requiring a 100Ω transmission line impedance to suppress signal reflection. In contrast, CMOS signals are single-ended with a full swing, requiring edge shaping and drive enhancement through an inverter chain. The input impedance, amplification mechanism, and noise margin requirements of the two are drastically different, making it difficult to reuse traditional circuit architectures. It is worth noting that some high-performance ADCs, such as Wolfson Microelectronics' WM8235 analog-to-digital converter, have achieved user-configurable LVDS / CMOS dual-mode output, but their output signals must be adapted to the input requirements of downstream DACs. If the DAC interface still uses a single-mode design, an additional level conversion circuit, such as a differential-to-single-ended converter, is required at the system level, increasing signal chain complexity, latency, and additional power consumption of 5-10mW, thus negating the flexibility advantages brought by dual-mode ADC output. The trade-off between power consumption and performance: LVDS receivers require high-bias-current analog circuitry for high-speed amplification, with typical operating currents of 10–15 mA, while the dynamic power consumption of the inverter chain in the CMOS path increases linearly with frequency. Traditional designs cannot effectively shut down high-speed circuits in low-speed mode, resulting in excessively high redundant power consumption, which is unacceptable for battery-powered devices. Furthermore, the difference in transmission delay between the two signal paths—such as nanoseconds for the LVDS path and hundreds of ps for the CMOS path—will, without control, cause timing mismatch in the DAC input signal, introducing conversion errors.

[0075] Even those few solutions attempting to achieve dual-mode input capability for DAC interfaces face the challenge of dramatically increased compatibility complexity: Synchronization issues in control logic: Signal mode switching requires precise coordination of multiplexers, distributors, and functional modules, such as the power-down control of LVDS receivers. Traditional state machine designs are prone to control signal glitches or timing misalignments, leading to transient short circuits in signal paths. For example, if LVDS and CMOS inputs are simultaneously turned on, it can cause latch-up or data errors. The impact of parasitic effects in layout design: High-speed LVDS paths require short-distance, low-parasitic-capacitance wiring, with parasitic capacitance controlled below 50fF. Meanwhile, the high input impedance nodes of CMOS paths are susceptible to electromagnetic coupling interference. Mixed layouts of these two types of signals can increase crosstalk noise by more than 20%, requiring additional isolation structures, such as grounding shields, further increasing design complexity.

[0076] In summary, existing technologies, limited by differences in signal characteristics, power consumption optimization bottlenecks, and the complexity of compatibility design, have not yet achieved a DAC interface circuit that can efficiently support LVDS / CMOS dual-mode input within a single chip while meeting the requirements of high speed, low power consumption, and timing consistency. Therefore, this application designs a novel interface architecture with switchable modes, self-isolated paths, and dynamic power consumption optimization to break through the application boundaries of traditional single-mode designs and meet current needs.

[0077] The design concept of this invention is as follows: This interface circuit integrates ESD protection circuitry, a DEMUX module, a MUX module, an LVDS receiver, an inverter chain, and digital logic circuitry. It achieves dual-mode input compatibility through dynamic signal path reconstruction: In high sampling rate mode, the LVDS differential signal, after ESD protection, is input to the LVDS receiver through the OUT2 port of the DEMUX, converted into a single-ended CMOS signal, and then output to the internal digital-to-analog converter via the MUX; in low sampling rate mode, the single-ended CMOS signal, after ESD protection, enters the inverter chain for shaping and amplification through the OUT1 port of the DEMUX, and is then output via the MUX. Simultaneously, digital logic controls the LVDS receiver to enter a power-down mode to reduce power consumption. This design overcomes the limitations of traditional single-mode interfaces, optimizes energy efficiency through modal power management, and is suitable for multi-rate mixed signal systems, providing an efficient solution for portable devices, high-speed sensor interfaces, and other scenarios.

[0078] For details, see Figure 1 and Figure 2 An embodiment of the present invention provides a digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input, comprising a first ESD protection circuit, a second ESD protection circuit, a first DEMUX multiplexer (DEMUX1), a second DEMUX multiplexer (DEMUX2), a MUX multiplexer (MUX), an LVDS receiver, a first inverter chain, a second inverter chain, and digital logic circuitry.

[0079] The first ESD protection circuit receives the input signal at its input terminal and connects to the first DEMUX multiplexer at its output terminal. The second ESD protection circuit receives the input signal at its input terminal and connects to the second DEMUX multiplexer at its output terminal. These first and second ESD protection circuits provide electrostatic discharge protection for the input signal. By clamping overvoltages and releasing overcurrents, they prevent electrostatic interference or surge voltages from damaging the subsequent DEMUX multiplexer and its internal circuitry, ensuring the reliability and stability of the interface circuitry.

[0080] Digital logic circuits are used to generate synchronization control signals based on external mode switching signals to coordinate the working states of each module. These synchronization control signals include: SEL1, which controls the input distribution of the first and second DEMUX multiplexers; the protection topology switching of the high-speed analog switch in the first ESD protection circuit; and the conduction state of the NMOS transistor M1 in the second ESD protection circuit; LVDS_PD, which controls the LVDS receiver to enter power-down mode; and SEL2, which controls the selection of the MUX multiplexer.

[0081] The first and second DEMUX multiplexers are used to distribute the input signals output by the first and second ESD protection circuits to their corresponding signal processing paths under the action of the digital logic circuit output control signal SEL1. The input terminals of the first and second DEMUX multiplexers are respectively connected to the output terminals of the first and second ESD protection circuits. The output terminals of both the first and second DEMUX multiplexers include:

[0082] First output branch OUT1: Connected to the input of the inverter chain, used to transmit single-ended CMOS signals;

[0083] The second output branch OUT2 is connected to the differential input of the LVDS receiver and is used to transmit differential LVDS signals.

[0084] In high sampling rate mode, DEMUX switches the input signal to the second output branch OUT2, enabling the LVDS signal path; in low sampling rate mode, DEMUX switches the input signal to the first output branch OUT1, enabling the CMOS signal path.

[0085] An LVDS receiver is used to receive LVDS signals, convert them into single-ended CMOS signals, and output them to a MUX multiplexer. The positive input of the LVDS receiver receives the INP signal, and the negative input receives the INN signal. In high sampling rate mode, the receiver receives the LVDS signal, converts it into a CMOS level signal, and outputs it to the first input of the MUX. In low sampling rate mode, the LVDS receiver enable signal LVDS_PD will put the receiver into a power-down state, at which point its output is in a high-impedance state to avoid interference with the CMOS signal path.

[0086] An inverter chain receives CMOS signals, with its inputs connected to a DEMUX and its outputs connected to a MUX multiplexer. It is used to buffer, shape, and enhance the drive of single-ended CMOS signals. In low sampling rate mode, the inverter chain receives single-ended CMOS signals at its inputs. After processing by N stages of inverters, it outputs a standard CMOS signal that meets the input requirements of the MUX multiplexer to its second input. The delay characteristics of this inverter chain are precisely designed to ensure matching with the total delay of the LVDS signal path in high sampling rate mode, thereby achieving timing consistency for dual-mode inputs.

[0087] The MUX multiplexer, under the control signal SEL2 from the digital logic circuit output, selects one input signal from two input signals to output to the DAC core circuit. The MUX input is connected to the LVDS receiver output and the inverter chain of the INP input branch. In high sampling rate mode, the LVDS output signal is selected for output to the DAC core circuit; in low sampling rate mode, the output signal from the inverter chain of the INP input branch is selected for output to the DAC core circuit.

[0088] The digital-to-analog converter interface circuit has two operating modes: LVDS mode (high sampling rate mode) and CMOS mode (low sampling rate mode). Figure 3 and Figure 4 The images show simulation diagrams of the digital-to-analog converter interface circuit under low sampling rate mode with a single-ended 125M CMOS signal input and under high sampling rate mode with a 500M LVDS signal input.

[0089] (1) High sampling rate mode:

[0090] When the external mode switching signal MODE is high, the interface circuit enters high sampling rate mode, which is suitable for LVDS differential signal input scenarios. The specific process is as follows:

[0091] S1, ESD Protection Stage: The LVDS differential signal first passes through the dedicated LVDS protection unit of the ESD protection circuit to ensure that overvoltage / overcurrent in the input signal is suppressed within a safe range.

[0092] S2, Signal Distribution Stage: The differential signal after ESD protection enters the DEMUX multiplexer. Under the control of the digital logic circuit output control signal SEL1, DEMUX directs the signal to the second output terminal OUT2, which is directly connected to the differential input terminal of the LVDS receiver.

[0093] S3, Signal Conversion Stage: The LVDS receiver is activated by the enable signal LVDS_PD, converting the differential signal into a single-ended CMOS signal.

[0094] S4, Signal Selection Stage: Under the control of the control signal SEL2, the MUX multiplexer selects the output signal of the LVDS receiver and transmits the signal to the DAC core circuit.

[0095] (2) Low sampling rate mode:

[0096] When the external mode switching signal MODE is low, the interface circuit switches to low sampling rate mode to adapt to single-ended CMOS signal input, which is connected through the INP interface. The specific process is as follows:

[0097] S1, ESD Protection Stage: The CMOS single-ended signal first passes through the dedicated CMOS protection unit of the ESD protection circuit, which can suppress high-frequency noise and clamp the input voltage within a safe range.

[0098] S2, Signal Distribution Stage: Under the control of the control signal SEL1, the DEMUX multiplexer directs the ESD output signal to the first output terminal OUT1, which is connected to the inverter chain. Simultaneously, the digital logic circuit cuts off the self-bias current of the LVDS receiver via the LVDS_PD signal, causing it to enter a deep power-down state, thus reducing system power consumption.

[0099] S3. Signal Conditioning Stage: The CMOS signal enters the inverter chain, which shapes and enhances the CMOS signal: the first-stage inverter matches the DEMUX output impedance to reduce signal reflection; the intermediate-stage inverter optimizes the rise / fall time to eliminate edge jitter; the final-stage inverter provides drive current to ensure stable signal drive of the MUX input capacitor.

[0100] S4, Signal Selection Stage: Under the control of the control signal SEL2, the MUX multiplexer selects the CMOS signal output from the inverter chain and outputs it to the DAC core circuit.

[0101] Of the two modes mentioned above, the high sampling rate mode supports LVDS signal transmission of ≥500MSPS. The low sampling rate mode supports CMOS signal transmission of ≤125MSPS.

[0102] The selection operation of the MUX is strictly synchronized with the allocation operations of DEMUX1 and DEMUX2, and digital logic circuits ensure that the signal states of SEL1 and SEL2 are consistent. When the system switches from high sampling rate mode to low sampling rate mode, the falling edge of the SEL2 signal precedes the falling edge of the LVDS_PD signal by at least 2ns, ensuring that the MUX has switched to the inverter chain output path before the LVDS receiver is completely turned off, avoiding signal interruption. The falling edge of the SEL2 signal precedes the falling edge of the LVDS_PD signal by at least 2ns, making the protection switching precede the signal path switching, thereby ensuring that the states of all circuits are completely synchronized when switching between high and low sampling rate modes, avoiding signal glitches and path conflicts. This timing design ensures that the data loss time during dual-mode switching is ≤500ps, meeting the dynamic response requirements of most high-speed DACs.

[0103] An inverter chain is a signal conditioning circuit consisting of multiple inverters (INV) connected in series. Each inverter stage includes both PMOS and NMOS transistors. The parameters of the inverter chain are configured to satisfy the following:

[0104] The input capacitor of the first-stage inverter is matched with the output impedance of the DEMUX multiplexer to suppress reflections and distortions during signal transmission. The output drive capability of the last-stage inverter is matched with the input load of the MUX multiplexer to ensure that the signal can stably drive subsequent circuits. The aspect ratio of adjacent inverters is designed according to a progressive amplification structure, so that the signal achieves edge shaping and enhanced drive capability after passing through the inverter chain. At the same time, a graded aspect ratio optimization design is adopted to provide only the minimum power consumption required for CMOS signal transmission. The overall transmission delay is coordinated with the delay of the LVDS receiver path to meet the timing consistency requirements of the digital-to-analog converter core circuit for dual-mode input signals.

[0105] The mode switching operation from CMOS mode to LVDS mode must satisfy the following timing constraints:

[0106] Wake-up time when switching from CMOS mode to LVDS mode ≤100ns

[0107] The shutdown delay when switching from LVDS mode to CMOS mode is ≤50ns.

[0108] In low sampling rate mode, the digital logic circuit adjusts the bias current of the LVDS receiver to put the LVDS receiver into power-down mode.

[0109] This invention addresses the problems of difficult reuse, power consumption and performance imbalance, and increased compatibility complexity in traditional dual-mode interface architectures. It achieves a precise breakthrough through dynamic allocation of dual-channel DEMUX, inverter chain adaptation, and intelligent digital logic management.

[0110] 1. Dual DEMUX dynamic path reconstruction (solving the architecture reuse problem)

[0111] Traditional solutions require separate signal links for LVDS / CMOS, resulting in high hardware redundancy. This invention utilizes a dual-channel distribution module (DEMUX1 / DEMUX2) that, along with the high-speed analog switch of the first ESD protection circuit and the MOSFET M1 of the second ESD protection circuit, is synchronously controlled by the SEL1 signal. This directs the protected input signal to either the LVDS receiver (high sampling rate) or the inverter chain (low sampling rate) according to the mode requirements. This design reuses core hardware, avoids redundant circuit construction, and solves the problem of traditional single-mode / redundant dual-mode architectures being unable to flexibly adapt to multiple signal types.

[0112] 2. LVDS receiver power loss and inverter chain reshaping (balancing power consumption and performance)

[0113] In traditional dual-mode designs, high-speed LVDS modules operate continuously in low-speed mode, resulting in redundant power consumption. This invention addresses this by using the LVDS_PD signal to cut off the self-bias current of the LVDS receiver in low sampling rate mode, achieving deep power-down. Simultaneously, the inverter chain employs a tiered aspect ratio optimization design, providing only the minimum power consumption required for CMOS signal transmission. This significantly reduces redundant power consumption while ensuring signal integrity, resolving the performance-power tradeoff of "high-speed modules dragging down low-speed energy efficiency."

[0114] 3. Global coordination of digital logic (simplifies compatibility complexity)

[0115] Traditional solutions are prone to signal conflicts and timing disorders during mode switching due to asynchronous control signals. This invention uses digital logic circuits to uniformly manage the SEL1 / SEL2 path selection and LVDS_PD power-down enable, and utilizes the inherent delay difference between the analog switch in the first ESD protection circuit and the DEMUX (protection switching precedes signal path switching) to ensure that DEMUX path allocation, MUX output selection, and receiver power consumption are completely synchronized during high / low sampling rate mode switching, avoiding signal glitches and path conflicts, and solving the design problem of "a change in one part affects the whole" in control logic under multi-mode compatibility.

[0116] As an application example, the collaborative process for switching from high sampling rate mode to low sampling rate mode in this application is as follows:

[0117] Triggering condition: The digital logic circuit detects that the MOD signal jumps to a low level, starts the mode switching process, synchronously pulls the LVDS_PD enable signal low, and updates the SEL1 / SEL2 strobe logic.

[0118] ESD Protection Circuit: Upon receiving the SEL1 mode switching signal, the high-speed switch in the INP branch ESD protection circuit disconnects the LVDS protection branch and closes the CMOS protection branch, completing the protection topology switch. Simultaneously, the NMOS transistor (M1) in the INN branch turns on, grounding the original LVDS protection circuit and eliminating floating interference. Thanks to the high-speed analog switch's faster switching speed than the DEMUX channel, the ESD module utilizes the timing difference to form a "protection-first" mechanism, ensuring effective signal protection throughout the entire process and continuously filtering anomalies until the low sampling rate mode stabilizes.

[0119] DEMUX Multiplexer (DEMUX1 / DEMUX2): Receives the SEL1 switching command from the digital logic circuit, switches the signal channel from OUT2 to OUT1, disconnects from the LVDS receiver, and outputs the ESD-protected single-ended CMOS signal to the inverter chain.

[0120] Inverter chain: Initially, the mode switch maintains a high impedance state. After the DEMUX outputs a single-ended CMOS signal, it is shaped and amplified by multiple inverters.

[0121] LVDS receiver: In response to the LVDS_PD power-down signal, it enters power-down mode, cutting off the internal self-bias current and reducing power consumption. The digital logic first sends a power-down command, then switches the DEMUX channel to prevent accidental signal triggering during switching, thus balancing low power consumption and stability.

[0122] MUX multiplexer: After the digital logic circuit completes path reconstruction and signal verification, it receives the SEL2 strobe command, connects the in2 port to the output of the inverter chain, and transmits the processed signal to the internal digital-to-analog converter.

[0123] Digital logic circuit: After detecting that the MOD signal has switched to a low level, the following steps are executed sequentially: pull down the LVDS_PD enable signal to turn off the LVDS receiver; send the SEL1 instruction to switch the signal path; verify whether the path switching is complete by receiving status feedback signals from circuits such as DEMUX and ESD; configure the SEL2 gate inverter chain output. Through strict instruction sequence and inter-module feedback coordination, combined with the timing difference between the ESD protection circuit and the DEMUX multiplexer, a "zero-blind-zone" switching without signal interruption is achieved, ensuring efficient and low-power operation in low sampling rate mode.

[0124] The collaborative process for switching from low sampling rate mode to high sampling rate mode is as follows:

[0125] Triggering condition: When the digital logic circuit detects that the MOD signal jumps to a high level, it immediately starts the mode switching process, synchronously pulls the LVDS_PD enable signal high, and updates the SEL1 / SEL2 strobe logic.

[0126] ESD Protection Circuit: Upon receiving the SEL1 mode switching signal, the high-speed switch in the INP branch ESD protection circuit quickly disconnects the CMOS protection branch and closes the LVDS protection branch, completing the protection topology switch. Simultaneously, the NMOS transistor (M1) in the INN branch is turned off, restoring the LVDS protection circuit to normal operation. The ESD module, leveraging the faster response speed of its high-speed analog switch compared to the DEMUX channel switching, utilizes the timing difference to achieve "protection first," ensuring that the signal is protected against electrostatic discharge, overcurrent, and other abnormalities throughout the switching process, until stable operation in high sampling rate mode.

[0127] DEMUX Multiplexer (DEMUX1 / DEMUX2): Receives the SEL1 switching command sent by the digital logic circuit, switches the signal channel from OUT1 to OUT2, disconnects from the inverter chain, and accurately outputs the ESD-protected LVDS differential signal to the LVDS receiver.

[0128] Inverter chain: After the mode switching command is issued, it immediately responds to the control signal of the digital logic circuit and enters high-impedance mode, cutting off its own output from the MUX path. This avoids interference with the LVDS signal, reduces its own power consumption, and ensures that high-speed signal transmission is not affected.

[0129] LVDS Receiver: The digital logic circuit receives the feedback signal from the DEMUX to confirm that the SEL1 switching is complete, and then sends a high-level LVDS_PD enable signal. After the LVDS receiver is activated, it quickly converts the input LVDS differential signal into a single-ended CMOS signal and outputs it to the corresponding int2 port of the MUX.

[0130] MUX multiplexer: After the digital logic circuit completes path reconstruction and sends the SEL2 strobe command, the receiving command switches to connect with the output terminal (int2 port) of the LVDS receiver, and transmits the converted single-ended CMOS signal to the internal digital-to-analog converter.

[0131] Digital logic circuit: After detecting the MOD signal transitioning to a high level, the switching is executed according to a strict timing sequence: First, the SEL1 instruction is sent to switch the DEMUX signal path; after receiving feedback confirmation from DEMUX that the switching is complete, the LVDS_PD enable signal is pulled high to activate the LVDS receiver; finally, the SEL2 strobe instruction is sent, and the LVDS receiver lockout status is continuously monitored. By precisely controlling the action sequence of each module and the feedback verification mechanism, the switching process from low sampling rate to high sampling rate is ensured to be stable and reliable, avoiding signal interruption and data loss.

[0132] As a preferred embodiment, this application also optimizes the ESD protection circuit design to achieve precise signal protection in different modes. See [link to relevant documentation] Figure 5This ESD protection circuit, through a triple design of "dual-branch isolation + high-speed analog switch + modemed grounding", achieves zero-blind-zone and zero-compromise electrostatic protection for LVDS / CMOS dual-mode signals for the first time, providing a highly reliable and low-latency guarantee for subsequent signal path switching.

[0133] Specifically, the first ESD protection circuit (corresponding to the positive terminal of INP, denoted as the INP branch) includes a high-speed analog switch, an LVDS-ESD protection circuit, and a CMOS-ESD protection circuit. The common terminal of the high-speed analog switch is connected to the positive terminal of INP and the SEL1 signal. The S1 terminal of the high-speed analog switch is connected to the LVDS-ESD protection circuit, and the S2 terminal of the high-speed analog switch is connected to the CMOS-ESD protection circuit. When SEL1 = 1: the high-speed analog switch switches the INP branch to the S1 terminal, forming LVDS differential protection. When SEL1 = 0: the high-speed analog switch switches the INP branch to the S2 terminal, forming CMOS single-ended protection.

[0134] The LVDS-ESD protection circuit is applied in LVDS mode and may include a TVS diode and a 100Ω differential matching network to suppress common-mode overvoltage, match differential impedance, and ensure high-speed signal integrity. The CMOS-ESD protection circuit is applied in CMOS mode and may include a Zener diode, a series resistor, and a 50Ω single-ended matching network to clamp single-ended overvoltage, match single-ended impedance, and reduce reflection. In this embodiment, the high-speed analog switch is implemented using an ADG719 single-pole double-throw analog switch.

[0135] The second ESD protection circuit (corresponding to the negative terminal of INN, referred to as the INN branch) includes an LVDS-ESD protection circuit and an NMOS transistor. The gate of the NMOS transistor is connected to the SEL1 signal, the drain of the NMOS transistor is connected to the output terminal of the LVDS-ESD protection circuit, and the source of the NMOS transistor is grounded.

[0136] The ESD protection circuit is described in detail below:

[0137] 1. Architecture Design: Dual-path physically isolated protective branches

[0138] To address the characteristic differences between LVDS differential signals and CMOS single-ended signals, independent protection branches (LVDS-ESD protection branch and CMOS-ESD protection branch) are designed. Physical isolation is achieved through a high-speed analog single-pole double-throw switch ADG719. The ADG719 switch is directly controlled by SEL1, the gate terminal of M1 is connected to the SEL1 signal, and the INP branch is connected in parallel with a TVS diode to ground.

[0139] For the INP branch:

[0140] LVDS mode (SEL1=1): ADG719 is switched to S1 and connected to the LVDS-ESD protection branch (including symmetrical TVS clamping circuit and 100Ω differential impedance matching network) to accurately suppress common-mode overvoltage of LVDS differential signal, while matching 100Ω differential impedance to compensate for signal attenuation and ensure high-speed signal integrity.

[0141] CMOS Mode (SEL1=0): ADG719 is switched to S2 and connected to the CMOS-ESD protection branch (including series resistor + Zener diode clamping, 50Ω single-ended impedance matching network) to accurately suppress overvoltage and reverse current of single-ended signals, while matching the 50Ω single-ended impedance to ensure signal rise / falling edge integrity.

[0142] For the INN branch:

[0143] In LVDS mode (SEL1=1), the NMOS transistor is turned off, and the INN normally transmits the negative terminal signal of LVDS. The signal passes through the LVDS-ESD protection branch.

[0144] CMOS mode (SEL1=0): The SEL1 signal turns on the M1 transistor, and the INN branch is grounded, eliminating noise and redundant power consumption caused by floating input.

[0145] 2. Dynamic switching: Deep coordination with mode control signals

[0146] The analog switch switching logic of the ESD protection circuit is synchronized at the hardware level with the SEL1 control signal of the digital logic circuit, and timing self-consistency is achieved through the inherent characteristics of existing components: the analog switch (ADG719) achieves a switching time of ≤3.5ns based on the MOSFET gate charging and discharging speed, while the DEMUX (such as 74HC157) has a channel switching delay of ≥10ns due to the internal logic gate cascading delay; when the two share the SEL1 control signal, the analog switch will inevitably complete the switching before the DEMUX, naturally forming a safety mechanism of "protection branch switches first, signal path conducts later", without the need for additional timing control circuits, effectively reducing cost and complexity.

[0147] During analog switchover, parallel TVS diodes can temporarily absorb ringing energy. Combined with the timing redundancy formed by the component characteristics, this ensures that there are no blind spots in protection during mode switching.

[0148] 3. Technical problems solved and innovative value

[0149] This design precisely solves the four major problems of traditional ESD protection schemes under different modes and input signals:

[0150] Compatibility challenges: By using dual-path physical isolation, protection compromises caused by differences in LVDS / CMOS signal characteristics are avoided (such as the impact of single-ended protection on the common-mode balance of differential signals in traditional solutions).

[0151] Mode switching risk: The protection blind spot during mode switching is eliminated by synchronous control of high-speed analog switch and SEL1 signal;

[0152] Signal integrity loss: Through the synergy of impedance matching networks and protection circuits, the transmission accuracy of signals in different modes is ensured;

[0153] Floating noise problem: By using a modular grounding design for the INN terminal, the noise and power consumption problems caused by the floating INN terminal in CMOS mode are solved.

[0154] The ESD protection circuit of this invention achieves precise protection under LVDS / CMOS dual-mode input through architectural isolation, high-speed switching, impedance coordination, timing optimization, and patterned grounding. In particular, by utilizing the inherent delay difference between analog switches and DEMUX, no additional circuitry is needed to ensure that protection switching precedes signal path switching; and through the NMOS grounding design at the INN terminal, floating noise and redundant power consumption are intelligently eliminated. These innovations collectively improve system reliability and compatibility, providing a highly reliable protection solution for dual-mode digital-to-analog converter interface circuits.

[0155] This invention achieves precise signal guidance and interference-resistant switching through a three-level architecture of "ESD protection front-end + DEMUX channel synchronous gating + timing collaborative isolation," solving the core problem of signal switching being susceptible to interference in existing technologies, as detailed below:

[0156] 1. Collaborative Architecture Design: Three-Level Protection and Selective Linkage

[0157] ESD protection and DEMUX share the SEL1 control signal to ensure that ESD protection branch switching and DEMUX channel selection are triggered synchronously; at the same time, the inherent delay difference between analog switch ADG719 and DEMUX is used to form timing redundancy (protection switching precedes channel selection) to avoid switching blind spots.

[0158] 2. Precise guidance mechanism: Dual-channel physical isolation

[0159] DEMUX uses physically isolated dual channels to guide signals based on the SEL1 state:

[0160] LVDS mode (SEL1=1): DEMUX directs the ESD-protected differential signal to the LVDS receiver channel while disconnecting the CMOS processing branch to avoid signal crosstalk;

[0161] CMOS mode (SEL1=0): DEMUX directs the single-ended signal after ESD protection to the inverter chain channel, and at the same time grounds the INN terminal through the NMOS transistor to eliminate floating noise and disconnect the LVDS processing branch.

[0162] 3. Anti-interference innovation: A triple mechanism to solve traditional pain points

[0163] This design solves the interference problem of signal switching in traditional technologies through a triple collaborative mechanism:

[0164] ESD pre-filtering: Before the signal enters the DEMUX, it first passes through the ESD protection circuit to suppress surges / overvoltages and prevent the DEMUX from being damaged or falsely triggered by abnormal signals;

[0165] Timing-based collaborative isolation: By utilizing the delay difference between the analog switch and DEMUX, it is ensured that the DEMUX channel is only turned on after the ESD protection branch has been switched, thus avoiding signal reflection and crosstalk at the moment of switching;

[0166] Dynamic grounding noise reduction: In CMOS mode, the INN terminal is grounded through an NMOS transistor to eliminate noise generated by floating input and improve signal purity.

[0167] The DEMUX multiplexer of this invention achieves precise signal guidance and anti-interference switching through synchronous control with the ESD protection circuit (SEL1), timing coordination (due to inherent differences in devices, the protection branch will complete switching before the DEMUX channel), and dynamic grounding innovation (M1). Its core advantages are:

[0168] 1. Hardware-level linkage ensures consistency between protection and selection; 2. Timing redundancy avoids switching blind spots; 3. Dynamic grounding eliminates floating noise.

[0169] These mechanisms collectively enhance the stability and reliability of dual-mode signal switching, providing an efficient solution for dual-mode digital-to-analog converter interfaces.

[0170] As a preferred embodiment, see Figure 6 This invention also improves the LVDS receiver by employing a four-stage architecture consisting of a self-bias generation circuit (self-bias circuit), a rail-to-rail preamplifier circuit (rail-to-rail folded cascode preamplifier), a hysteresis comparator circuit (hysteresis comparator), a differential amplifier circuit (differential amplifier), and an output buffer stage circuit (output buffer). Through targeted configuration and optimization of each module, a performance leap is achieved compared to existing technologies, as detailed below:

[0171] The first-stage self-bias generation circuit, unlike existing technologies that rely on external bias circuits, generates the required current source and bias internally, reducing errors that may be introduced during transmission from external circuits and improving circuit stability. Simultaneously, in low sampling rate mode, the bias current can be pulled close to zero via the LVDS_PD signal, achieving efficient power-down. Compared to traditional LVDS receivers that still have some residual current in power-down mode, this significantly reduces standby power consumption.

[0172] The second-stage rail-to-rail preamplifier circuit consists of a folded cascode operational amplifier composed of differential-to-rail input differential pairs. In existing technologies, many preamplifier circuits have a narrow common-mode input range and poor adaptability to signals with different common-mode levels. However, the rail-to-rail input differential pairs in this design significantly widen the common-mode input range, ensuring stable reception of LVDS signals with various common-mode levels. Furthermore, the folded cascode output circuit, while ensuring sufficient gain, possesses a wide input signal bandwidth, meeting the requirements of high-speed signal transmission and solving the problem of balancing gain and bandwidth in some existing circuits.

[0173] The third-stage hysteresis comparator circuit consists of a differential input pair, a diode load, and a negative resistor. Some existing comparators are susceptible to hysteresis characteristics affected by manufacturing processes, temperature, and common-mode voltage. When the input signal approaches the threshold, noise can easily cause output oscillations and false state flips. However, the hysteresis comparator designed in this invention is unaffected by these factors, effectively eliminating output oscillations caused by unstable input signals and improving the accuracy of signal conversion.

[0174] The fourth-stage differential amplifier circuit works in conjunction with the output buffer stage. The differential amplifier circuit consists of a differential input pair and a current mirror load. Unlike some existing amplifier circuits that lack sufficient common-mode signal suppression, this circuit amplifies only the differential signal and has a strong common-mode signal suppression effect, enhancing anti-interference capability. The subsequent inverter buffer ensures the signal driving capability, achieving stable conversion from LVDS to CMOS signals.

[0175] This four-level architecture, through the special configuration and optimization of each module, enables the LVDS receiver to efficiently process high-speed signals in high sampling rate mode and achieve low power consumption in low sampling rate mode. At the same time, it takes into account performance such as wide common-mode input, high gain, and noise interference resistance. Compared with existing technologies, it has significant differences in adaptability, stability and power consumption control, ensuring that the interface circuit can operate stably and efficiently in different modes.

[0176] As a preferred embodiment, this invention also optimizes the inverter chain design. To address the buffering, shaping, and drive enhancement requirements of CMOS signals in low sampling rate mode, a multi-stage cascaded optimization design is adopted. Through gradient configuration of aspect ratios, step-by-step matching of drive capabilities, and load adaptability adjustment, the stability and reliability of the signal at low rates are ensured. Specifically, the buffering function is achieved through a three-stage cascade of inverters. Each stage acts as a buffer unit to isolate the preceding and following stages, reducing the direct impact of the load of the following stage on the preceding stage circuit (DEMUX1 output). Specifically, the input stage INV1 has a PMOS aspect ratio of 2 / 1 and an NMOS aspect ratio of 1 / 1, reducing the load pull on the preceding stage with a smaller size; the intermediate stage INV2 has a PMOS aspect ratio of 4 / 1 and an NMOS aspect ratio of 2 / 1, achieving signal transition and initial drive enhancement; the output stage INV3 has a PMOS aspect ratio of 8 / 1 and an NMOS aspect ratio of 4 / 1, increasing the load capacity with a larger size.

[0177] In terms of shaping, to address the issue of gradual edge changes or small oscillations that easily occur after CMOS signal transmission in low sampling rate mode, the inverter chain achieves shaping through width-to-length ratio matching and threshold coordination: the width-to-length ratio of the PMOS and NMOS in each stage inverter is maintained at 2:1 to ensure symmetry between rise time and fall time and avoid signal duty cycle distortion; the intermediate stage INV2 increases the gate capacitance by increasing the width-to-length ratio to 4 / 1 and 2 / 1, which filters the high-frequency oscillation of the input signal and reduces signal edge jitter.

[0178] In terms of drive enhancement, for scenarios involving long-line transmission or multiple loads in parallel at low sampling rates, the inverter chain is enhanced through a gradient design of drive capability: the width-to-length ratio of each inverter stage is twice that of the previous stage, significantly improving the total drive capability and ensuring that the rise / fall time of the output signal can still meet the timing requirements of low sampling rates when driving capacitive loads; the width-to-length ratio design of the output stage INV3 makes the output resistor match the characteristic impedance of the PCB transmission line, greatly reducing reflection noise.

[0179] Unlike traditional inverter chains that often use a fixed width-to-length ratio (e.g., each stage is 4 / 2), which leads to problems such as "excessive power consumption under light load and insufficient drive under heavy load", this design reduces static power consumption at low sampling rates through graded width-to-length ratio optimization. Furthermore, it balances load capacity and signal integrity by using a 2x progressively increasing drive ratio gradient control, thus resolving the contradictions of traditional designs.

[0180] In summary, the inverter chain, through hierarchical configuration of width-to-length ratio, gradient matching of driving capability, and symmetrical edge design, achieves efficient buffering, precise shaping, and stable driving of CMOS signals in low sampling rate mode, ensuring reliable operation of interface circuits in low-speed scenarios.

[0181] Compared with existing technologies, this application achieves significant improvements and breakthroughs in ESD protection circuits. Existing technologies mostly adopt single-path protection, which is difficult to adapt to both LVDS differential signals and CMOS single-ended signals simultaneously, and the protection switching and signal path switching lack coordination, resulting in protection blind spots.

[0182] This application designs a dual-path isolated protection topology, achieving dynamic switching between the LVDS and CMOS protection branches via a high-speed analog switch. Simultaneously, it synchronizes the ESD module and DEMUX control signals at the hardware level, utilizing the inherent delay differences of the components to ensure that protection switching precedes signal path switching, completely eliminating switching blind spots. Furthermore, the innovative INN-terminal modemed grounding design eliminates floating noise in CMOS mode using an NMOS transistor, further optimizing signal quality.

[0183] These improvements enable ESD protection circuits to automatically adapt to different signal types, achieving precise protection in both high-speed and low-speed transmission scenarios. They overcome the limitations of poor compatibility and discontinuous protection in traditional ESD circuits, achieving functional and performance enhancements that existing technologies cannot achieve.

[0184] The LVDS receiver of this invention achieves high-efficiency transmission with low latency and low distortion through a four-stage architecture optimized for high-speed signal transmission. The self-bias generation circuit employs an internal closed-loop bias system, avoiding noise and delay introduced by external bias, providing a stable reference for high-speed transmission, and reducing power supply ripple interference. The rail-to-rail preamplifier circuit utilizes a dual differential pair input stage and a folded cascode output structure to widen the effective signal bandwidth while improving open-loop gain and unity-gain bandwidth, ensuring that high-speed signals can be transmitted with extremely short rise / fall times and maintaining good eye diagram quality.

[0185] In the hysteresis comparator circuit, negative resistance-enhanced hysteresis technology keeps the hysteresis stable, effectively suppressing the risk of metastability during high-speed switching; the optimized fast latching mechanism of internal node capacitors significantly shortens the decision time, meeting high-speed timing requirements. Differential amplification and output buffer stages further enhance signal quality; the high common-mode rejection ratio differential-to-single-ended design effectively suppresses common-mode noise, and the adaptive bias technology of the output buffer stage dynamically matches the output impedance according to the load, reducing signal reflection.

[0186] Compared to traditional LVDS receivers, this design achieves breakthroughs in bandwidth, timing, and distortion control in high-speed scenarios, overcoming problems such as insufficient bandwidth, high latency, and significant distortion in traditional solutions. It ensures that the signal transmission maintains excellent performance with low latency and low distortion at all times, significantly improving the stability and reliability of signal transmission.

[0187] In low-speed signal transmission modes, the inverter chain is specifically designed to ensure the integrity and stability of CMOS signals. Traditional inverter chains often use a fixed aspect ratio, which leads to excessive power consumption under light loads and insufficient drive under heavy loads, making them unsuitable for low-speed scenarios. The inverter chain of this invention employs a multi-stage cascaded optimization design, achieving efficient buffering, precise shaping, and stable drive through gradient aspect ratio configuration, progressive matching of drive capability, and load adaptability adjustment.

[0188] The input stage employs a smaller aspect ratio to reduce load pull on the preceding stages; the intermediate stages provide signal transition and initial drive enhancement; and the output stage uses a larger size to increase load capacity. The PMOS and NMOS aspect ratios of each inverter stage are maintained in a specific ratio to ensure symmetrical signal rise and fall times, avoiding duty cycle distortion. Simultaneously, the intermediate stages filter and shape high-frequency oscillations by increasing the gate capacitance. Furthermore, the gradient-increasing drive capability design matches the output resistance to the transmission line characteristic impedance, significantly reducing reflection noise and thus maintaining the integrity and stability of the CMOS signal during low-speed transmission.

[0189] In terms of seamless switching between high-speed and low-speed signals, existing technologies often involve independently controlled ESD protection circuits and signal processing modules, which can easily lead to protection blind spots and signal reflections during mode switching, resulting in signal interruption and data loss. This invention achieves a breakthrough through deep multi-module collaboration: the ESD protection circuit adopts a dual-path isolated protection topology, dynamically switching between LVDS and CMOS protection branches via a high-speed analog switch, and is synchronized at the hardware level with the control signal of the DEMUX. Utilizing the inherent delay differences of components, it ensures that protection switching precedes signal path switching, eliminating switching blind spots. The LVDS receiver achieves efficient power-down in low sampling rate mode through a self-biasing generation circuit, reducing power consumption and interference. The inverter chain responds quickly in low sampling rate mode, buffering, shaping, and enhancing the CMOS signal. All modules operate around a unified control signal, achieving timing coordination and adaptive parameter adjustment during the switching process. Compared to existing technologies, this significantly improves the reliability of the interface circuit during high-speed and low-speed switching, avoiding signal interruption and data loss.

[0190] This invention achieves precise power consumption control in different modes through a multi-module collaborative dynamic power consumption optimization mechanism, exhibiting significant advantages, especially in low sampling rate scenarios. The digital logic circuit, through deep collaboration between the LVDS_PD signal and the self-bias generation circuit of the LVDS receiver, precisely triggers a power-down mechanism in low sampling rate mode. Unlike existing technologies that rely on external bias circuits resulting in residual power consumption, this design uses an internal closed-loop bias system to reduce the bias current of the LVDS receiver to an extremely low level, almost completely cutting off unnecessary power consumption sources and avoiding the static current loss problem in traditional solutions from the source.

[0191] When switching between high-speed and low-speed modes, the dual-path isolation topology of the ESD protection circuit and the timing coordination of DEMUX further enhance power consumption optimization: In high-speed mode, the rail-to-rail preamplifier and differential processing circuit of the LVDS receiver are activated as needed, ensuring high-performance transmission while avoiding redundant power consumption; In low-speed mode, in addition to the deep power-down of the LVDS receiver, the inverter chain dynamically adjusts the drive capability through a graded width-to-length ratio design, providing only the minimum power consumption required for CMOS signal transmission, avoiding the power waste caused by "large drive capability matching small load" in the traditional fixed width-to-length ratio design.

[0192] Compared to the power management methods of independent modules in existing technologies, this invention achieves dynamic power adaptation across the entire link from ESD protection and signal reception to buffer driving through a unified digital logic control signal. It not only significantly reduces overall power consumption in low sampling rate mode, but also avoids instantaneous power surges during mode switching through timing coordination. This "on-demand supply and precise control" power management strategy is of key significance for power-sensitive scenarios such as battery-powered portable devices. While ensuring the performance of high and low speed signal transmission, it significantly extends the device's battery life, breaking through the technical bottleneck of "difficulty in balancing performance and power consumption" in traditional solutions.

[0193] In traditional technology systems, LVDS and CMOS signals have long faced the challenge of incompatibility within a single chip due to significant differences in level standards and transmission characteristics. Existing solutions typically employ separate hardware links to process LVDS and CMOS signals, leading to chip area redundancy, high power consumption, and difficulty in meeting the timing consistency requirements of high-speed transmission. For example, traditional LVDS receivers experience signal distortion due to common-mode range mismatch when processing CMOS signals, while a single CMOS interface circuit cannot adapt to the low-swing, differential transmission characteristics of high-speed LVDS signals. Furthermore, in high-speed / low-speed mode switching scenarios, traditional designs, lacking coordinated control mechanisms, are prone to issues such as protection blind spots, signal interruptions, or wasted power.

[0194] This invention systematically overcomes the aforementioned industry challenges through a multi-module collaborative innovation architecture:

[0195] In terms of dual-mode input compatibility, a dual-channel DEMUX dynamic allocation module is designed, which combines ESD dual protection topology with the rail-to-rail preamplification technology of LVDS receiver to achieve adaptive switching and precise processing of LVDS differential signal and CMOS single-ended signal.

[0196] In terms of high speed and low power consumption, the LVDS receiver adopts a self-biased closed-loop system and a negative resistance enhanced hysteresis comparator to maintain low latency and low distortion transmission at high speeds above 500MSPS. At the same time, in low sampling rate mode, it significantly reduces redundant power consumption by deep power-down of the LVDS_PD signal and combined with the hierarchical width-to-length ratio optimization design of the inverter chain.

[0197] At the level of ensuring timing consistency, the digital logic circuit, as the global control core, achieves a "zero blind zone" transition between high / low speed modes by synchronizing signals such as SEL1 / SEL2 path selection and LVDS_PD power consumption control at the hardware level, combined with the timing difference design of the ESD module and DEMUX, thus ensuring signal integrity and system stability.

[0198] Compared to traditional solutions, this invention breaks through the technical bottleneck of LVDS and CMOS dual-mode input, which makes it difficult to balance performance, power consumption and compatibility. It provides a high-performance, highly integrated signal processing solution for portable devices, communication interfaces and other fields, and has significant industry innovation and application value.

[0199] This invention achieves flexible adaptation of the DAC interface circuit to different data sources through three core innovations: dual-path dynamic allocation topology, adaptive protection architecture, and intelligent collaborative control logic. It completely eliminates the level conversion stage in traditional solutions, significantly simplifying system design. The specific principles and breakthrough design are as follows:

[0200] 1. Dual-path DEMUX dynamic path allocation architecture

[0201] Traditional solutions require separate input links for LVDS and CMOS signals and rely on level conversion circuits (such as LVDS to TTL chips) to achieve format unification, leading to hardware redundancy and increased costs. This invention employs a dual-path parallel structure (DEMUX1 / DEMUX2), dynamically selecting the path through the SEL1 signal output from the digital logic circuit: in high sampling rate mode, DEMUX directly guides the ESD-protected LVDS differential signal to the LVDS receiver; in low sampling rate mode, it switches to an inverter chain to process the single-ended CMOS signal. This design eliminates the need for additional level conversion, improving the core circuit utilization by over 50% through hardware multiplexing, while eliminating the delay and power consumption introduced by the conversion chip.

[0202] 2. ESD Dual Protection Topology and Adaptive Impedance Matching

[0203] In existing technologies, ESD protection circuits are mostly single-mode designs, making it difficult to simultaneously meet the 100Ω differential impedance requirements of LVDS and the 50Ω single-ended impedance requirements of CMOS. This invention innovatively designs a dual-path isolated ESD protection architecture: the INP branch is equipped with a symmetrical TVS clamp and a 100Ω differential matching network to adapt to LVDS signals, switching to 50Ω single-ended protection with a series resistor and Zener diode in CMOS mode; the INN branch uses an NMOS transistor M1 for mode-specific grounding control, floating in LVDS mode and grounded in CMOS mode. A high-speed analog switch, controlled by the SEL1 signal, operates before the signal path during mode switching, forming a "protection-first" mechanism to ensure the integrity and safety of signals from different data sources, avoiding signal reflection and distortion caused by impedance mismatch in traditional single-protection circuits.

[0204] 3. Digital Logic Intelligent Collaborative Control Logic

[0205] Traditional dual-mode systems often suffer from timing irregularities due to asynchronous control signals, requiring additional synchronization circuits and complex logic designs. This invention, however, achieves end-to-end coordination using only three control signals: SEL1, SEL2, and LVDS_PD, through simplified and efficient control logic. Specifically, after detecting the MOD signal, the digital logic circuit prioritizes pre-configuring the SEL1 / SEL2 gating logic and the LVDS_PD power consumption state to predict the mode. Subsequently, leveraging the characteristic that the ESD module's analog switch switches faster than the DEMUX channel switching, and based on their inherent delay difference, the protection topology switches before the signal path, achieving hardware synchronization. Finally, by receiving status feedback signals from the DEMUX and LVDS receivers, the path switching and module activation status are verified in real time, ensuring the control commands are executed correctly. This control logic eliminates the need for external synchronization chips, achieving low-complexity, high-reliability end-to-end coordination with minimal control signals. Compared to traditional solutions, it significantly simplifies system design and reduces the complexity of dual-mode control.

[0206] Through the above innovations, this invention achieves "plug-and-play" adaptation of the DAC interface circuit to LVDS / CMOS data sources. Compared with traditional solutions, it reduces at least three peripheral chips (level conversion, synchronization, and some protection devices), significantly improving integration and reliability while reducing system costs, and providing a breakthrough solution for the field of multimode signal processing.

[0207] The core functions have been verified through phased simulation. The simulation found that the same interface circuit can be used to convert LVDS to CMOS, and then the CMOS can maintain the complete logic level output.

[0208] In the above description of specific embodiments of the present invention, features described and / or shown for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0209] Although the invention has been disclosed above through the description of specific embodiments, it should be understood that all the embodiments and examples described above are exemplary and not restrictive. Those skilled in the art can design various modifications, improvements, or equivalents to the invention within the spirit and scope of the appended claims. These modifications, improvements, or equivalents should also be considered to be included within the protection scope of the invention.

Claims

1. A digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input, characterized in that: Includes ESD protection circuitry, DEMUX multiplexer, MUX multiplexer, LVDS receiver, inverter chain, and digital logic circuitry; The input terminal of the ESD protection circuit receives the input signal, and the output terminal is connected to the DEMUX multiplexer; the digital logic circuit is used to generate a synchronization control signal according to the external mode switching signal to coordinate the working state of each module; the synchronization control signal includes the SEL1 signal for controlling the DEMUX multiplexer to perform input distribution, the LVDS_PD signal for controlling the LVDS receiver to enter the power-down mode, and the SEL2 signal for controlling the MUX multiplexer to perform selection; The input terminal of the DEMUX multiplexer is connected to the output terminal of the ESD protection circuit. The output terminal includes: a first output branch OUT1, connected to the input terminal of the inverter chain, used to transmit single-ended CMOS signals; and a second output branch OUT2, connected to the differential input terminal of the LVDS receiver, used to transmit differential LVDS signals. The DEMUX multiplexer is used to distribute the input signals output by the ESD protection circuit to the corresponding signal processing paths under the action of the digital logic circuit output control signal SEL1. The positive input terminal of the LVDS receiver receives the INP signal, and the negative input terminal receives the INN signal; the LVDS receiver is used to receive LVDS signals, convert the LVDS signals into single-ended CMOS signals, and output them to the MUX multiplexer. The input of the inverter chain is connected to a DEMUX multiplexer, and the output is connected to a MUX multiplexer; the inverter chain is used to receive CMOS signals. The input terminal of the MUX multiplexer is connected to the inverter chain of the LVDS receiver output terminal and the INP signal input branch; the MUX multiplexer is used to select one of the two input signals to output to the DAC core circuit under the action of the digital logic circuit output control signal SEL2.

2. The digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input according to claim 1, characterized in that: The ESD protection circuit includes a first ESD protection circuit and a second ESD protection circuit; the DEMUX multiplexer includes a first DEMUX multiplexer and a second DEMUX multiplexer; and the inverter chain includes a first inverter chain and a second inverter chain. The SEL1 signal is also used for topology switching of the high-speed analog switch in the first ESD protection circuit and for switching the conduction state of the NMOS transistor M1 in the second ESD protection circuit. The first ESD protection circuit receives the input signal and the SEL1 signal at its input terminal and is connected to the first DEMUX multiplexer at its output terminal; the second ESD protection circuit receives the input signal and the SEL1 signal at its input terminal and is connected to the second DEMUX multiplexer at its output terminal. The output of the first DEMUX multiplexer includes: First output branch: connected to the input of the first inverter chain, used to transmit single-ended CMOS signals; Second output branch: connected to the positive differential input of the LVDS receiver, used to transmit differential LVDS signals; The output of the second DEMUX multiplexer includes: First output branch: connected to the input of the second inverter chain, used only as an impedance matching load when a single-ended CMOS signal is input, and does not transmit the actual signal; The second output branch is connected to the negative differential input of the LVDS receiver and is used to transmit differential LVDS signals.

3. The digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input according to claim 1, characterized in that: The ESD protection circuit includes a first ESD protection circuit and a second ESD protection circuit. The first ESD protection circuit includes a high-speed analog switch, an LVDS-ESD protection circuit, and a CMOS-ESD protection circuit. The common terminal of the high-speed analog switch is connected to the positive terminal of INP and the SEL1 signal. The S1 terminal of the high-speed analog switch is connected to the LVDS-ESD protection circuit, and the S2 terminal of the high-speed analog switch is connected to the CMOS-ESD protection circuit. When SEL1=1: the high-speed analog switch switches the INP branch to the S1 terminal to form LVDS differential protection. When SEL1=0: the high-speed analog switch switches the INP branch to the S2 terminal to form CMOS single-ended protection. The second ESD protection circuit includes an LVDS-ESD protection circuit and an NMOS transistor. The gate of the NMOS transistor is connected to the SEL1 signal, the drain of the NMOS transistor is connected to the output terminal of the LVDS-ESD protection circuit, and the source of the NMOS transistor is grounded.

4. The digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input according to claim 1, characterized in that: The digital-to-analog converter interface circuit has two operating modes: high sampling rate mode and low sampling rate mode.

5. The digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input according to claim 4, characterized in that: In high sampling rate mode, the DEMUX multiplexer switches the input signal to the second output branch OUT2, enabling the LVDS signal path; in low sampling rate mode, the DEMUX multiplexer switches the input signal to the first output branch OUT1, enabling the CMOS signal path. In high sampling rate mode, the LVDS receiver receives the LVDS signal, converts it into a CMOS level signal, and outputs it to the first input terminal of the MUX; in low sampling rate mode, the LVDS receiver enable signal LVDS_PD will cause the receiver to enter a power-down state, and its output is in a high impedance state to avoid interference with the CMOS signal path. In low sampling rate mode, the input of the first inverter chain receives a single-ended CMOS signal, which is processed by N-stage inverters and outputs a standard CMOS signal that meets the input requirements of the MUX multiplexer to the second input of the MUX multiplexer. The delay characteristics of the inverter chain are precisely designed to ensure that it matches the total delay of the LVDS signal path in high sampling rate mode, thereby achieving timing consistency of dual-mode input. In high sampling rate mode, the MUX multiplexer selects the LVDS output signal to output to the DAC core circuit. In low sampling rate mode, the MUX multiplexer selects the output signal of the first inverter chain of the INP input branch to output to the DAC core circuit.

6. The digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input according to claim 4, characterized in that: In this digital-to-analog converter interface circuit, when the external mode switching signal MODE is high, the interface circuit enters a high sampling rate mode, which is suitable for LVDS differential signal input scenarios; the specific process is as follows: S1, ESD protection stage: The LVDS differential signal first passes through the dedicated LVDS protection unit of the ESD protection circuit to ensure that the overvoltage / overcurrent in the input signal is suppressed within a safe range; S2, Signal Distribution Stage: The differential signal processed by the ESD protection circuit enters the DEMUX multiplexer. Under the control of the digital logic circuit output control signal SEL1, the DEMUX multiplexer directs the signal to the second output terminal OUT2, which is directly connected to the differential input terminal of the LVDS receiver. S3, Signal Conversion Stage: The LVDS receiver is activated by the enable signal LVDS_PD and converts the differential signal into a single-ended CMOS signal. S4, Signal Selection Stage: Under the control of the control signal SEL2, the MUX multiplexer selects the output signal of the LVDS receiver and transmits the signal to the DAC core circuit.

7. The digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input according to claim 6, characterized in that: In this digital-to-analog converter interface circuit, when the external mode switching signal MODE is low, the interface circuit switches to low sampling rate mode to adapt to single-ended CMOS signal input, which is connected through the INP interface. The specific process is as follows: S1, ESD protection stage: The CMOS single-ended signal first passes through the CMOS dedicated protection unit of the ESD protection circuit, which can suppress high-frequency noise and clamp the input voltage within a safe range. S2, Signal Distribution Stage: Under the control of the control signal SEL1, the first DEMUX multiplexer directs the ESD output signal to the first output terminal OUT1 and connects it to the first inverter chain. At the same time, the digital logic circuit cuts off the self-bias current of the LVDS receiver through the LVDS_PD signal, causing it to enter a deep power-down state and reduce system power consumption. S3, Signal Conditioning Stage: The CMOS signal enters the inverter chain for shaping and drive enhancement: The first-stage inverter matches the DEMUX output impedance to reduce signal reflection; The intermediate stage inverter optimizes rise / fall times and eliminates edge jitter. The final stage inverter provides the drive current to ensure stable signal driving of the MUX input capacitor; S4, Signal Selection Stage: Under the control of the control signal SEL2, the MUX multiplexer selects the CMOS signal output from the inverter chain and outputs it to the DAC core circuit. The high sampling rate mode supports LVDS signal transmission of ≥500MSPS; the low sampling rate mode supports CMOS signal transmission of ≤125MSPS; in the low sampling rate mode, the digital logic circuit adjusts the bias current of the LVDS receiver to make the LVDS receiver enter the power-down mode.

8. The digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input according to claim 7, characterized in that: The switching operation between low sampling rate mode and high sampling rate mode satisfies the following timing constraints: The wake-up time for switching from low sampling rate mode to high sampling rate mode is ≤100ns; The shutdown delay when switching from high sampling rate mode to low sampling rate mode is ≤50ns.

9. The digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input according to claim 7, characterized in that: The selection operation of the MUX multiplexer is strictly synchronized with the distribution operation of the DEMUX multiplexer. The digital logic circuit ensures that the SEL1 and SEL2 signals are in the same state. When the system switches from high sampling rate mode to low sampling rate mode, the falling edge of the SEL2 signal precedes the falling edge of the LVDS_PD signal by at least 2ns, ensuring that the MUX has switched to the inverter chain output path before the LVDS receiver is completely turned off, thus avoiding signal interruption.

10. The digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input according to claim 1, characterized in that: The inverter chain is a signal conditioning circuit composed of multiple inverters connected in series, each inverter containing both a PMOS transistor and an NMOS transistor; the parameter configuration of the inverter chain satisfies: The input capacitor of the first-stage inverter is matched with the output impedance of the DEMUX multiplexer to suppress reflections and distortion during signal transmission; The output drive capability of the final stage inverter is matched with the input load of the MUX multiplexer to ensure that the signal can stably drive the subsequent circuitry. The aspect ratio of two adjacent inverters is designed according to a progressive amplification structure, so that the signal can achieve edge shaping and enhanced driving capability after passing through the inverter chain; The overall transmission delay is coordinated with the delay of the LVDS receiver path to meet the timing consistency requirements of the digital-to-analog converter core circuit for dual-mode input signals.

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