Analog-to-digital conversion ADC circuit

Abstract

The invention relates to the technical field of power electronics, in particular to an analog-to-digital conversion ADC circuit. The circuit comprises N assembly line modules which are in cascade connection, and N is a positive integer; wherein the effective precision of the first assembly line module is two bits, and the first assembly line module is set to be 2.5 bit quantization. By adopting the scheme, factors such as power consumption, precision, design difficulty and the like of the pipelined ADC can be considered when the first-stage pipelined module is designed.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of power electronics, and particularly relates to an analog-to-digital conversion (ADC) circuit. BACKGROUND

[0002] A pipeline type analog-to-digital conversion (ADC) is composed of a plurality of cascade pipeline modules. Through the processing of each pipeline module, high-precision analog-to-digital conversion can be finally achieved. In the pipeline type ADC, the design of the first-stage pipeline module is the most difficult, and therefore, how to design the first-stage pipeline module to take into account the power consumption, precision, design difficulty and other factors of the pipeline type ADC has become the focus of attention. SUMMARY

[0003] The present disclosure provides an analog-to-digital conversion (ADC) circuit, and the main purpose is to take into account the power consumption, precision, design difficulty and other factors of the pipeline type ADC when designing the first-stage pipeline module.

[0004] According to an aspect of the present disclosure, an analog-to-digital conversion (ADC) circuit is provided, comprising: N cascade-connected pipeline modules, N being a positive integer; wherein,

[0005] The effective precision of the first pipeline module is two bits, and the first pipeline module is set to 2.5-bit quantization.

[0006] Optionally, in an embodiment of the present disclosure, N is 11, the effective precision of the second pipeline module and the eleventh pipeline module is two bits, the effective precision of the third pipeline module to the tenth pipeline module is one bit, the second pipeline module is set to 2.5-bit quantization, the third pipeline module to the tenth pipeline module is set to 1.5-bit quantization, and the eleventh pipeline module is set to 2-bit quantization.

[0007] Optionally, in an embodiment of the present disclosure, the pipeline module adopts a no-sampling-hold structure, and the analog-to-digital conversion (ADC) circuit further comprises a clock generation module and a reference module; wherein,

[0008] The clock generation module is configured to generate a plurality of phase non-overlapping clock signals and input the plurality of phase non-overlapping clock signals into each of the N cascade-connected pipeline modules.

[0009] The reference module is configured to generate at least one reference voltage and input the at least one reference voltage into each of the N cascade-connected pipeline modules.

[0010] N pipeline modules connected in cascade convert a received analog signal into a digital signal according to a plurality of non-overlapping phased clock signals and at least one reference voltage.

[0011] Optionally, in an embodiment of the present disclosure, the clock generating module comprises a clock buffering submodule and a non-overlapping clock generating submodule; wherein,

[0012] The clock buffering submodule is configured to convert the initial clock signal into a target clock signal, wherein a duty cycle of the target clock signal is greater than a duty cycle threshold, and a clock jitter of the target clock signal is lower than a jitter threshold.

[0013] The non-overlapping clock generating submodule is configured to convert the target clock signal into the plurality of non-overlapping phased clock signals and input the plurality of non-overlapping phased clock signals into each of the N pipeline modules connected in cascade.

[0014] Optionally, in an embodiment of the present disclosure, the clock buffering submodule comprises a waveform conversion submodule and a shaping output submodule; wherein,

[0015] The waveform conversion submodule is configured to receive the initial clock signal and convert the initial clock signal into an initial square wave signal.

[0016] The shaping output submodule is configured to shape the initial square wave signal to obtain and output the target clock signal to the non-overlapping clock generating submodule.

[0017] Optionally, in an embodiment of the present disclosure, the initial clock signal comprises a first sinusoidal wave signal and a second sinusoidal wave signal that are differentially connected to each other, the waveform conversion submodule comprises a first analog power supply, a first analog ground, a first amplifier, a first capacitor, a second capacitor, a first resistor, a first P-type switch tube, and a first N-type switch tube, and the shaping output submodule comprises a second analog power supply, a first inverter, a second inverter, and a second analog ground; wherein,

[0018] The positive input end of the first amplifier receives the first sinusoidal wave signal, the positive output end of the first amplifier receives the second sinusoidal wave signal, the power supply end of the first amplifier is connected to the first analog power supply, the ground end of the first amplifier is connected to the first analog ground, the output end of the first amplifier is connected to the first end of the first capacitor, the second end of the first capacitor is connected to the first end of the second capacitor, the first end of the first resistor, the gate of the first P-type switch tube, and the gate of the first N-type switch tube, respectively, the second end of the second capacitor and the source of the first N-type switch tube are connected to the second analog ground, the source of the first P-type switch tube is connected to the second analog power supply, the drain of the first P-type switch tube is connected to the second end of the first resistor, the drain of the first N-type switch tube, and the input end of the first inverter, respectively, the output end of the first inverter is connected to the input end of the second inverter, and the output end of the second inverter is connected to the non-overlapping clock generating submodule.

[0019] Optionally, in an embodiment of the present disclosure, the reference module comprises a bandgap reference submodule, a reference voltage generation submodule; wherein,

[0020] The bandgap reference submodule is configured to generate an initial reference voltage.

[0021] The reference voltage generation submodule is configured to convert the initial reference voltage into at least one reference voltage, and input the at least one reference voltage into each of the N cascade-connected pipeline modules.

[0022] Optionally, in an embodiment of the present disclosure, the bandgap reference submodule comprises a third analog power supply, a third analog ground, a second P-type switch tube, a third P-type switch tube, a fourth P-type switch tube, a fifth P-type switch tube, a sixth P-type switch tube, a seventh P-type switch tube, an eighth P-type switch tube, a ninth P-type switch tube, a tenth P-type switch tube, an eleventh P-type switch tube, a twelfth P-type switch tube, a thirteenth P-type switch tube, a fourteenth P-type switch tube, a second N-type switch tube, a third N-type switch tube, a fourth N-type switch tube, a fifth N-type switch tube, a sixth N-type switch tube, a second resistor, a third resistor, and a fourth resistor; wherein,

[0023] The third analog power supply is connected with the source of the second P-type switch tube, the source of the third P-type switch tube, the source of the fourth P-type switch tube, the source of the fifth P-type switch tube, the source of the sixth P-type switch tube, the source of the seventh P-type switch tube, and the source of the eighth P-type switch tube, respectively.

[0024] The gate of the second P-type switch tube is connected with the gate of the third P-type switch tube, the drain of the fourth P-type switch tube and the drain of the second N-type switch tube respectively, the gate of the second N-type switch tube receives an enable signal, the drain of the second P-type switch tube is connected with the gate and the drain of the third N-type switch tube, the gate of the fourth N-type switch tube, the drain of the ninth P-type switch tube respectively, the drain of the third P-type switch tube is connected with the drain of the fourth N-type switch tube, the gate of the fifth N-type switch tube, the gate of the sixth N-type switch tube, the drain of the tenth P-type switch tube respectively, the source of the ninth P-type switch tube is connected with the source of the tenth P-type switch tube and the drain of the fifth P-type switch tube, the gate of the fourth P-type switch tube is connected with the gate of the fifth P-type switch tube, the gate and the drain of the sixth P-type switch tube, the gate of the eighth P-type switch tube and the drain of the fifth N-type switch tube respectively, the gate of the seventh P-type switch tube is connected with the drain of the eleventh P-type switch tube and the drain of the sixth N-type switch tube respectively, the drain of the seventh P-type switch tube is connected with the source of the eleventh P-type switch tube, the gate of the eleventh P-type switch tube is connected with the gate of the twelfth P-type switch tube, the source of the twelfth P-type switch tube is connected with the drain of the eighth P-type switch tube, the gate of the ninth P-type switch tube is connected with the source of the thirteenth P-type switch tube and the first end of the second resistor respectively, the gate of the tenth P-type switch tube is connected with the first end of the third resistor and the first end of the fourth resistor respectively, the second end of the third resistor (R1) is connected with the source of the fourteenth P-type switch tube, and the connection point between the drain of the twelfth P-type switch tube, the second end of the second resistor and the second end of the fourth resistor is connected with the reference voltage generating submodule.

[0025] The third analog ground is connected with the source of the second N-type switch tube, the source of the third N-type switch tube, the source of the fourth N-type switch tube, the source of the fifth N-type switch tube, the source of the sixth N-type switch tube, the gate and the drain of the thirteenth P-type switch tube, and the gate and the drain of the fourteenth P-type switch tube respectively.

[0026] Optionally, in an embodiment of the present disclosure, the reference voltage generating submodule comprises at least one reference voltage generating circuit, and the reference voltage generating circuit comprises a fourth analog power supply, a fourth analog ground, an operational amplifier, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a third capacitor, a fourth capacitor, and a fifteenth P-type switch tube; wherein,

[0027] The first end of the fifth resistor is connected with the bandgap reference module, the second end of the fifth resistor is connected with the positive input end of the operational amplifier and the first end of the third capacitor respectively, the output end of the operational amplifier is connected with the gate of the fifteenth P-type switch tube and the first end of the sixth resistor respectively, the second end of the sixth resistor is connected with the first end of the fourth capacitor, the second end of the fourth capacitor is connected with the drain of the fifteenth P-type switch tube and the first end of the seventh resistor respectively, the source of the fifteenth P-type switch tube is connected with the fourth analog power supply, the second end of the seventh resistor is connected with the negative input end of the operational amplifier and the first end of the eighth resistor respectively, the second end of the eighth resistor is connected with the connecting point between the ninth resistor and the flow pipeline module;

[0028] The second end of the third capacitor and the second end of the ninth resistor are connected with the fourth analog ground.

[0029] Optionally, in an embodiment of the present disclosure, the operational amplifier comprises a fifth analog power supply, a fifth analog ground, a sixteenth P-type switch tube, a seventeenth P-type switch tube, an eighteenth P-type switch tube, a nineteenth P-type switch tube, a twentieth P-type switch tube, a twenty-first P-type switch tube, a twenty-second P-type switch tube, a twenty-third P-type switch tube, a twenty-fourth P-type switch tube, a seventh N-type switch tube, an eighth N-type switch tube, a ninth N-type switch tube, a tenth N-type switch tube, an eleventh N-type switch tube, a twelfth N-type switch tube, a thirteenth N-type switch tube, a fourteenth N-type switch tube, a fifteenth N-type switch tube, a sixteenth N-type switch tube, a seventeenth N-type switch tube; wherein,

[0030] The fifth analog power supply is connected with the gate and the drain of the seventh N-type switch tube, the gate of the eighth N-type switch tube, the gate of the ninth N-type switch tube, the gate of the tenth N-type switch tube, the source of the sixteenth P-type switch tube, the source of the seventeenth P-type switch tube, the source of the eighteenth P-type switch tube, the source of the nineteenth P-type switch tube, and the source of the twentieth P-type switch tube respectively;

[0031] The gate of the sixteenth P-type switch tube is connected with the gate of the nineteenth P-type switch tube, the drain of the sixteenth P-type switch tube is connected with the source of the twenty-first P-type switch tube, the drain of the twenty-first P-type switch tube is connected with the drain of the eighth N-type switch tube, the gate of the twenty-first P-type switch tube is connected with the gate of the seventeenth P-type switch tube, the gate and the drain of the twenty-second P-type switch tube and the drain of the ninth N-type switch tube respectively, the drain of the seventeenth P-type switch tube is connected with the source of the twenty-second P-type switch tube, the gate of the eighteenth P-type switch tube is connected with the gate of the twentieth P-type switch tube, the drain of the twenty-third P-type switch tube and the drain of the eleventh N-type switch tube respectively, the drain of the eighteenth P-type switch tube is connected with the source of the twenty-third P-type switch tube, the drain of the twentieth P-type switch tube is connected with the source of the twenty-fourth P-type switch tube, the gate of the twenty-third P-type switch tube is connected with the gate of the twenty-fourth P-type switch tube, the gate of the eleventh N-type switch tube is connected with the gate of the twelfth N-type switch tube, the gate of the thirteenth N-type switch tube, the gate of the fourteenth N-type switch tube and the gate of the fifteenth N-type switch tube respectively, the drain of the nineteenth P-type switch tube is connected with the drain of the thirteenth N-type switch tube, the source of the thirteenth N-type switch tube is connected with the drain of the fourteenth N-type switch tube, the source of the fourteenth N-type switch tube is connected with the drain of the fifteenth N-type switch tube, the source of the fifteenth N-type switch tube is connected with the source of the sixteenth N-type switch tube, the source of the seventeenth N-type switch tube and the drain of the tenth N-type switch tube respectively, the source of the eleventh N-type switch tube is connected with the drain of the sixteenth N-type switch tube, the source of the twelfth N-type switch tube is connected with the drain of the seventeenth N-type switch tube;

[0032] The connection point between the drain of the twenty-fourth P-type switch tube and the drain of the twelfth N-type switch tube is the output end of the operational amplifier, the gate of the sixteenth N-type switch tube is the positive output end of the operational amplifier, and the gate of the seventeenth N-type switch tube is the negative output end of the operational amplifier;

[0033] The source of the seventh N-type switch tube, the source of the eighth N-type switch tube, the source of the ninth N-type switch tube, and the source of the tenth N-type switch tube are connected with the fifth analog ground.

[0034] In summary, in one or more embodiments of the embodiments of the present disclosure, by compromising the factors such as power consumption, accuracy, design difficulty of the pipeline module, the effective accuracy of the first pipeline module (Stage 1) is set to two bits, and the first pipeline module (Stage 1) is set to 2.5 bit quantization. When designing the first-stage pipeline module, the power consumption, accuracy, design difficulty and other factors of the pipeline type ADC are considered.

[0035] Additional aspects and advantages of the present disclosure will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0036] The above mentioned and / or additional aspects and advantages of the present disclosure will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings in which:

[0037] Figure 1 A structural schematic diagram of an analog-to-digital conversion (ADC) circuit provided by an embodiment of the present disclosure;

[0038] Figure 2 An ideal transfer curve of a 2.5-bit pipeline module provided by an embodiment of the present disclosure;

[0039] Figure 3 A schematic diagram of the relationship between power consumption and precision provided by an embodiment of the present disclosure;

[0040] Figure 4 A structural schematic diagram of a clock buffer sub-module provided by an embodiment of the present disclosure;

[0041] Figure 5 A voltage waveform diagram of a key node of a clock buffer sub-module provided by an embodiment of the present disclosure;

[0042] Figure 6 A structural schematic diagram of a clock buffer sub-module provided by an embodiment of the present disclosure;

[0043] Figure 7 A structural schematic diagram of a bandgap reference sub-module provided by an embodiment of the present disclosure;

[0044] Figure 8 A structural schematic diagram of a reference voltage generation circuit provided by an embodiment of the present disclosure;

[0045] Figure 9 A structural schematic diagram of an operational amplifier provided by an embodiment of the present disclosure;

[0046] Figure 10 A setting schematic diagram of a non-ideal factor provided by an embodiment of the present disclosure;

[0047] Figure 11 A display schematic diagram of a simulation result provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, examples of which are shown in the drawings, wherein the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present disclosure, and cannot be understood as a limitation of the present disclosure. On the contrary, the embodiments of the present disclosure include all changes, modifications and equivalents falling within the spirit and scope of the appended claims.

[0049] The present disclosure will be described in detail below with specific embodiments.

[0050] Figure 1 A structural schematic diagram of an analog-to-digital conversion (ADC) circuit provided by an embodiment of the present disclosure.

[0051] As shown in Figure 1 , the analog-to-digital conversion (ADC) circuit includes N cascade-connected pipeline modules, where N is a positive integer.

[0052] It should be noted that the design difficulty of Stage1 in the analog-to-digital conversion (ADC) circuit is the largest. On the one hand, if Stage1 adopts a traditional structure of 1.5 bits, the effective precision of the sub-digital-to-analog conversion (MDAC) module in Stage1 needs to be designed very high. On the other hand, if Stage1 adopts a multi-bit structure, the design of the sub-digital-to-analog conversion (Sub-ADC) module in Stage1 will have higher requirements.

[0053] wherein, Figure 2 An ideal transfer curve of a 2.5-bit pipeline module provided by an embodiment of the present disclosure. As shown in Figure 2 , there are a total of 6 decision points, 7 decision intervals, the inter-stage gain is 4, and the least significant bit (LSB) of the Sub-ADC is 200 mV (differential). In this case, when Stage1 adopts a 2.5-bit structure (redundant 1 bit), the redundant range of this structure is more than one time relative to the 1.5-bit structure, and relative to the 3.5-bit structure, it has higher energy efficiency and can save the dynamic offset voltage calibration circuit in the front end of the complex sample-and-hold-less (SHA-less) structure. If Stage1 is redundant by 0.5 bits, when the voltage value Vin of the analog input is greater than 7 / 8 of the reference voltage Vref, the residual output Vres of Stage1 is greater than 1 / 2 Vref. At this time, the swing of the operational amplifier in Stage1 is increased, and the working region of the transistor in the operational amplifier may be close to the linear region, which will deteriorate the linearity of the operational amplifier, so the residual output of Stage1 can be folded back. When the offset voltage of the pipeline stage is not considered, the output swing of the operational amplifier in Stage1 can be limited within 1 / 2 Vref. At this time, the number of bits of Stage1 is 2 bits, which is approximately redundant by 1 bit.

[0054] wherein, Vrefb is a negative reference voltage, and Vreft is a positive reference voltage.

[0055] In summary, the disclosed embodiments compromise the power consumption, accuracy, design difficulty and other factors of the Sub-ADC and the MDAC, set the effective accuracy of the first pipeline module (Stage 1) to two bits, and set the first pipeline module (Stage 1) to 2.5-bit quantization.

[0056] In addition, the higher the number of bits of each stage of the pipeline ADC, the fewer the total number of pipeline stages required, and the fewer the number of residual amplifiers required, but at the same time, the requirements for the operational amplifier and the sub-ADC in each pipeline module are higher. The accuracy selection of each bit pipeline module in the pipeline ADC needs to be analyzed from linearity and noise.

[0057] First, the accuracy selection of each bit pipeline module in the pipeline ADC is analyzed from linearity, and the differential nonlinearity (DNL) caused by the capacitance mismatch of the pipeline module is:

[0058]

[0059] wherein, ΔC j is the mismatch value of each capacitor in the pipeline module, C t is the total value of the capacitance of the pipeline module, and n is the total resolution of the analog-to-digital conversion ADC circuit. Assuming that the effective accuracy of the pipeline module is M bits, the unit capacitance value C of each unit capacitor in the pipeline module is:

[0060]

[0061] If only the random mismatch of the capacitor is considered, the mismatch ratio is inversely proportional to the square root of the capacitance:

[0062]

[0063] wherein, k is a constant, not a fixed value, but a variable related to the capacitance and its application conditions.

[0064] Therefore, the absolute value of the capacitance mismatch is:

[0065]

[0066] Since the absolute value of the capacitance mismatch is proportional to the square root of the unit capacitance, the differential nonlinearity (DNL) is:

[0067]

[0068] It is easy to understand that the above formula shows that, under the condition of a certain total capacitance value, increasing the effective accuracy M of the pipeline module can reduce the differential nonlinearity, which is beneficial to the linearity of the analog-to-digital conversion ADC circuit.

[0069] Secondly, the accuracy of each stage of the pipeline module is considered from the noise point of view, all noise sources can be equivalent to the input. Among them, taking a single pole system as an example, and assuming that the load capacitance C L is determined by the sampling capacitance of the Nth pipeline module. When the effective accuracy M of the pipeline module increases by one bit, the signal gain G of the pipeline module doubles, and the feedback coefficient β of the pipeline module decreases by half without considering the parasitic capacitance. Therefore, in order to maintain the loop bandwidth of the pipeline module without increasing the power consumption, the load capacitance C L also needs to be reduced by half.

[0070] In this case, the sampling phase and the amplification phase of the N-1th pipeline module and the sampling capacitance noise power of the Nth pipeline module are equivalent to the input end:

[0071]

[0072] Where T is the temperature, C S is the sampling capacitance of the N-1th pipeline module, indicating that when the number of bits of the N-1th pipeline module increases by one bit, the sampling capacitance noise power of the Nth pipeline module decreases by half.

[0073] That is, the N-1th pipeline module and the Nth pipeline module are weakly related functions of the number of bits, and in general, the higher the number of bits of the pipeline module, the lower the equivalent input noise power. However, the above formula assumes that the load capacitance of the N-1th pipeline module is completely determined by the sampling capacitance of the Nth pipeline module, and when the number of bits of the N-1th pipeline module increases too much, the sampling capacitance of the Nth pipeline module cannot be infinitely reduced, and when the sampling capacitance of the Nth pipeline module decreases to a certain extent, the parasitic capacitance of the operational amplifier and the switch in the Nth pipeline module and the layout trace will become non-negligible.

[0074] When the ADC works at low speed, if the output parasitic capacitance of the operational amplifier and the parasitic capacitance of the input node are considered, the analysis result is consistent with the above analysis, and the higher the accuracy of the pipeline module, the higher the energy efficiency. But in high-speed ADC, smaller capacitance is generally used, at this time the feedback coefficient of the input parasitic capacitance of the operational amplifier will be greatly reduced, thereby reducing the speed of the ADC, and the influence of the load parasitic capacitance is more obvious. If you want to ensure speed and accuracy, you need more operational amplifier power consumption. Therefore, in high-speed ADC, the higher the accuracy of the pipeline module, the lower the energy efficiency.

[0075] Where, Figure 3 is a schematic diagram of the relationship between power consumption and accuracy provided by the embodiment of the present disclosure. As Figure 3As shown in FIG. 6, which shows the relationship between the power consumption of the analog-to-digital conversion ADC circuit and the number of bits of each pipeline module in both low-speed and high-speed cases, it can be seen that the higher the accuracy of the pipeline module, the lower the energy efficiency.

[0076] In summary, as Figure 1 shown, the analog-to-digital conversion ADC circuit provided by the embodiments of the present disclosure can adopt 11 pipeline modules, that is, N is 11, adopt an accuracy allocation of 2-2-1-1-1-1-1-1-1-1-2, a total of 14 bits, is downward compatible with 12-bit output, the effective accuracy of the second pipeline module and the eleventh pipeline module is two bits, the effective accuracy of the third pipeline module to the tenth pipeline module is one bit, the second pipeline module is set to 2.5-bit quantization, the third pipeline module to the tenth pipeline module is set to 1.5-bit quantization, and the eleventh pipeline module is set to 2-bit quantization.

[0077] According to some embodiments, when the analog-to-digital conversion ADC circuit is working, the sub-analog-to-digital converter in the Nth pipeline module can sample and quantize the output signal of the (N-1)th pipeline module to obtain an N-bit digital signal, the sub-analog-to-digital converter in the Nth pipeline module can subtract the N-bit digital signal from the output signal of the (N-1)th pipeline module to obtain a residual signal corresponding to the Nth pipeline module, and the residual amplifier in the Nth pipeline module can amplify the residual signal to obtain a final output signal and input the signal into the next pipeline module.

[0078] Optionally, as Figure 1 shown, the ADC circuit further includes an error calibration module, which can calibrate the output of each pipeline module and add the calibrated N digital output signals in a staggered manner to obtain a final digital output signal.

[0079] Optionally, the pipeline module can adopt a SHA-less structure.

[0080] It should be noted that in the traditional structure of the pipeline ADC, the sample-and-hold structure is at the forefront of the entire pipeline link, and under the control of the clock, it can sample and hold the analog input signal. The hold signal output by the sample-and-hold structure is a direct current-like signal relative to the first pipeline module. The advantage is that the first pipeline stage does not need to face the high-frequency changing signal of the input, and is also isolated from the parasitic brought by the chip pin. At the same time, the signals sampled by the sub-analog-to-digital converter and the MDAC are consistent. However, the sample-and-hold structure will result in more power consumption and area required by the analog-to-digital conversion ADC circuit.

[0081] As Figure 1As shown, in the case of no sample-and-hold structure, the first pipeline module directly samples the analog input signal, so that the power consumption can be saved to the greatest extent, and the area required by the sample-and-hold structure can also be saved.

[0082] According to some embodiments, the no sample-and-hold structure is selected, and a large redundancy space is required to tolerate dynamic offset voltage. The effective precision of the first pipeline module and the second pipeline module in the embodiments of the present disclosure is selected to be two bits, which can provide a large redundancy space to tolerate dynamic offset voltage.

[0083] Optionally, an inter-stage reduction technique can be used to reduce the power consumption of the analog-to-digital conversion ADC circuit.

[0084] According to some embodiments, the basic idea of the inter-stage reduction technique is to appropriately reduce between the pipeline modules to reduce the required power consumption. Specifically, the inter-stage reduction technique can optimize the resolution, power supply voltage or reference voltage of the pipeline module, etc. By reducing the resolution of the pipeline module, the number of comparators required and the power consumption can be reduced.

[0085] In some embodiments, there are various implementation manners of the inter-stage reduction technique, such as using a segmented comparator, a dynamic power supply voltage and a reference voltage, etc. These techniques can be selected and optimized according to specific application scenarios and performance requirements.

[0086] Optionally, an op-amp sharing technique can also be used to reduce the power consumption of the analog-to-digital conversion ADC circuit.

[0087] In some embodiments, the op-amp sharing technique refers to that when N cascade-connected pipeline modules are working, the holding state of the previous pipeline module and the sampling state of the next pipeline module are in the same clock phase, the operation of the sampling phase does not require the participation of the operational amplifier, so one operational amplifier can be shared between the two pipeline modules with completely different phases, so that the number of operational amplifiers can be reduced, thereby reducing the overall power consumption and chip area.

[0088] Optionally, the analog-to-digital conversion ADC circuit further comprises a clock generation module and a reference module, wherein,

[0089] The clock generation module is configured to generate a plurality of phase non-overlapping clock signals and input the plurality of phase non-overlapping clock signals into each of the N cascade-connected pipeline modules.

[0090] The reference module is configured to generate at least one reference voltage and input the at least one reference voltage into each of the N cascade-connected pipeline modules.

[0091] N cascade connected pipeline modules convert received analog signals into digital signals according to a plurality of non-overlapping clock signals and at least one reference voltage.

[0092] According to some embodiments, the plurality of non-overlapping clock signals refers to clock signals with multiple phases and no overlap with each other. In the plurality of non-overlapping clock signals, each clock phase has its own unique phase relationship, usually with a certain angular offset. These clock phases can perform different operations in different time periods, thereby achieving parallel processing and high-speed data transmission. The plurality of non-overlapping clock signals has many advantages. First, it can improve the efficiency of the circuit, because multiple operations can be performed simultaneously, reducing the waiting time. Second, the plurality of non-overlapping clock signals can reduce the power consumption of the circuit, because it can reduce unnecessary waiting and idle time. In addition, the plurality of non-overlapping clock signals can also improve the stability of the circuit, because it reduces the timing errors caused by clock signal delay.

[0093] It should be noted that in the case of using the operational amplifier sharing technology, the operational amplifier works in two phases that are completely different from each other. In one cycle, the operational amplifier is always in working state and has no time to zero the input offset of the operational amplifier. The actual gain error of the operational amplifier affects the result of each amplification, thereby affecting the sampling accuracy of this time, which is called "memory effect". Second, in order to realize the inter-stage sharing of the operational amplifier, a number of switches need to be introduced. The channel charge injection and clock feedthrough effect introduced by these switches will produce additional errors. In addition, the series resistance introduced by these switches combined with the input capacitance of the operational amplifier will reduce the sampling rate of the pipeline module.

[0094] To solve the problems caused by the use of the operational amplifier sharing technology, the clock generation module can lengthen the period of the plurality of non-overlapping clock signals generated by the clock generation module, and insert a reset phase before each operation of the operational amplifier, so as to zero the input and output of the operational amplifier.

[0095] Optionally, the clock generation module comprises a clock buffering submodule and a non-overlapping clock generation submodule; wherein,

[0096] The clock buffering submodule is configured to convert the initial clock signal into a target clock signal, wherein the duty cycle of the target clock signal is greater than a duty cycle threshold, and the clock jitter of the target clock signal is lower than a jitter threshold.

[0097] The non-overlapping clock generation submodule is configured to convert the target clock signal into a plurality of non-overlapping clock signals, and input the plurality of non-overlapping clock signals into each of the N cascade connected pipeline modules.

[0098] It should be noted that the duty cycle and clock jitter of the target clock signal are the main indicators that restrict the ADC circuit.

[0099] In some embodiments, due to the structural characteristics of the pipeline ADC, the amplification phase of the current pipeline module is the sampling phase of the next pipeline module, and the amplification phase of the next pipeline module is the sampling phase of the pipeline module behind it. Therefore, in order to ensure that each pipeline module has sufficient time for amplification, the clock duty cycle of the target clock signal needs to be kept at 50%. That is, the duty cycle threshold can be no less than 50%.

[0100] According to some embodiments, a single tone signal is often generated by a crystal oscillator or a specific phase-locked loop circuit, and the generated sine wave more or less has interference, which is manifested as phase noise in the frequency spectrum and as jitter in the time domain. Assuming that the clock jitter at the sampling time is t j , the input signal frequency is f0, and the root mean square of the signal amplitude is A rms , the noise power N Jitter caused by jitter is:

[0101] N Jitter =(2πf0A rms t j ) 2

[0102] Since jitter is a random variable, the error caused by sampling a changing signal also appears as noise. Assuming that the sum of all low-frequency noise powers is N low , and the sum of the noise powers caused by clock jitter is N t , the signal-to-noise ratio of the ADC circuit is:

[0103] SNR=10log(SI(N low +N Jitter ))

[0104] where S is the signal power, and SNR is the total signal-to-noise ratio. After rearranging the above formula, the clock jitter t j is obtained:

[0105]

[0106] where SRN low is the total signal-to-noise ratio when the input signal is low frequency. According to the requirement that the signal-to-noise ratio of the ADC circuit is ≥65dB@input signal bandwidth (BW)=40MHZ & highest sampling, the total time jitter requirement can be obtained, that is, the jitter threshold is no more than 100.

[0107] Optionally, the clock buffer sub-module comprises a waveform conversion sub-module and a shaping output sub-module; wherein,

[0108] The waveform conversion submodule is used to receive the initial clock signal and convert it into an initial square wave signal;

[0109] The shaping output submodule is used to shape the initial square wave signal to obtain and output the target clock signal to the non-overlapping clock generation submodule.

[0110] According to some embodiments, Figure 4 This is a schematic diagram of the structure of a clock buffer submodule provided in an embodiment of this disclosure. Figure 4 As shown, the initial clock signal includes a first sine wave signal CLKN and a second sine wave signal CLKP that are differentially expressed. The waveform conversion submodule includes a first analog power supply AVDD1, a first analog ground AVSS1, a first amplifier, a first capacitor C1, a second capacitor C2, a first resistor R1, a first P-type switch PM1, and a first N-type switch NM1. The shaping output submodule includes a second analog power supply AVDD2, a first inverter, a second inverter, and a second analog ground AVSS2.

[0111] The positive input terminal of the first amplifier receives the first sine wave signal CLKN, and the positive output terminal of the first amplifier receives the second sine wave signal CLKP. The power supply terminal of the first amplifier is connected to the first analog power supply AVDD1, the ground terminal of the first amplifier is connected to the first analog ground AVSS1, the output terminal of the first amplifier is connected to the first terminal of the first capacitor C1, the second terminal of the first capacitor C1 is connected to the first terminal of the second capacitor C2, the first terminal of the first resistor R1, the gate of the first P-type switch PM1, and the gate of the first N-type switch NM1, respectively. The second terminal of the second capacitor C2 and the source of the first N-type switch NM1 are connected to the second analog ground AVSS2, the source of the first P-type switch PM1 is connected to the second analog power supply AVDD2, the drain of the first P-type switch PM1 is connected to the second terminal of the first resistor R1, the drain of the first N-type switch NM1, and the input terminal of the first inverter, respectively. The output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the non-overlapping clock generation submodule.

[0112] Among them, such as Figure 4 As shown, the output of the second inverter can output the target clock signal CLKO to the non-overlapping clock generation submodule.

[0113] To reduce clock jitter, the circuit between the first amplifier and the non-overlapping clock generation submodule can utilize a core device. The supply voltage provided by the first analog power supply AVDD1 and the second analog power supply AVDD2 can range from 0.35V to 1.3V. In this case, the first amplifier outputs a sinusoidal signal of 0–2.5V. Therefore, connecting the first capacitor C1 across the first amplifier can reduce its output swing, and the second capacitor C2 can be used to fine-tune the rising edge of the first amplifier's output.

[0114] The first resistor R1 connected between the gate and drain of the first P-type switch PM1 and the first N-type switch NM1 can accelerate the falling edge speed of the connection point (point C) between the drain of the first P-type switch PM1 and the drain of the first N-type switch NM1.

[0115] In some embodiments, Figure 5 The voltage waveform diagram of a key node of a clock buffer submodule provided in an embodiment of this disclosure is shown. Figure 5 As shown, the output terminal of the first amplifier (point A) and the second terminal of the first capacitor C1 (point B) both output sinusoidal signals, point C outputs a square wave signal, and the target clock signal CLKO output by the output terminal of the second inverter is a square wave signal.

[0116] According to some embodiments, Figure 6 This is a schematic diagram of the structure of a clock buffer submodule provided in an embodiment of this disclosure. Figure 6 As shown, the first amplifier uses a two-stage common-source amplifier. In this case, the clock buffer submodule includes the sixth analog power supply AVDD6, the sixth analog ground AVSS6, the twenty-fifth P-type switch PM25, the twenty-sixth P-type switch PM26, the twenty-seventh P-type switch PM27, the twenty-eighth P-type switch PM28, the twenty-ninth P-type switch PM29, the thirtieth P-type switch PM30, the thirty-first P-type switch PM31, the thirty-second P-type switch PM32, the eighteenth N-type switch NM18, the nineteenth N-type switch NM19, and the second... The following transistors are included: NM20 (10-type N-type), NM21 (21-type N-type), NM22 (22-type N-type), NM23 (23-type N-type), NM24 (24-type N-type), NM25 (25-type N-type), NM26 (26-type N-type), NM27 (27-type N-type), NM28 (28-type N-type), R10 (10-type), R11 (11-type), R12 (12-type), R13 (13-type), R14 (14-type), C5 (5-type), C6 (6-type), C6 (6-type), C7 (7-type), and C8 (8-type).

[0117] The sixth analog power supply AVDD6 is connected with the drain and the gate of the eighteenth N-type switch tube NM18, the gate of the nineteenth N-type switch tube NM19, the gate of the twentieth N-type switch tube NM20, the source of the twenty-fifth P-type switch tube PM25, the source of the twenty-sixth P-type switch tube PM26, the source of the twenty-seventh P-type switch tube PM27, the source of the twenty-eighth P-type switch tube PM28, the source of the twenty-ninth P-type switch tube PM29, the source of the thirtieth P-type switch tube PM30, the first end of the tenth resistor R10, and the first end of the eleventh resistor R11 respectively;

[0118] The gate of the twenty-fifth P-type switch tube PM25 is connected with the gate of the twenty-seventh P-type switch tube PM27, the drain of the twenty-fifth P-type switch tube PM25 is connected with the drain of the nineteenth N-type switch tube NM19, the gate of the twenty-sixth P-type switch tube PM26 is connected with the gate and the drain of the thirty-first P-type switch tube PM31, the gate of the thirty-second P-type switch tube PM32 and the drain of the twenty-seventh P-type switch tube PM27 respectively, the drain of the twenty-seventh P-type switch tube PM27 is connected with the source of the thirty-second P-type switch tube PM32, the drain of the thirty-second P-type switch tube PM32 is connected with the gate and the drain of the twenty-first N-type switch tube NM21 and the first end of the twelfth resistor R12 respectively, the second end of the twelfth resistor R12 is connected with the first end of the fifth capacitor C5, the gate of the twenty-second N-type switch tube NM22 and the gate of the twenty-third N-type switch tube NM23 respectively, the drain of the twenty-second N-type switch tube NM22 is connected with the source of the twenty-fourth N-type switch tube NM24 and the source of the twenty-fifth N-type switch tube NM25 respectively, the drain of the twenty-fourth N-type switch tube NM24 is connected with the second end of the tenth resistor R10 and the gate of the twenty-sixth N-type switch tube NM26 respectively, the gate of the twenty-fourth N-type switch tube NM24 and the gate of the twenty-fifth N-type switch tube NM25 receive the first sinusoidal signal CLKN and the second sinusoidal signal CLKP which are different from each other respectively, the drain of the twenty-fifth N-type switch tube NM25 is connected with the second end of the eleventh resistor R11 and the gate of the twenty-seventh N-type switch tube NM27 respectively, the drain of the twenty-third N-type switch tube NM23 is connected with the source of the twenty-sixth N-type switch tube NM26 and the source of the twenty-seventh N-type switch tube NM27 respectively, the drain of the twenty-sixth N-type switch tube NM26 is connected with the drain of the twenty-eighth P-type switch tube PM28, the first end of the thirteenth resistor R13 and the first end of the sixth capacitor C6 respectively, the gate of the twenty-eighth P-type switch tube PM28 is connected with the gate of the twenty-ninth P-type switch tube PM29, the second end of the thirteenth resistor R13 and the second end of the sixth capacitor C6 respectively, the drain of the twenty-ninth P-type switch tube PM29 is connected with the drain of the twenty-seventh N-type switch tube NM27, the gate of the thirtieth P-type switch tube PM30, the gate of the twenty-eighth N-type switch tube NM28 and the first end of the fourteenth resistor R14 respectively, the drain of the thirtieth P-type switch tube PM30 is connected with the drain of the twenty-eighth N-type switch tube NM28, the second end of the fourteenth resistor R14 and the input end of the third inverter respectively, the output end of the third inverter is connected with the input end of the fourth inverter, the output end of the fourth inverter is connected with the non-overlapping clock generation sub-module.

[0119] The source of the eighteenth N-type switch NM18, the source of the nineteenth N-type switch NM19, the source of the twentieth N-type switch NM20, the source of the twenty-first N-type switch NM21, the source of the twenty-second N-type switch NM22, the source of the twenty-third N-type switch NM23, the source of the twenty-eighth N-type switch NM28, and the second terminal of the fifth capacitor C5 are connected to the sixth analog ground AVSS6.

[0120] It should be noted that in order to obtain a low-jitter clock, a fast transient rise or fall rate is required at the zero-crossing point. At this time, the input transistor of the first amplifier is in saturation, which essentially requires a large input transistor transconductance. Therefore, from the design concept of gm / ld, the Vdsat of the input transistor needs to be as small as possible to obtain the largest possible gm / ld. In essence, to increase gm, a sufficiently large quiescent current and a sufficiently large input transistor size are still required.

[0121] Optionally, the reference module includes a bandgap reference submodule and a reference voltage generation submodule; wherein,

[0122] The bandgap reference submodule is used to generate the initial reference voltage;

[0123] A reference voltage generation submodule is used to convert an initial reference voltage into at least one reference voltage and input the at least one reference voltage to each of N cascaded pipeline modules.

[0124] According to some embodiments, Figure 7 This is a schematic diagram of the structure of a bandgap reference submodule provided in an embodiment of this disclosure. Figure 7 As shown, the bandgap reference submodule includes a third analog power supply AVDD3, a third analog ground AVSS3, a second P-type switch PM2, a third P-type switch PM3, a fourth P-type switch PM4, a fifth P-type switch PM5, a sixth P-type switch PM6, a seventh P-type switch PM7, an eighth P-type switch PM8, a ninth P-type switch PM9, a tenth P-type switch PM10, an eleventh P-type switch PM11, a twelfth P-type switch PM12, a thirteenth P-type switch PM13, a fourteenth P-type switch PM14, a second N-type switch NM2, a third N-type switch NM3, a fourth N-type switch NM4, a fifth N-type switch NM5, a sixth N-type switch NM6, a second resistor R2, a third resistor R3, and a fourth resistor R4; among which,

[0125] The third analog power supply AVDD3 is connected with the source of the second P-type switch PM2, the source of the third P-type switch PM3, the source of the fourth P-type switch PM4, the source of the fifth P-type switch PM5, the source of the sixth P-type switch PM6, the source of the seventh P-type switch PM7, and the source of the eighth P-type switch PM8, respectively.

[0126] The gate of the second P-type switch PM2 is connected with the gate of the third P-type switch PM3, the drain of the fourth P-type switch PM4, and the drain of the second N-type switch NM2, respectively. The gate of the second N-type switch NM2 receives an enable signal EN. The drain of the second P-type switch PM2 is connected with the gate and the drain of the third N-type switch NM3, the gate of the fourth N-type switch NM4, and the drain of the ninth P-type switch PM9, respectively. The drain of the third P-type switch PM3 is connected with the drain of the fourth N-type switch NM4, the gate of the fifth N-type switch NM5, the gate of the sixth N-type switch NM6, and the drain of the tenth P-type switch PM10, respectively. The source of the ninth P-type switch PM9 is connected with the source of the tenth P-type switch PM10 and the drain of the fifth P-type switch PM5, respectively. The gate of the fourth P-type switch PM4 is connected with the gate of the fifth P-type switch PM5, the gate and the drain of the sixth P-type switch PM6, the gate of the eighth P-type switch PM8, and the drain of the fifth N-type switch NM5, respectively. The gate of the seventh P-type switch PM7 is connected with the drain of the eleventh P-type switch PM11 and the drain of the sixth N-type switch NM6, respectively. The drain of the seventh P-type switch PM7 is connected with the source of the eleventh P-type switch PM11. The gate of the eleventh P-type switch PM11 is connected with the gate of the twelfth P-type switch PM12. The source of the twelfth P-type switch PM12 is connected with the drain of the eighth P-type switch PM8. The gate of the ninth P-type switch PM9 is connected with the source of the thirteenth P-type switch PM13 and the first end of the second resistor R2, respectively. The gate of the tenth P-type switch PM10 is connected with the first end of the third resistor R3 and the first end of the fourth resistor R4, respectively. The second end of the third resistor R3 is connected with the source of the fourteenth P-type switch PM14. A connection point between the drain of the twelfth P-type switch PM12, the second end of the second resistor R2, and the second end of the fourth resistor R4 is connected with a reference voltage generating sub-module.

[0127] The third analog ground AVSS3 is connected with the source of the second N-type switch NM2, the source of the third N-type switch NM3, the source of the fourth N-type switch NM4, the source of the fifth N-type switch NM5, the source of the sixth N-type switch NM6, the gate and the drain of the thirteenth P-type switch PM13, and the gate and the drain of the fourteenth P-type switch PM14, respectively.

[0128] In some embodiments, as Figure 7As shown, this bandgap reference submodule utilizes the virtual short characteristic of the operational amplifier to perform voltage clamping on the connection point between the first terminal of the third resistor R3, the first terminal of the fourth resistor R4, the source of the thirteenth P-type switch PM13, and the connection point between the first terminal of the second resistor R2. This can generate a positive temperature coefficient voltage ΔV across the third resistor R3. BE Then, the voltage V across the fourteenth P-type switching transistor PM14 is added. BE2 The voltage across the fourth resistor R4 ultimately outputs an initial reference voltage of 1.2V to the reference voltage generation submodule, resulting in an output voltage V. out The expression is as follows:

[0129]

[0130] Among them, V BE It is a quantity with a negative temperature coefficient, V T It is a quantity with a positive temperature coefficient. As long as n' and the resistance values ​​of the third resistor R3 and the fourth resistor R4 are set properly, an initial reference voltage with a zero temperature coefficient can be generated.

[0131] It should be noted that, Figure 7 The bandgap reference submodule shown does not have an additional bias circuit; it achieves self-biasing using a loop. Attention should be paid to the startup process of this bandgap reference submodule. Upon power-up, since there is no current in the circuit, the fourth P-type switch PM4 is off. At this time, the gate voltages of the second P-type switch PM2 and the third P-type switch PM3 are pulled low by the second N-type switch NM2, thus turning them on. Current flows from the second P-type switch PM2 and the third P-type switch PM3 into the load transistors of the op-amp, the third N-type switch NM3 and the fourth N-type switch NM4. As the drain voltage of the fourth N-type switch NM4 gradually increases, the current in the branch of the fifth N-type switch NM5 slowly increases and is mirrored through the sixth P-type switch PM6 to the branches of the fourth P-type switch PM4, the fifth P-type switch PM5, and the eighth P-type switch PM8. The entire bandgap reference circuit gradually starts working and eventually stabilizes in a normal operating state. When the circuit is stable, the fourth P-type switch PM4 pulls up the gate voltage of the second P-type switch PM2 and the third P-type switch PM3, thereby shutting down the startup circuit.

[0132] According to some embodiments, Figure 8 This is a schematic diagram of a reference voltage generation circuit provided in an embodiment of this disclosure. Figure 8As shown, the reference voltage generating sub-module includes at least one reference voltage generating circuit, and the reference voltage generating circuit includes a fourth analog power supply AVDD4, a fourth analog ground AVSS4, an operational amplifier Amp, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a third capacitor C3, a fourth capacitor C4, and a fifteenth P-type switch PM15; wherein

[0133] A first end of the fifth resistor R5 is connected to the bandgap reference module, a second end of the fifth resistor R5 is connected to a positive input end of the operational amplifier Amp and a first end of the third capacitor C3 respectively, an output end of the operational amplifier Amp is connected to a gate of the fifteenth P-type switch PM15 and a first end of the sixth resistor R6 respectively, a second end of the sixth resistor R6 is connected to a first end of the fourth capacitor C4, a second end of the fourth capacitor C4 is connected to a drain of the fifteenth P-type switch PM15 and a first end of the seventh resistor R7 respectively, a source of the fifteenth P-type switch PM15 is connected to the fourth analog power supply AVDD4, a second end of the seventh resistor R7 is connected to a negative input end of the operational amplifier Amp and a first end of the eighth resistor R8 respectively, and a connection point between the second end of the eighth resistor R8 and the ninth resistor R9 is connected to the pipeline module.

[0134] A second end of the third capacitor C3 and a second end of the ninth resistor R9 are connected to the fourth analog ground AVSS4.

[0135] In some embodiments, the output voltage of the bandgap reference sub-module is input to the operational amplifier Amp after being filtered by an RC low-pass filter, so as to reduce noise interference in the output voltage of the bandgap reference sub-module.

[0136] In some embodiments, the required different reference voltages can be generated at the connection point between the second end of the eighth resistor R8 and the ninth resistor R9 by using the operational amplifier Amp to clamp the generated reference current.

[0137] It should be noted that the second end of the seventh resistor R7 and the negative input end of the operational amplifier Amp can also be connected to a first end of a resistor string, and a second end of the resistor string is connected to the fourth analog ground AVSS4, and the resistor string includes a plurality of sub-resistors connected in series. In this case, different reference voltages are generated at the connection points between every two sub-resistors in the resistor string, and in this case, only one reference voltage generating circuit needs to be set.

[0138] According to some embodiments, the operational amplifier can adopt a Low Dropout Regulator (LDO) structure. The LDO structure has two types of N-type and P-type.

[0139] In some embodiments, in the case that the output voltage of the bandgap reference sub-module is large, the N-type switch tube is selected as the input tube in the operational amplifier, and based on the consideration of noise, gain, power suppression and the like, the operational amplifier can adopt a sleeve type cascode structure, if the feedback switch tube adopts the N-type switch tube, the source stage is grounded, and in the low-power design in which the static current needs to be reduced as much as possible, the gate-source voltage of the switch tube needs to be compressed as much as possible, and the threshold voltage Vth of the N-type switch tube under the current process is about 0.5V, that is, the output of the operational amplifier is constrained at 0.5-0.6V, so that the voltage margin of the tail current source tube, the input tube and the cascode of the operational amplifier is compressed, and problems may exist under different process angles, and when the feedback switch tube adopts the P-type switch tube, the problem can be avoided, and 0.5V is allocated to the current source load and the cascode, which is acceptable, therefore, the operational amplifier of the embodiment of the present disclosure can select the P-type LDO structure.

[0140] In some embodiments, Figure 9 A structural schematic diagram of an operational amplifier provided by the embodiment of the present disclosure is shown in FIG. 1. Figure 9 As shown in FIG. 1, the operational amplifier includes a fifth analog power supply AVDD5, a fifth analog ground AVSS5, a sixteenth P-type switch tube PM16, a seventeenth P-type switch tube PM17, an eighteenth P-type switch tube PM18, a nineteenth P-type switch tube PM19, a twentieth P-type switch tube PM20, a twenty-first P-type switch tube PM21, a twenty-second P-type switch tube PM22, a twenty-third P-type switch tube PM23, a twenty-fourth P-type switch tube PM24, a seventh N-type switch tube NM7, an eighth N-type switch tube NM8, a ninth N-type switch tube NM9, a tenth N-type switch tube NM10, an eleventh N-type switch tube NM11, a twelfth N-type switch tube NM12, a thirteenth N-type switch tube NM13, a fourteenth N-type switch tube NM14, a fifteenth N-type switch tube NM15, a sixteenth N-type switch tube NM16, and a seventeenth N-type switch tube NM17.

[0141] The fifth analog power supply AVDD5 is connected with the gate and drain of the seventh N-type switch tube NM7, the gate of the eighth N-type switch tube NM8, the gate of the ninth N-type switch tube NM9, the gate of the tenth N-type switch tube NM10, the source of the sixteenth P-type switch tube PM16, the source of the seventeenth P-type switch tube PM17, the source of the eighteenth P-type switch tube PM18, the source of the nineteenth P-type switch tube PM19, and the source of the twentieth P-type switch tube PM20.

[0142] The gate of the sixteenth P-type switch tube PM16 and the gate of the nineteenth P-type switch tube PM19 are connected, the drain of the sixteenth P-type switch tube PM16 and the source of the twenty-first P-type switch tube PM21 are connected, the drain of the twenty-first P-type switch tube PM21 and the drain of the eighth N-type switch tube NM8 are connected, the gate of the twenty-first P-type switch tube PM21 is connected with the gate of the seventeenth P-type switch tube PM17, the gate and the drain of the twenty-second P-type switch tube PM22, and the drain of the ninth N-type switch tube NM9 respectively, the drain of the seventeenth P-type switch tube PM17 and the source of the twenty-second P-type switch tube PM22 are connected, the gate of the eighteenth P-type switch tube PM18 is connected with the gate of the twentieth P-type switch tube PM20, the drain of the twenty-third P-type switch tube PM23, and the drain of the eleventh N-type switch tube NM11 respectively, the drain of the eighteenth P-type switch tube PM18 and the source of the twenty-third P-type switch tube PM23 are connected, the drain of the twentieth P-type switch tube PM20 and the source of the twenty-fourth P-type switch tube PM24 are connected, the gate of the twenty-third P-type switch tube PM23 and the gate of the twenty-fourth P-type switch tube PM24 are connected, the gate of the eleventh N-type switch tube NM11 is connected with the gate of the twelfth N-type switch tube NM12, the gate of the thirteenth N-type switch tube NM13, the gate of the fourteenth N-type switch tube NM14, and the gate of the fifteenth N-type switch tube NM15 respectively, the drain of the nineteenth P-type switch tube PM19 and the drain of the thirteenth N-type switch tube NM13 are connected, the source of the thirteenth N-type switch tube NM13 and the drain of the fourteenth N-type switch tube NM14 are connected, the source of the fourteenth N-type switch tube NM14 and the drain of the fifteenth N-type switch tube NM15 are connected, the source of the fifteenth N-type switch tube NM15 is connected with the source of the sixteenth N-type switch tube NM16, the source of the seventeenth N-type switch tube NM17, and the drain of the tenth N-type switch tube NM10 respectively, the source of the eleventh N-type switch tube NM11 and the drain of the sixteenth N-type switch tube NM16 are connected, the source of the twelfth N-type switch tube NM12 and the drain of the seventeenth N-type switch tube NM17 are connected;

[0143] The connection point between the drain of the twenty-fourth P-type switch tube PM24 and the drain of the twelfth N-type switch tube NM12 is the output end of the operational amplifier, the gate of the sixteenth N-type switch tube NM16 is the positive output end of the operational amplifier, and the gate of the seventeenth N-type switch tube NM17 is the negative output end of the operational amplifier;

[0144] The source of the seventh N-type switch tube NM7, the source of the eighth N-type switch tube NM8, the source of the ninth N-type switch tube NM9, and the source of the tenth N-type switch tube NM10 are connected with the fifth analog ground AVSS5.

[0145] It should be noted that the first analog power supply AVDD1 to the sixth analog power supply AVDD6 in the above embodiment may, for example, adopt the same analog power supply with the same power supply voltage, or may separately adopt analog power supplies with different power supply voltages. The first analog ground AVSS1 to the sixth analog ground AVSS6 may, for example, adopt the same analog ground, or may separately adopt different analog grounds.

[0146] It should be noted that the switch tubes in the above embodiment, including the first P-type switch tube PM1 to the thirty-second P-type switch tube PM32, the first N-type switch tube NM1 to the twenty-eighth N-type switch tube NM28, include but are not limited to Bipolar Junction Transistor (BJT), Gate Turn-off Thyristor (GTO), Insulated Gate Bipolar Transistor (IGBT), Integrated Gate Commuted Transistor (IGCT), and Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET, MOS), and the like.

[0147] Taking one scenario as an example, a model of an analog-to-digital conversion ADC circuit is built, an input signal close to the Nyquist frequency is input under a sampling rate of 250 MHz, and after importing non-ideal factors such as limited gain, bandwidth, noise comparator offset, and the like shown in Figure 10 the model simulation result obtained by using Fast Fourier Transform (FFT) analysis is as shown in Figure 11 It can be seen from the simulation result that the analog-to-digital conversion ADC circuit provided in the embodiment of the present disclosure can meet the high performance requirement.

[0148] In summary, the analog-to-digital conversion ADC circuit provided in the embodiment of the present disclosure, by compromising the power consumption, accuracy, design difficulty and the like of the pipeline module, sets the effective accuracy of the first pipeline module (Stage 1) to two bits, and sets the first pipeline module (Stage 1) to 2.5 bit quantization, which can take into account the power consumption, accuracy, design difficulty and the like of the pipeline type ADC when designing the first stage pipeline module.

[0149] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In the specification, the illustrative expression of the above terms can be directed to different embodiments or examples. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments or examples. In addition, a person skilled in the art can combine and combine different embodiments or examples described in the specification and the features of different embodiments or examples without contradiction.

[0150] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise explicitly specified.

[0151] Although the embodiments of the present disclosure have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, replacements and variations can be made to the embodiments without departing from the principles and spirit of the present disclosure, and the scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. An analog-to-digital converter (ADC) circuit, characterized in that, include: N cascaded pipeline modules, where N is a positive integer; The effective precision of the first pipeline module is two bits, and the first pipeline module is set to 2.5-bit quantization.

2. The analog-to-digital converter (ADC) circuit according to claim 1, characterized in that, When N is 11, the effective precision of the 2nd and 11th pipeline modules is two bits, the effective precision of the 3rd to 10th pipeline modules is one bit, the 2nd pipeline module is set to 2.5-bit quantization, the 3rd to 10th pipeline modules are all set to 1.5-bit quantization, and the 11th pipeline module is set to 2-bit quantization.

3. The analog-to-digital converter (ADC) circuit according to claim 1, characterized in that, The pipeline module adopts a data acquisition-protection-free structure, and the analog-to-digital converter (ADC) circuit further includes a clock generation module and a reference module; wherein... The clock generation module is used to generate multi-phase non-overlapping clock signals and input the multi-phase non-overlapping clock signals to each of the N cascaded pipeline modules. The reference module is used to generate at least one reference voltage and input the at least one reference voltage to each of the N cascaded pipeline modules; The N cascaded pipeline modules convert the received analog signals into digital signals based on the multiphase non-overlapping clock signals and the at least one reference voltage.

4. The analog-to-digital converter (ADC) circuit according to claim 3, characterized in that, The clock generation module includes a clock buffer submodule and a non-overlapping clock generation submodule; wherein... The clock buffer submodule is used to convert the initial clock signal into a target clock signal, wherein the duty cycle of the target clock signal is greater than a duty cycle threshold, and the clock jitter of the target clock signal is lower than a jitter threshold. The non-overlapping clock generation submodule is used to convert the target clock signal into a multi-phase non-overlapping clock signal and input the multi-phase non-overlapping clock signal to each of the N cascaded pipeline modules.

5. The analog-to-digital converter (ADC) circuit according to claim 4, characterized in that, The clock buffer submodule includes a waveform conversion submodule and a shaping output submodule; wherein... The waveform conversion submodule is used to receive the initial clock signal and convert the initial clock signal into an initial square wave signal; The shaping output submodule is used to shape the initial square wave signal to obtain and output the target clock signal to the non-overlapping clock generation submodule.

6. The analog-to-digital converter (ADC) circuit according to claim 5, characterized in that, The initial clock signal includes a first sine wave signal and a second sine wave signal that are differentially expressed. The waveform conversion submodule includes a first analog power supply, a first analog ground, a first amplifier, a first capacitor, a second capacitor, a first resistor, a first P-type switch, and a first N-type switch. The shaping output submodule includes a second analog power supply, a first inverter, a second inverter, and a second analog ground. The positive input terminal of the first amplifier receives the first sine wave signal, and the positive output terminal of the first amplifier receives the second sine wave signal. The power supply terminal of the first amplifier is connected to the first analog power supply, and the ground terminal of the first amplifier is connected to the first analog ground. The output terminal of the first amplifier is connected to the first terminal of the first capacitor. The second terminal of the first capacitor is connected to the first terminal of the second capacitor, the first terminal of the first resistor, the gate of the first P-type switch, and the gate of the first N-type switch. The second terminal of the second capacitor and the source of the first N-type switch are connected to the second analog ground. The source of the first P-type switch is connected to the second analog power supply. The drain of the first P-type switch is connected to the second terminal of the first resistor, the drain of the first N-type switch, and the input terminal of the first inverter. The output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the non-overlapping clock generation submodule.

7. The analog-to-digital converter (ADC) circuit according to claim 3, characterized in that, The reference module includes a bandgap reference submodule and a reference voltage generation submodule; wherein... The bandgap reference submodule is used to generate an initial reference voltage; The reference voltage generation submodule is used to convert the initial reference voltage into at least one reference voltage and input the at least one reference voltage to each of the N cascaded pipeline modules.

8. The analog-to-digital converter (ADC) circuit according to claim 7, characterized in that, The bandgap reference submodule includes a third analog power supply, a third analog ground, a second P-type switch, a third P-type switch, a fourth P-type switch, a fifth P-type switch, a sixth P-type switch, a seventh P-type switch, an eighth P-type switch, a ninth P-type switch, a tenth P-type switch, an eleventh P-type switch, a twelfth P-type switch, a thirteenth P-type switch, a fourteenth P-type switch, a second N-type switch, a third N-type switch, a fourth N-type switch, a fifth N-type switch, a sixth N-type switch, a second resistor, a third resistor, and a fourth resistor; wherein, The third analog power supply is connected to the source of the second P-type switch, the source of the third P-type switch, the source of the fourth P-type switch, the source of the fifth P-type switch, the source of the sixth P-type switch, the source of the seventh P-type switch, and the source of the eighth P-type switch, respectively. The gate of the second P-type switch is connected to the gate of the third P-type switch, the drain of the fourth P-type switch, and the drain of the second N-type switch. The gate of the second N-type switch receives an enable signal. The drain of the second P-type switch is connected to the gate and drain of the third N-type switch, the gate of the fourth N-type switch, and the drain of the ninth P-type switch. The drain of the third P-type switch is connected to the drain of the fourth N-type switch, the gate of the fifth N-type switch, the gate of the sixth N-type switch, and the drain of the tenth P-type switch. The source of the ninth P-type switch is connected to the source of the tenth P-type switch and the drain of the fifth P-type switch. The gate of the fourth P-type switch is connected to the gate of the fifth P-type switch, the gate and drain of the sixth P-type switch, the gate of the eighth P-type switch, and the drain of the fifth P-type switch. The drain of the N-type switch is connected. The gate of the seventh P-type switch is connected to the drain of the eleventh P-type switch and the drain of the sixth N-type switch. The drain of the seventh P-type switch is connected to the source of the eleventh P-type switch. The gate of the eleventh P-type switch is connected to the gate of the twelfth P-type switch. The source of the twelfth P-type switch is connected to the drain of the eighth P-type switch. The gate of the ninth P-type switch is connected to the source of the thirteenth P-type switch and the first terminal of the second resistor. The gate of the tenth P-type switch is connected to the first terminal of the third resistor and the first terminal of the fourth resistor. The second terminal of the third resistor is connected to the source of the fourteenth P-type switch. The connection point between the drain of the twelfth P-type switch, the second terminal of the second resistor, and the second terminal of the fourth resistor is connected to the reference voltage generation submodule. The third analog ground is connected to the source of the second N-type switch, the source of the third N-type switch, the source of the fourth N-type switch, the source of the fifth N-type switch, the source of the sixth N-type switch, the gate and drain of the thirteenth P-type switch, and the gate and drain of the fourteenth P-type switch, respectively.

9. The analog-to-digital converter (ADC) circuit according to claim 7, characterized in that, The reference voltage generation submodule includes at least one reference voltage generation circuit, which includes a fourth analog power supply, a fourth analog ground, an operational amplifier, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a third capacitor, a fourth capacitor, and a fifteenth P-type switching transistor; wherein, The first end of the fifth resistor is connected to the bandgap reference module. The second end of the fifth resistor is connected to the positive input terminal of the operational amplifier and the first end of the third capacitor. The output terminal of the operational amplifier is connected to the gate of the fifteenth P-type switch and the first end of the sixth resistor. The second end of the sixth resistor is connected to the first end of the fourth capacitor. The second end of the fourth capacitor is connected to the drain of the fifteenth P-type switch and the first end of the seventh resistor. The source of the fifteenth P-type switch is connected to the fourth analog power supply. The second end of the seventh resistor is connected to the negative input terminal of the operational amplifier and the first end of the eighth resistor. The connection point between the second end of the eighth resistor and the ninth resistor is connected to the pipeline module. The second terminal of the third capacitor and the second terminal of the ninth resistor are connected to the fourth analog ground.

10. The analog-to-digital converter (ADC) circuit according to claim 9, characterized in that, The operational amplifier includes a fifth analog power supply, a fifth analog ground, and sixteenth P-type switching transistors, seventeenth P-type switching transistors, eighteenth P-type switching transistors, nineteenth P-type switching transistors, twentieth P-type switching transistors, twenty-first P-type switching transistors, twenty-second P-type switching transistors, twenty-third P-type switching transistors, twenty-fourth P-type switching transistors, seventh N-type switching transistors, eighth N-type switching transistors, ninth N-type switching transistors, tenth N-type switching transistors, eleventh N-type switching transistors, twelfth N-type switching transistors, thirteenth N-type switching transistors, fourteenth N-type switching transistors, fifteenth N-type switching transistors, sixteenth N-type switching transistors, and seventeenth N-type switching transistors; wherein, The fifth analog power supply is connected to the gate and drain of the seventh N-type switch, the gate of the eighth N-type switch, the gate of the ninth N-type switch, the gate of the tenth N-type switch, the source of the sixteenth P-type switch, the source of the seventeenth P-type switch, the source of the eighteenth P-type switch, the source of the nineteenth P-type switch, and the source of the twentieth P-type switch, respectively. The gate of the sixteenth P-type switch is connected to the gate of the nineteenth P-type switch. The drain of the sixteenth P-type switch is connected to the source of the twenty-first P-type switch. The drain of the twenty-first P-type switch is connected to the drain of the eighth N-type switch. The gate of the twenty-first P-type switch is connected to the gate of the seventeenth P-type switch, the gate and drain of the twenty-second P-type switch, and the drain of the ninth N-type switch. The drain of the seventeenth P-type switch is connected to the source of the twenty-second P-type switch. The gate of the eighteenth P-type switch is connected to the gate of the twentieth P-type switch, the drain of the twenty-third P-type switch, and the drain of the eleventh N-type switch. The drain of the eighteenth P-type switch is connected to the source of the twenty-third P-type switch. The drain of the twentieth P-type switch is connected to the source of the twenty-fourth P-type switch. The gate of the 23P-type switch is connected to the gate of the 24th P-type switch. The gate of the 11th N-type switch is connected to the gates of the 12th N-type switch, the 13th N-type switch, the 14th N-type switch, and the 15th N-type switch. The drain of the 19th P-type switch is connected to the drain of the 13th N-type switch. The source of the 13th N-type switch is connected to the drain of the 14th N-type switch. The source of the 14th N-type switch is connected to the drain of the 15th N-type switch. The source of the 15th N-type switch is connected to the sources of the 16th N-type switch, the 17th N-type switch, and the 10th N-type switch. The source of the 11th N-type switch is connected to the drain of the 16th N-type switch. The source of the 12th N-type switch is connected to the drain of the 17th N-type switch. The connection point between the drain of the 24th P-type switch and the drain of the 12th N-type switch is the output terminal of the operational amplifier, the gate of the 16th N-type switch is the positive output terminal of the operational amplifier, and the gate of the 17th N-type switch is the negative output terminal of the operational amplifier. The source of the seventh N-type switch, the source of the eighth N-type switch, the source of the ninth N-type switch, and the source of the tenth N-type switch are connected to the fifth analog ground.

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