Three-dimensional 1S1C memory and preparation method thereof
By introducing a columnar capacitor structure and an independent gate transistor functional layer into the three-dimensional 1S1C memory, the problems of complex fabrication process and high cost are solved, and high-density storage effect is achieved.
Patent Information
- Application Number
- CN202511193397.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-25
- Publication Date
- 2025-11-18
AI Technical Summary
Existing 3D 1S1C memory suffers from problems such as complex fabrication processes, high costs, difficulties in interlayer alignment, and insufficient storage capacity, which limit its industrial application.
By adopting a columnar capacitor structure and introducing a second and a third metal electrode layer as capacitor electrodes in the memory cell, the effective contact area of the capacitor electrodes is increased and the fabrication process is simplified. The use of a columnar capacitor structure and an independent gate transistor functional layer simplifies the etching process of the multilayer structure.
This improved the capacitance stability of the storage capacitor, reduced the manufacturing cost, simplified the process, and enabled the fabrication of a high-density three-dimensional 1S1C memory.
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Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the technical field of memory, and more particularly relates to a three-dimensional 1S1C memory and a preparation method. BACKGROUND
[0002] With the rapid development of big data, artificial intelligence, 5G communication and other technologies, the global data volume is growing exponentially, and it is predicted that the global data volume will reach 175 ZB in 2025. As the core component of data storage and processing, the performance (capacity, speed, power consumption, reliability) of the memory directly determines the upper limit of the terminal device (such as a smart phone, a server, an AI chip). Due to the low area utilization rate (unit chip area capacity ≤ 100 Gb) and scaling bottleneck, the traditional planar memory (such as 2D DRAM, 2D NAND) has been unable to meet the demand for high capacity and low power consumption.
[0003] Three-dimensional memory breaks through the capacity limit of planar structure by vertically stacking storage units, and becomes the mainstream direction of current memory technology. Among them, 1S1C refers to 1 select transistor and 1 storage capacitor, and its structure is the classic architecture of DRAM, FeRAM and other memories, which has the advantages of high integration, low power consumption and fast read-write speed, and is an important research branch of three-dimensional memory. The current three-dimensional 1S1C memory scheme proposed by the industry is to use a crossbar structure. With each additional layer of storage unit, a hole-shaped structure needs to be etched and filled with a functional layer (storage capacitor unit and select transistor unit) in the hole-shaped structure, which will introduce the problems of inaccurate precision and high cost caused by multiple etching. With the increase of the number of stacked layers, the cost will be greatly increased. Therefore, the implementation of three-dimensional 1S1C memory based on the crossbar structure has the problems of complex process, and the cost will be greatly increased with the increase of the number of layers, which limits the theoretical number of stacked layers of three-dimensional 1S1C memory.
[0004] The vertical integration and device performance of the existing three-dimensional 1S1C memory still have problems such as interlayer alignment difficulty, insufficient storage capacitor capacity due to size miniaturization, and complex preparation process, which seriously restricts its industrial application. In order to better solve the existing problems and fully exploit the advantages of 1S1C memory in easy three-dimensional stacking to achieve high-density storage, it is urgent to propose an easy-to-implement three-dimensional 1S1C memory structure and a preparation method. SUMMARY
[0005] In view of the defects of the prior art and the demand for improvement, the present application provides a three-dimensional 1S1C memory and a preparation method, which aims to simplify the preparation process of the three-dimensional memory, reduce the preparation cost, and increase the effective contact area of the capacitor electrode through a columnar capacitor structure, thereby improving the capacity stability of the storage capacitor.
[0006] To achieve the above-mentioned purpose, according to one aspect of the present application, a three-dimensional 1S1C memory is provided, comprising: a peripheral electrode layer and a storage unit. The peripheral electrode layer is formed on a substrate, and first dielectric layers and first metal electrode layers are alternately stacked in sequence from bottom to top, with the topmost layer and the bottommost layer being first dielectric layers. The peripheral electrode layer is provided with a plurality of trenches penetrating in the vertical direction, each trench being parallel to each other, and the bottom of the trench being located in the substrate, the trench being used to divide the first metal electrode layer, and each layer of the first metal electrode layer being divided into a plurality of independent strip-shaped electrodes by the trench, the strip-shaped electrode being a word line of the memory. The peripheral electrode layer is provided with a plurality of holes penetrating in the vertical direction in structure, the holes being arranged in an array, and the holes extending to the first dielectric layer of the bottommost layer. The storage unit comprises a second metal electrode layer, a second dielectric layer, a third metal electrode layer, and a select gate functional layer, wherein each hole is inwardly recessed at the place where it contacts each layer of the first metal electrode layer; a layer of the second metal electrode layer is uniformly covered on the inner wall of the inwardly recessed place of the hole, the second metal electrode layer is also inwardly recessed correspondingly, and the second metal electrode layer formed at the inwardly recessed place of each hole is independent of each other; a second dielectric layer is formed on the surface formed by the second metal electrode layer and the inner wall of the hole which is not inwardly recessed; a third metal electrode layer is formed on the surface of the second dielectric layer which is inwardly recessed, and the third metal electrode layer formed in each hole is independent of each other; a select gate functional layer is formed on the surface of the third metal electrode layer, and the select gate functional layer formed in each hole is independent of each other; a fourth metal electrode layer is formed on the surface formed by the select gate functional layer and the second dielectric layer, the top of the fourth metal electrode layer extends to the surface of the first dielectric layer of the topmost layer to form a bit line electrode, the bit line electrode is connected with a bit line, the bottom of the fourth metal electrode layer is lower than the first metal electrode layer in the bottommost layer in the vertical direction, and the area opposite to the first metal electrode layer of the fourth metal electrode layer constitutes a storage unit.
[0007] The present application also discloses a preparation method of the above-mentioned three-dimensional 1S1C memory, comprising: S1: alternately growing first dielectric layers and first metal electrode layers on a substrate, the number of layers of the first metal electrode layers being the same as the number of layers of storage units in the three-dimensional 1S1C memory; S2: etching to form a plurality of vertically penetrating holes, the holes being arranged in an array, the holes extending to at least the bottommost first dielectric layer; S3: etching the first metal electrode layer in the holes, leaving a plurality of longitudinal annular grooves on the sidewalls of the holes, the number of grooves in each hole being the same as the number of layers of the first metal electrode layer; S4: forming a second metal electrode layer on the inner walls of each groove in the holes, as one electrode of the capacitor, the second metal electrode layer film being recessed at the grooves produced in step S3, each second metal electrode layer being independent of each other; S5: forming a second dielectric layer on the surface formed by the inner walls of the holes not recessed inwardly and the second metal electrode layer, as a dielectric layer of the capacitor; S6: forming a third metal electrode layer on the surface of the second dielectric layer recessed inwardly, as the other electrode of the capacitor, each third metal electrode layer being independent of each other; S7: forming a gate function layer on the surface of the third metal electrode layer, each gate function layer being independent of each other; S8: forming a fourth metal electrode layer on the surface formed by the gate function layer and the second dielectric layer, the top of the fourth metal electrode layer extending to the surface of the topmost first dielectric layer to form a bit line electrode, the bit line electrode being connected to a bit line; S9: performing multiple etching on the edge of the three-dimensional 1S1C memory to expose each layer of the first metal electrode layer, forming a plurality of electrode steps; S10: etching to form a plurality of vertically penetrating trenches between different holes, the trenches being parallel to each other, and the bottom of the trenches being located in the substrate, the trenches dividing the peripheral electrode layer into a plurality of independent strip-shaped parts as word lines of the three-dimensional 1S1C memory.
[0008] Overall, the above technical solutions conceived by the present application can achieve the following beneficial effects: The various layers of thin films constituting the storage unit achieve columnar three-dimensional contact through the upper surface, the lower surface and the annular side surface, significantly increasing the effective contact area of the capacitor electrodes, such as the second metal electrode layer and the third metal electrode layer. This design effectively compensates for the area decay problem of the capacitor electrodes caused by size shrinkage at advanced process nodes, ensuring the stability of the storage capacitor capacity.
[0009] The first metal electrode layer for etching of the multi-layer structure is usually not well matched with the interface of the second dielectric layer, affecting the reliability of the device. However, electrode materials that are well matched with the interface of the second dielectric layer are difficult to etch with high aspect ratio. Therefore, the introduction of the second metal electrode layer can increase the surface area of the capacitor and improve the reliability of the capacitor.
[0010] In the three-dimensional 1S1C memory provided by the present application, the second metal electrode layer and the third metal electrode layer serve as the two electrodes of the capacitor. Since the two electrodes of the capacitor are deposited after the first dielectric layer and the first metal electrode layer are alternately stacked, compared with the existing structure in which the stacked first metal electrode layer directly serves as the electrode of the capacitor, such as the word line and capacitor electrode design of the conventional 3D DRAM, the capacitor electrode material of the present application does not need to be limited to the material of the first metal electrode layer (such as tungsten, titanium nitride), and can be freely selected according to the performance requirements of the capacitor conductivity, migration resistance and the like, and the degree of freedom of material selection is significantly improved. BRIEF DESCRIPTION OF DRAWINGS
[0011] Figure 1 is a three-dimensional 1S1C memory structure diagram provided by an embodiment of the present application. Figure 2 is a schematic diagram of the trench structure of the three-dimensional 1S1C memory provided by the embodiment of the present application. Figure 3 is a preparation flowchart of the memory cell of the three-dimensional 1S1C memory provided by the embodiment of the present application.
[0012] Figure 1 In the figure, 1 is the first metal electrode layer, 2 is the first dielectric layer, 3 is the second metal electrode layer, 4 is the second dielectric layer, 5 is the third metal electrode layer, 6 is the gate function layer, and 7 is the fourth metal electrode layer. DETAILED DESCRIPTION
[0013] In order to make the purpose, technical scheme and advantages of the present application clearer and more apparent, the present application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application. In addition, the technical features involved in each embodiment of the present application described below can be combined with each other as long as there is no conflict.
[0014] In the present application, the terms "first", "second", etc. (if any) in the present application and the drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence.
[0015] Embodiment 1: Figure 1 is a three-dimensional 1S1C memory structure diagram provided by an embodiment of the present application. Figure 1 In combination with Figure 2The three-dimensional 1S1C memory includes a peripheral electrode layer and a memory cell. The peripheral electrode layer is formed on a substrate, and a first metal electrode layer 1 and a first dielectric layer 2 are alternately stacked in sequence from bottom to top, wherein the bottom layer and the top layer are both the first dielectric layer 2. A plurality of trenches penetrating in the vertical direction are arranged on the peripheral electrode layer, the trenches are parallel to each other, and the bottom of the trench is located in the substrate. The trenches are used to divide the first metal electrode layer. Each layer of the first metal electrode layer 1 is divided into a plurality of independent strip electrodes by the trenches, and each strip electrode serves as a word line of the three-dimensional 1S1C memory. The peripheral electrode layer is also provided with a plurality of holes penetrating in the vertical direction, and the holes are arranged in an array. The holes extend to the bottommost first dielectric layer 2. The memory cell includes a second metal electrode layer 3, a second dielectric layer 4, a third metal electrode layer 5, and a select gate functional layer 6. Each hole is inwardly recessed at the place where it contacts each layer of the first metal electrode layer 1. A layer of the second metal electrode layer 3 is uniformly covered on the inner wall of the inwardly recessed place of the hole. The second metal electrode layer 3 is also inwardly recessed correspondingly, and the second metal electrode layer 3 formed in the inwardly recessed place of each hole is independent of each other. The second dielectric layer 4 is formed on the surface of the inner wall of the hole which is not inwardly recessed and the surface formed by the second metal electrode layer 3. The third metal electrode layer 3 is formed on the surface of the second dielectric layer 4 which is inwardly recessed. The third metal electrode layer 3 formed in each hole is independent of each other. The select gate functional layer 6 is formed on the surface of the third metal electrode layer 3. The select gate functional layer 6 formed in each hole is independent of each other. A fourth metal electrode layer is formed on the surface formed by the select gate functional layer and the second dielectric layer. The top of the fourth metal electrode layer extends to the surface of the topmost first dielectric layer to form a bit line electrode. The bit line electrode is connected to a bit line. The bottom of the fourth metal electrode layer is lower than the first metal electrode layer in the bottommost layer in the vertical direction. The area opposite to the first metal electrode layer of the fourth metal electrode layer constitutes a memory cell.
[0016] Further, as shown in Figure 1 each layer of film constituting the memory cell contacts the upper surface, the lower surface, and the annular side surface, i.e., the surfaces of the second metal electrode layer 3, the second dielectric layer 4, the third metal electrode layer 5, and the select gate functional layer 6 are in complete contact. The innermost layer is a columnar fourth metal electrode layer film, and the outward layers are in sequence a columnar select gate functional layer film, a third metal electrode layer film, a second dielectric layer film, and a second metal electrode layer film. The second metal electrode layer film is surrounded by the first metal electrode layer.
[0017] It should be noted that each memory cell formed in the same vertical hole shares the same fourth metal electrode as a bit line electrode, and all memory cells in the same strip electrode share the same word line electrode. The first dielectric layer and the first metal electrode layer alternately stacked with each other are periodically repeated in the vertical direction, and the number of repetitions is the same as the number of layers of the three-dimensional 1S1C memory storage unit. The gating tube functional layer material includes: OTS type material, conductive bridge type material, metal insulator transition type material, but is not limited thereto, and the OTS type material includes: a sulfur compound material, which has three main material systems: Se-based compound system, Te-based compound system and S-based compound system.
[0018] When operating the memory cells in the three-dimensional 1S1C memory, first, the corresponding word line and bit line are selected, and by applying a voltage to the word line and the bit line, a pressure difference is formed between the top electrode and the bottom electrode of the memory cell at the intersection of the word line and the bit line, so that the gating tube layer film region in the area opposite to the two electrodes is turned on, and then by charging and discharging the capacitor of the selected memory cell, the data writing and reading process is realized. The principle of operation of other memory cells is the same.
[0019] Further, in order to more clearly understand the positional relationship between each memory cell in the memory, Figure 2 A schematic diagram of the trench structure of the three-dimensional 1S1C memory according to an embodiment of the present application is provided. As shown in Figure 2 Between different holes, a trench is provided which penetrates in the vertical direction, each trench is parallel to each other, and the trench divides the first metal electrode layer into several independent strip electrodes. The strip electrode is used as the word line of the memory, and the strip electrode is used to control the adjacent memory cells. In other words, when a voltage is applied to the strip electrode and the fourth metal electrode layer, the gating tube of the memory cell at the intersection of the first and fourth metal electrode layers and the word line and bit line to which the voltage is applied is selected, and then the read and write control of the memory cell is realized. The trench is filled with insulating material to block the electrical connection of different word lines in the memory.
[0020] Embodiment 2: The present application also provides a preparation method of the three-dimensional 1S1C memory based on the above, comprising the following steps: S1: alternately growing a first dielectric layer and a first metal electrode layer on a substrate, the number of layers of the first metal electrode layer is the same as the number of layers of the memory cells in the three-dimensional 1S1C memory; S2: etching to form a plurality of vertical holes penetrating in the vertical direction, the holes are arranged in an array, and the bottom of the hole extends to at least the bottommost first dielectric layer; S3: etching the first metal electrode layer in the hole, leaving a plurality of longitudinal annular grooves on the sidewall of the hole, the number of grooves in each hole is the same as the number of layers of the first metal electrode layer; S4: forming the second metal electrode layer on the inner wall of each groove in the hole as one electrode of the capacitor, the second metal electrode layer film will form a recess at the groove generated in step S3, and each second metal electrode layer is independent of each other; S5: forming the second dielectric layer on the surface formed by the inner wall of the hole not recessed inwardly and the second metal electrode layer as the dielectric layer of the capacitor; S6: forming the third metal electrode layer on the surface of the second dielectric layer recessed inwardly as the other electrode of the capacitor, and each third metal electrode layer is independent of each other; S7: forming the gate function layer on the surface of the third metal electrode layer, and each gate function layer is independent of each other; S8: forming the fourth metal electrode layer on the surface formed by the gate function layer and the second dielectric layer, and the top of the fourth metal electrode layer extends to the surface of the topmost first dielectric layer to form a bit line electrode connected with the bit line; S9: etching the edge of the three-dimensional 1S1C memory multiple times to expose each layer of the first metal electrode layer and form a plurality of electrode steps; S10: etching to form a plurality of vertical grooves between different holes, the grooves are parallel to each other, and the bottom of the groove is located in the substrate, and the groove divides the peripheral electrode layer into a plurality of independent strip-shaped parts as the word line of the three-dimensional 1S1C memory. Further, the materials of the second metal electrode layer and the third metal electrode layer are any one of aluminum, silver, palladium, nickel, copper, platinum, gold, titanium, tungsten, or nitride or alloy combination thereof, such as titanium nitride, tungsten nitride, silver-palladium alloy.
[0021] Further, the method of depositing the dielectric layer, the metal electrode layer and the gate function layer includes but is not limited to atomic layer deposition, chemical vapor deposition, physical vapor deposition, etc., wherein the dielectric layer includes the first dielectric layer and the second dielectric layer, and the metal electrode layer includes the first metal electrode layer, the second metal electrode layer, the third metal electrode layer and the fourth metal electrode layer.
[0022] In an optional embodiment, the hole and groove structure is a square hole structure or a circular hole structure.
[0023] In order to better understand the preparation process of the three-dimensional 1S1C memory, Figure 3 The preparation flow chart of the storage unit of the three-dimensional 1S1C memory provided by the embodiment of the present application is shown in FIG. 1. Figure 3As shown in Figure a, a first dielectric layer and a first metal electrode layer are first alternately grown on the substrate. The number of layers depends on the number of layers in the three-dimensional 1S1C memory cell, where the bottom and top layers are the first dielectric layers. Figure 3 As shown in b, for Figure 3 The structure in section a is photolithographically etched to create cylindrical holes that penetrate the entire structure vertically. For example... Figure 3 As shown in Figure c, selective etching is performed on the first metal electrode layer, also known as the word lines of the memory, causing the word lines to be recessed inwards where they contact the holes. For example... Figure 3 As shown in diagram d, a second metal electrode layer is deposited inside the cavity as the bottom electrode of the capacitor. To prevent the bottom electrodes of capacitors from different memory cells from interconnecting, the second metal electrode layer deposited on the non-recessed portion of the cavity is etched, retaining only the bottom electrode material within the groove, thus making the bottom electrodes of capacitors from different memory cells independent of each other. Figure 3 As shown in Figure e, a second dielectric layer is deposited within the pores to serve as the capacitor's dielectric layer. To reduce the thickness of the capacitor's dielectric layer, a high-k dielectric material is selected. Specifically, high-k materials include, but are not limited to, nitrides, such as SiN, AlN, and TiN; metal oxides, primarily transition metal and lanthanide oxides, such as MgO, Al2O3, Ta2O5, TiO2, ZnO, ZrO2, HfO2, CeO2, Y2O3, and La2O3; nitrogen oxides, such as SiON and HfSiON; and perovskite phase oxides, such as PbZrxTi1-xO3 (PZT) and BaxSr1-xTiO3 (BST). Figure 3 As shown in figure f, a third metal electrode layer is deposited inside the hole as the top electrode of the capacitor. To prevent the top electrodes of capacitors in different memory cells from interconnecting, the third metal electrode layer deposited on the non-recessed portion of the hole is etched, retaining only the top electrode material within the groove, thus making the top electrodes of capacitors in different memory cells independent of each other. Figure 3 As shown in g, a gated transistor functional layer is deposited within the via. The material for this layer includes OTS-type materials, conductive bridge materials, and metal-insulator transition materials, all exhibiting threshold conductivity. Since the resistance of the gated transistor functional layer is relatively low compared to the capacitor dielectric layer, it is necessary to prevent interconnection between the gated transistor functional layers of different memory cells. The gated transistor functional layer deposited on the non-recessed portion of the via is etched, retaining only the layer within the recess, thus ensuring the independence of the gated transistor functional layers for different memory cells. For example... As shown in figure h, a fourth metal electrode layer is deposited within the holes to serve as the bit lines of the three-dimensional 1S1C memory. The bit lines need to extend to the surface of the topmost first dielectric layer, thereby completing the fabrication of the three-dimensional 1S1C memory cell.
[0024] The application can complete the preparation of all the memory cells of the three-dimensional memory by depositing all the word line electrode layers of the memory, performing one-time photoetching to etch a through hole in the word line electrode layer, then etching a first metal electrode layer in the hole to form a groove part, and further depositing a one-time capacitor layer, a gating tube layer and a bit line electrode layer in the groove, thus simplifying the preparation process of the three-dimensional memory, reducing the preparation cost, and theoretically enabling the stacking number to reach an unlimited number of layers; meanwhile, a columnar capacitor structure is obtained, which significantly increases the effective contact area of the capacitor electrode and improves the capacity stability of the storage capacitor.
[0025] Those skilled in the art will easily understand that the above description is only the preferred embodiment of the present application, and is not intended to limit the present application, and any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A three-dimensional 1S1C memory, characterized in that, include: Peripheral electrode layer and memory cell: The peripheral electrode layer is formed on the substrate, and the first dielectric layer and the first metal electrode layer are stacked alternately from bottom to top, with the top and bottom layers being the first dielectric layer; The peripheral electrode layer is provided with a number of vertically penetrating trenches, each trench being parallel to the others, and the bottom of each trench being located in the substrate. The trenches are used to divide the first metal electrode layer, and each first metal electrode layer is divided into a number of independent strip electrodes by the trenches. The strip electrodes are word lines of the memory. The outer electrode layer has several vertically penetrating holes arranged in an array, extending to the bottom first dielectric layer. The storage unit includes a second metal electrode layer, a second dielectric layer, a third metal electrode layer, and a gate transistor functional layer. Each hole is recessed inwards at the point of contact with the first metal electrode layer of each hole. A second metal electrode layer is uniformly covered on the inner wall of the recessed portion of the hole, and the second metal electrode layer also forms a corresponding inward recess, with each recessed portion of the second metal electrode layer being independent. A second dielectric layer is formed on the surface formed between the inner wall of the hole where it is not recessed and the second metal electrode layer. A third metal electrode layer is formed on the inwardly recessed surface of the second dielectric layer. The third metal electrode layers formed within the holes are independent of each other; a gate tube functional layer is formed on the surface of the third metal electrode layer, and the gate tube functional layers formed within each hole are independent of each other. A fourth metal electrode layer is formed on the surface formed by the gate tube functional layer and the second dielectric layer. The top of the fourth metal electrode layer extends to the surface of the top first dielectric layer to form a bit line electrode, which is connected to the bit line. The bottom of the fourth metal electrode layer is lower than the bottom first metal electrode layer in the vertical direction. The area where the fourth metal electrode layer and the first metal electrode layer are directly opposite each other constitutes a memory cell.
2. The three-dimensional 1S1C memory according to claim 1, characterized in that, The thin films of the memory cell are in contact with each other on the upper surface, lower surface and annular side; the innermost layer is a columnar fourth metal electrode layer film, and from the inside out are columnar gate functional layer film, third metal electrode layer film, second dielectric layer film and second metal electrode layer film, wherein the second metal electrode layer film is surrounded and wrapped by the first metal electrode layer.
3. The three-dimensional 1S1C memory according to claim 1, characterized in that, Each memory cell formed in the same vertical hole shares the same fourth metal electrode as the bit line electrode, and all memory cells located on the same strip electrode share the same word line electrode.
4. The three-dimensional 1S1C memory according to claim 1, characterized in that, The alternating stacked first dielectric layer and first metal electrode layer repeat periodically in the vertical direction, and the number of repetitions is the same as the number of layers in the three-dimensional 1S1C memory storage cell.
5. The three-dimensional 1S1C memory according to claim 1, characterized in that, The materials of the gate tube functional layer include: OTS-type materials, conductive bridge-type materials, and metal-insulator transformation materials.
6. The three-dimensional 1S1C memory according to claim 5, characterized in that, The OTS-type materials include: chalcogenide compound materials.
7. A method for fabricating a three-dimensional 1S1C memory based on any one of claims 1-6, characterized in that, Includes the following steps: S1: A first dielectric layer and a first metal electrode layer are alternately grown on the substrate, and the number of the first metal electrode layers is the same as the number of storage cells in the three-dimensional 1S1C memory. S2: Etching forms several vertical through holes arranged in an array, with the bottom of the holes extending at least to the bottommost first dielectric layer; S3: Etch the first metal electrode layer in the hole, leaving multiple longitudinal annular grooves on the sidewall of the hole. The number of grooves in each hole is the same as the number of layers of the first metal electrode layer. S4: A second metal electrode layer is formed on the inner wall of each groove in the hole, serving as an electrode of the capacitor. The second metal electrode layer film will form a depression at the groove generated in step S3. Each second metal electrode layer is independent of each other. S5: A second dielectric layer is formed on the surface formed by the inner wall of the hole (which is not recessed inward) and the second metal electrode layer, serving as the dielectric layer of the capacitor. S6: A third metal electrode layer is formed on the inwardly recessed surface of the second dielectric layer as another electrode of the capacitor. Each third metal electrode layer is independent of the others. S7: A gate tube functional layer is formed on the surface of the third metal electrode layer, and each gate tube functional layer is independent of the others. S8: A fourth metal electrode layer is formed on the surface formed by the gate tube functional layer and the second dielectric layer. The top of the fourth metal electrode layer extends to the surface of the top first dielectric layer to form a bit line electrode. The bit line electrode is connected to the bit line. S9: Multiple etchings are performed at the edge of the three-dimensional 1S1C memory to expose each first metal electrode layer, forming a multi-layer electrode step. S10: Several vertically penetrating trenches are etched between different holes. The trenches are parallel to each other and the bottom of the trenches is located in the substrate. The trenches divide the outer electrode layer into multiple independent strip-shaped parts, which serve as word lines of the three-dimensional 1S1C memory.
8. The preparation method according to claim 7, characterized in that, The materials of the second metal electrode layer and the third metal electrode layer include any one of aluminum, silver, palladium, nickel, copper, platinum, gold, titanium, tungsten, or their nitrides or alloy combinations.
9. The preparation method according to claim 7, characterized in that, Methods for depositing dielectric layers, metal electrode layers, and gate functional layers include atomic layer deposition, chemical vapor deposition, or physical vapor deposition, wherein the dielectric layer includes a first dielectric layer and a second dielectric layer, and the metal electrode layer includes a first metal electrode layer, a second metal electrode layer, a third metal electrode layer, and a fourth metal electrode layer.
10. The preparation method according to claim 7, characterized in that, The holes and grooves are either square or circular.