Gallium nitride power device and preparation method thereof

Abstract

The invention discloses a gallium nitride power device and a preparation method thereof, and relates to a power semiconductor device, in order to simplify a forming process of a multilayer field plate, the invention provides the gallium nitride power device which is provided with a plurality of dielectric layers rising in a step shape, and a step-shaped side edge is formed on the side surface of each dielectric layer; according to the method provided by the invention, no matter how many layers of the field plates are, field plate deposition only needs to be carried out once, etching can be carried out twice and two layers of field plates can be formed during photoetching each time, the number of layers of the field plates can be increased without increasing the complexity and cost of the process, and the manufacturing cost of the field plates can be reduced. The electric field distribution between the gate metal and the drain metal of the device is more uniform, and the breakdown voltage and the reliability of the device are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to a manufacturing method of a power semiconductor device, in particular a gallium nitride power device. BACKGROUND

[0002] Gallium nitride material has higher energy band gap, electron mobility, saturated electron velocity and breakdown field than silicon material. Gallium nitride high electron mobility transistor is a common gallium nitride power device, and is widely used in high frequency application fields such as radio frequency and microwave. An existing gallium nitride high electron mobility transistor structure is shown in Figure 1 The device is provided with a multi-layer independent field plate 102 beside the gate metal 101. The multi-layer independent field plate 102 mainly functions to reduce the electric field peak between the gate metal 101 and the drain metal 103, so that the electric field distribution is more uniform, and the breakdown voltage and reliability of the device are improved. As shown in Figure 2 The number of field plate layers 102 is inversely proportional to the maximum electric field between the gate and the drain, and the more the number of field plate layers, the lower the maximum electric field between the gate and the drain, and the higher the breakdown voltage and reliability of the device. Referring again to Figure 1 Each layer of field plate of the device needs to be deposited, photolithographed and etched separately, and the more the number of field plate layers, the more complex the process, and the higher the cost. SUMMARY

[0003] To solve the above-mentioned problems, the present application provides a gallium nitride power device, which comprises a substrate layer at the bottom, a buffer layer above the substrate layer, a channel layer above the buffer layer, the surface of the channel layer having a horizontal two-dimensional electron gas, a barrier layer above the channel layer, a first dielectric layer above the barrier layer, and a first conductive type gallium nitride, a source metal and a drain metal separated by the first dielectric layer, and a gate metal above the first conductive type gallium nitride; at least a second dielectric layer and a third dielectric layer above the first dielectric layer, the adjacent dielectric layers being composed of different materials; the first dielectric layer, the second dielectric layer and the third dielectric layer rising in a stepped manner between the gate metal and the drain metal to form a stepped side, a stepped integrated field plate above the formed stepped side, and a top dielectric layer above the stepped integrated field plate.

[0004] Further, a fourth dielectric layer is further provided above the third dielectric layer, the fourth dielectric layer further extending the formed stepped side, so that the stepped integrated field plate is further extended upward; or,

[0005] A fifth dielectric layer is further provided above the fourth dielectric layer, the fifth dielectric layer further extending the formed stepped side, so that the stepped integrated field plate is further extended upward; or,

[0006] In succession, more medium layers can be designed according to actual requirements to further extend the stepped integrated field plate.

[0007] Further, the stepped integrated field plate gradually rises from the gate metal to the drain metal.

[0008] Further, the inclination angle of the stepped integrated field plate is greater than or equal to 90° and less than 180°.

[0009] Further, the medium layers are the same in composition to simplify the process.

[0010] The application also provides a forming method of a gallium nitride power device, which comprises the following steps:

[0011] Firstly, a buffer layer is formed on a substrate layer, then a channel layer is formed on the buffer layer, and then a barrier layer is formed on the channel layer;

[0012] Secondly, a patterned first-conductive-type gallium nitride layer and a gate metal thereon are formed on the barrier layer;

[0013] Thirdly, a patterned source metal and a drain metal are formed on the barrier layer;

[0014] Fourthly, a plurality of medium layers are formed on the barrier layer according to actual requirements, and the adjacent medium layers are different in composition;

[0015] Fifthly, a photoresist layer is formed on the surface of the uppermost medium layer by photoetching;

[0016] Sixthly, the uppermost medium layer is subjected to wet etching to remove part of the medium layer and expose the medium layer thereunder;

[0017] Then, the medium layer continues to be subjected to dry etching to remove part of the medium layer and expose another medium layer thereunder;

[0018] In succession, the medium layers are etched to form stepped medium layers by means of the photoresist layer, and stepped side edges are obtained;

[0019] Seventhly, a plurality of stepped integrated field plates are formed on the stepped side edges, and then a top medium layer is formed on the stepped integrated field plates.

[0020] Further, the substrate layer is composed of silicon, gallium nitride, silicon carbide or sapphire; or the buffer layer is composed of aluminum gallium nitride, aluminum nitride or gallium nitride, or the buffer layer comprises a plurality of gallium nitride layers with different carbon and iron impurity contents; or,

[0021] The channel layer is composed of undoped gallium nitride or doped gallium nitride; or,

[0022] The barrier layer is composed of aluminum gallium nitride; or,

[0023] The dielectric layer is composed of oxide or nitride; or,

[0024] The multi-layer step-shaped integrated field plate is formed of titanium, nickel, tungsten, aluminum and / or gold.

[0025] The gallium nitride power device is formed by the method comprising the following steps: in the second step, the gate metal and the first conductive type gallium nitride thereunder form a Schottky contact; or,

[0026] In the third step, the source metal and the drain metal and the semiconductor thereunder form an ohmic contact.

[0027] In the preparation method, no matter how many layers of the field plate are, only one field plate deposition is needed, in addition, two etchings and two layers of field plates are formed by each lithography, the number of lithography for forming the multi-layer field plate is halved, compared with the multi-layer independent field plate, the process of the present application is simpler, and the cost is also lower. In other words, the present application can increase the number of layers of the field plate without increasing the complexity and cost of the process, so that the electric field distribution between the gate metal and the drain metal of the device is more uniform, and the breakdown voltage and reliability of the device are improved. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 It is a cross-sectional schematic diagram of an existing high electron mobility transistor structure.

[0029] Figure 2 It is a cross-sectional schematic diagram of an existing high electron mobility transistor structure. Figure 1 It is a cross-sectional schematic diagram of an existing high electron mobility transistor structure.

[0030] Figure 3 It is a cross-sectional schematic diagram of an existing high electron mobility transistor structure.

[0031] Figure 4 It is a cross-sectional schematic diagram of an existing high electron mobility transistor structure.

[0032] Figure 5 It is a cross-sectional schematic diagram of an existing high electron mobility transistor structure.

[0033] Figure 6 It is a cross-sectional schematic diagram of an existing high electron mobility transistor structure.

[0034] Figure 7 It is a cross-sectional schematic diagram of an existing high electron mobility transistor structure. DETAILED DESCRIPTION

[0035] The present application will be described in detail below with reference to the accompanying drawings and embodiments. It should be noted that the positional terms such as "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", "vertical", used in this document are relative to the positions of the reference figures. The specific implementation does not limit the fixed direction. The devices in the drawings are not necessarily drawn in specific proportions. The straight lines shown in the boundaries of the doped regions and trenches in the drawings, and the sharp corners formed by the boundaries, are generally not straight lines and precise angles in actual applications.

[0036] Embodiment 1

[0037] Please refer to Figure 3 , Figure 3 The cross-sectional schematic diagram of the device structure of the first embodiment of the present application, which includes:

[0038] The substrate layer 300 at the bottom;

[0039] The buffer layer 301 above the substrate layer;

[0040] The channel layer 302 above the buffer layer;

[0041] The barrier layer 303 above the channel layer;

[0042] The P-type gallium nitride 304, the source metal 306, the drain metal 307 and the first dielectric layer 308A distributed thereon above the barrier layer 303; The gate metal 305 is provided above the P-type gallium nitride 304;

[0043] The second dielectric layer 309A above the first dielectric layer 308A;

[0044] The third dielectric layer 308B above the second dielectric layer 309A;

[0045] The fourth dielectric layer 309B above the third dielectric layer 308B;

[0046] The fifth dielectric layer 308C above the fourth dielectric layer 309B;

[0047] The multi-layer stepped integrated field plate 310 above the first dielectric layer 308A, the second dielectric layer 309A, the third dielectric layer 308B, the fourth dielectric layer 309B and the fifth dielectric layer 308C;

[0048] The sixth dielectric layer 308D above the multi-layer stepped integrated field plate 310;

[0049] In the above structure, the channel layer 302 surface has a horizontal two-dimensional electron gas (2DEG), and forms a current channel between the source and the drain when the device is turned on.

[0050] In the above structure, the multi-layer stepped integrated field plate 310 has five field plates, located on the sidewalls and above the first dielectric layer 308A, the second dielectric layer 309A, the third dielectric layer 308B, the fourth dielectric layer 309B, and the fifth dielectric layer 308C, respectively. The sidewalls formed by these dielectric layers are stepped continuous sidewalls, therefore the field plates formed on and above these sidewalls are also... Figure 3 The multi-layer stepped integrated field plate 310 shown in this embodiment has an inclination angle @ equal to or close to 90°.

[0051] In the above structure, the multi-layer stepped integrated field plate 310 is connected to the source metal 306 or the gate metal 305. In some variations, additional electrodes may also be introduced.

[0052] In one embodiment, the multi-layer stepped integral field plate 310 material may include, but is not limited to, metals such as titanium, nickel, tungsten, aluminum, and gold, and their metal compounds.

[0053] In the above structure, the first dielectric layer 308A isolates the upper multilayer stepped integrated field plate 310 from the lower barrier layer 303 and reduces lattice defects on the surface of the barrier layer 303.

[0054] In the above structure, such as Figure 4 As shown, the opening width d3 of the third dielectric layer 308B is larger than the opening width d2 of the second dielectric layer 309A, the opening width d4 of the fourth dielectric layer 309B is larger than the opening width d3 of the third dielectric layer 308B, and the opening width d5 ​​of the fifth dielectric layer 308C is larger than the opening width d4 of the fourth dielectric layer 309B. The first to fifth dielectric layers form a multi-layer stepped shape, located below the multi-layer stepped integrated field plate 310. Therefore, the stepped integrated field plate 310 rises step by step from the gate metal 305 to the drain metal 307, and the opening width gradually increases with the increase of the number of layers.

[0055] In one embodiment, the first dielectric layer 308A, the second dielectric layer 309A, the third dielectric layer 308B, the fourth dielectric layer 309B, the fifth dielectric layer 308C, and the sixth dielectric layer 308D are typically composed of oxides or nitrides, such as aluminum oxide, silicon oxide, gallium oxide, aluminum nitride, silicon nitride, etc.

[0056] In the above structure, the second dielectric layer 309A and the third dielectric layer 308B are composed of different materials.

[0057] In the above structure, the third dielectric layer 308B and the fourth dielectric layer 309B are composed of different materials.

[0058] In the above structure, the fourth dielectric layer 309B and the fifth dielectric layer 308C are composed of different materials.

[0059] In one embodiment, the first dielectric layer 308A, the third dielectric layer 308B, the fifth dielectric layer 308C and the sixth dielectric layer 308D can be composed of the same material, i.e. the materials of the dielectric layers in between can be the same, simplifying the process.

[0060] In one embodiment, the second dielectric layer 309A and the fourth dielectric layer 309B can be composed of the same material, simplifying the process.

[0061] In the above structure, the multi-layered stepped integrated field plate 310 reduces the electric field peak between the gate metal 305 and the drain metal 307 when the device is under voltage, making the electric field distribution more even, and improving the breakdown voltage and reliability of the device.

[0062] Embodiment 2

[0063] A variation of the device embodiment of the present application is shown in Figure 5 and Figure 3 The difference between the embodiment and the variation is that the sidewalls of the second dielectric layer 309A, the third dielectric layer 308B, the fourth dielectric layer 309B and the fifth dielectric layer 308C are inclined instead of vertical, and therefore the multi-layered stepped integrated field plate 310 located at the sidewalls of the second dielectric layer 309A, the third dielectric layer 308B, the fourth dielectric layer 309B and the fifth dielectric layer 308C is also inclined instead of vertical, and in this embodiment, the inclination angle of the stepped integrated field plate 310 is greater than 90°.

[0064] In one embodiment, the inclination angles of the sidewalls of the second dielectric layer 309A, the third dielectric layer 308B, the fourth dielectric layer 309B and the fifth dielectric layer 308C can be different, and the inclination angles depend on the process conditions.

[0065] In one embodiment, the inclination angles of the multi-layered stepped integrated field plate 310 located at the sidewalls of the second dielectric layer 309A, the third dielectric layer 308B, the fourth dielectric layer 309B and the fifth dielectric layer 308C can be different, and depend on the inclination angles of the sidewalls of the second dielectric layer 309A, the third dielectric layer 308B, the fourth dielectric layer 309B and the fifth dielectric layer 308C.

[0066] In the above structure, the multi-layered stepped integrated field plate 310 more effectively reduces the electric field peak between the gate metal 305 and the drain metal 307 when the device is under voltage, making the electric field distribution more even, and further improving the breakdown voltage and reliability of the device.

[0067] Embodiment 3

[0068] A variation of the device embodiment of the present application is shown inFigure 6 As shown, and Figure 3 The difference in the embodiment is that the multi-layer stepped integrated field plate 310 has three layers instead of five layers, which are located on the sidewalls and above the first dielectric layer 308A, the second dielectric layer 309A and the third dielectric layer 308B respectively.

[0069] In the above structure, the second dielectric layer 309A and the third dielectric layer 308B are composed of different materials.

[0070] In one embodiment, the first dielectric layer 308A, the third dielectric layer 308B, and the fourth dielectric layer 308C can be composed of the same material, that is, the dielectric layers separated by each other can be composed of the same material, thereby simplifying the process.

[0071] and with three independent field plates Figure 1 Component comparison Figure 3 The embodiment has the same number of field plates, but the process is simpler and the cost is lower.

[0072] Example 4

[0073] A variation of the device embodiment of the present invention may have five or more, compared to Figure 3 The embodiments have a greater number of field plates, such as seven, nine, etc.

[0074] In the above structure, due to the ratio Figure 3 The embodiments have multiple field plates, such as Figure 2 As shown, the maximum electric field between the gate and drain is relatively low, resulting in higher breakdown voltage and reliability of the device, although the manufacturing process is more complex.

[0075] Those skilled in the art should know that the structural features mentioned in the various embodiments of the present invention above can be combined with each other to form more device structures of the present invention embodiments.

[0076] Example 5 Based on the structural features of the above-described embodiments of the present invention, and combined with existing gallium nitride high electron mobility transistor manufacturing processes, various methods for forming embodiments of the present invention can be obtained. An exemplary method for forming an embodiment of the present invention is as follows: Figure 7 As shown: The first step is to form a buffer layer 301 on the substrate layer 300, then form a channel layer 302 on the buffer layer 301, and then form a barrier layer 303 on the channel layer 302, as shown in 7A.

[0079] The substrate 300 is usually made of silicon, but it may also be made of materials such as gallium nitride, silicon carbide, or sapphire.

[0080] The buffer layer 301 can comprise a combination of materials such as aluminum gallium nitride, aluminum nitride, gallium nitride, etc. The combination of materials can comprise multiple layers of gallium nitride with different carbon, iron, etc. impurity contents, and can be beneficial in reducing leakage current and crystal misregistration.

[0081] The channel layer 302 can be undoped gallium nitride or doped gallium nitride.

[0082] The barrier layer 303 can be aluminum gallium nitride.

[0083] The above structure can be formed by processes such as chemical vapor deposition, physical vapor deposition, epitaxial growth, etc.

[0084] In a second step, a patterned P-type gallium nitride layer 304 and an overlying gate metal 305 are formed over the barrier layer 303, as shown in FIG. 3B. Figure 7

[0085] The P-type gallium nitride layer 304 can be formed by processes such as chemical vapor deposition, physical vapor deposition, epitaxial growth, etc. The method of forming the patterned P-type gallium nitride 304 can include process steps such as photolithography, dry etching, wet etching, etc.

[0086] The gate metal layer can be formed by processes such as evaporation, sputtering, etc., and can comprise materials such as but not limited to titanium, nickel, tungsten, aluminum, gold, etc. and their metal compounds. The method of forming the patterned gate metal 305 can include process steps such as photolithography, dry etching, wet etching, etc.

[0087] Typically, the gate metal 305 needs to form a Schottky contact with the P-type gallium nitride 304 located thereunder.

[0088] In a third step, a patterned source metal 306 and a patterned drain metal 307 are formed over the barrier layer 303, as shown in FIG. 3C. Figure 7

[0089] The source and drain metal layers can be formed by processes such as evaporation, sputtering, etc., and can comprise materials such as but not limited to titanium, nickel, tungsten, aluminum, gold, etc. and their metal compounds. The method of forming the patterned source metal 306 and the patterned drain metal 307 can include process steps such as photolithography, dry etching, wet etching, etc.

[0090] Typically, the source metal 306 and the drain metal 307 need to form an Ohmic contact with the semiconductor located thereunder.

[0091] ​​Fourthly, a first dielectric layer 308A is formed above the barrier layer 303, a second dielectric layer 309A is formed above the first dielectric layer 308A, a third dielectric layer 308B is formed above the second dielectric layer 309A, a fourth dielectric layer 309B is formed above the third dielectric layer 308B, and a fifth dielectric layer 308C is formed above the fourth dielectric layer 309B, as shown in FIG. 3D. Figure 7

[0092] The first dielectric layer 308A, the second dielectric layer 309A, the third dielectric layer 308B, the fourth dielectric layer 309B, and the fifth dielectric layer 308C are usually composed of oxide or nitride, such as aluminum oxide, silicon oxide, gallium oxide, aluminum nitride, silicon nitride, etc.

[0093] The second dielectric layer 309A and the third dielectric layer 308B are composed of different materials.

[0094] The third dielectric layer 308B and the fourth dielectric layer 309B are composed of different materials.

[0095] The fourth dielectric layer 309B and the fifth dielectric layer 308C are composed of different materials.

[0096] The first dielectric layer 308A, the third dielectric layer 308B, and the fifth dielectric layer 308C can be composed of the same material.

[0097] The second dielectric layer 309A and the fourth dielectric layer 309B can be composed of the same material.

[0098] Fifthly, a photoresist layer 311 is formed on the surface of the fifth dielectric layer 308C by photolithography, as shown in FIG. 3E. Figure 7

[0099] Sixthly, the fifth dielectric layer 308C is removed by wet etching, and part of the fourth dielectric layer 309B is exposed, as shown in FIG. 3F. Figure 7

[0100] Since the fourth dielectric layer 309B and the fifth dielectric layer 308C are composed of different materials, the fifth dielectric layer 308C can be etched while the fourth dielectric layer 309B is preserved by selective wet etching.

[0101] Seventhly, the fourth dielectric layer 309B is removed by dry etching, and part of the third dielectric layer 308B is exposed, as shown in FIG. 3G. Figure 7

[0102] Since the third dielectric layer 308B and the fourth dielectric layer 309B are composed of different materials, the third dielectric layer 308B can be used as an etch stop layer for dry etching of the fourth dielectric layer 309B. ​​​​

[0103] The eighth step is to remove the photoresist layer 311 and perform photoetching on the surface of the third dielectric layer 308B to form a patterned photoresist layer 312, as shown in Figure 7 H.

[0104] The ninth step is to perform wet etching on the third dielectric layer 308B and dry etching on the second dielectric layer 309A, and remove the photoresist layer 312, as shown in Figure 7 I.

[0105] The tenth step is to form a multi-layer stepped integrated field plate 310 above the first dielectric layer 308A, the second dielectric layer 309A, the third dielectric layer 308B, the fourth dielectric layer 309B, and the fifth dielectric layer 308C. Form a sixth dielectric layer 308D above the multi-layer stepped integrated field plate 310, as shown in Figure 7 J.

[0106] The multi-layer stepped integrated field plate layer can be formed by processes such as evaporation, sputtering, etc., and the constituent materials can include but are not limited to metals such as titanium, nickel, tungsten, aluminum, gold, and their metal compounds. The method for forming the patterned multi-layer stepped integrated field plate 310 can include process steps such as photoetching, dry etching, wet etching, etc.

[0107] Those skilled in the art should know that the above manufacturing steps only list the key steps and do not show the complete steps of forming the device. The specific detailed manufacturing steps can be obtained and appropriately added, reduced, and changed according to the common manufacturing process steps and common sense knowledge in the art.

Claims

1. A gallium nitride power device, comprising a substrate layer at the bottom, a buffer layer above the substrate layer, a channel layer above the buffer layer, the surface of the channel layer having a two-dimensional electron gas in the horizontal direction, a barrier layer above the channel layer, a first dielectric layer above the barrier layer, and a first conductive type gallium nitride, a source metal and a drain metal separated by the first dielectric layer, a gate metal above the first conductive type gallium nitride; characterized in that At least a second dielectric layer and a third dielectric layer above the first dielectric layer, the adjacent dielectric layers having different materials; The first dielectric layer, the second dielectric layer and the third dielectric layer form a stepped side between the gate metal and the drain metal, a stepped integrated field plate above the stepped side, and a top dielectric layer above the stepped integrated field plate.

2. A gallium nitride power device as defined in claim 1, wherein, A fourth dielectric layer above the third dielectric layer, the fourth dielectric layer further extending the stepped side, so that the stepped integrated field plate is further extended upward; or A fifth dielectric layer above the fourth dielectric layer, the fifth dielectric layer further extending the stepped side, so that the stepped integrated field plate is further extended upward; or More dielectric layers are provided to further extend the stepped integrated field plate.

3. A gallium nitride power device as claimed in claim 1 or 2, wherein The stepped integrated field plate gradually rises from the gate metal to the drain metal.

4. A gallium nitride power device as claimed in claim 1 or 2, wherein The inclination angle of the stepped integrated field plate is greater than or equal to 90° and less than 180°.

5. A gallium nitride power device as claimed in claim 1 or 2, wherein The adjacent dielectric layers are dielectric layers with the same material.

6. A method of forming a gallium nitride power device, comprising: The forming method comprises the following steps: First, form a buffer layer on the substrate layer, then form a channel layer above the buffer layer, and then form a barrier layer above the channel layer; Second, form a patterned first conductive type gallium nitride layer and a gate metal above the barrier layer; Third, form a patterned source metal and a drain metal above the barrier layer; Fourth, form a plurality of dielectric layers above the barrier layer in sequence, the adjacent dielectric layers having different materials; Fifth, perform photolithography on the surface of the uppermost dielectric layer to form a patterned photoresist layer; Sixth, perform wet etching on the exposed uppermost dielectric layer to remove part of the dielectric layer and expose the dielectric layer below; Then continue to perform dry etching on the exposed dielectric layer to remove part of the exposed dielectric layer and expose another dielectric layer below; Continue to etch in sequence, and finally form the stepped dielectric layers by means of the photoresist layer to obtain a stepped side; Seventh, form a plurality of stepped integrated field plates above the stepped side, and then form a top dielectric layer above the stepped integrated field plates.

7. The method of forming a gallium nitride power device of claim 6, wherein, The substrate layer is made of silicon, gallium nitride, silicon carbide or sapphire; or The buffer layer is made of aluminum gallium nitride, aluminum nitride or gallium nitride, or the buffer layer comprises a plurality of gallium nitride layers with different carbon and iron impurity contents; or The channel layer is made of undoped gallium nitride or doped gallium nitride; or The barrier layer is composed of aluminum gallium nitride; or The dielectric layer is composed of oxide or nitride; or The multilayer step-shaped integrated field plate is formed by titanium, nickel, tungsten, aluminum and / or gold.

8. The method of claim 6, wherein the gate metal and the first conductivity type gallium nitride layer thereunder form a Schottky contact; or the source metal and the drain metal and the semiconductor thereunder form an ohmic contact. ​

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