Back contact battery hot spot prevention structure and preparation method thereof

Abstract

The invention relates to the photovoltaic field, and discloses a hot spot prevention structure of a back contact battery and a preparation method of the hot spot prevention structure. According to the hot spot prevention structure of the back contact battery, the boron-doped layer and the extended phosphorus-doped layer are disconnected through the gap; wherein the boron diffusion layer and the phosphorus diffusion layer can form a conductive channel, the conductive channel is located in the semi-silicon substrate and is formed by diffusing boron / phosphorus atoms into the silicon substrate and diffusing the boron / phosphorus atoms to the periphery, and the design can avoid generation of larger conduction electric leakage. According to the hot spot prevention structure of the back contact battery, the electric leakage loss can be effectively reduced on the basis of reducing the risk of generating a hot spot effect at the assembly end.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of photovoltaics, in particular to a back contact cell anti-hot spot structure and a preparation method thereof. BACKGROUND

[0002] The back contact cell is a technology that places both positive and negative metal contacts of a solar cell on the back of the cell. Its front side without shading structure can increase the effective light receiving area of the module and improve the conversion efficiency of the photovoltaic module. The back contact cell technology is highly concerned in the photovoltaic industry due to its high efficiency and beautiful front appearance.

[0003] From the perspective of the back contact cell, the cell generally includes two doped semiconductor layers with opposite conduction types, which are cross-contacted, and a gap is needed between them to prevent physical contact to suppress forward leakage, so that the back contact cell has high photoelectric conversion efficiency in the forward voltage region. In order to separate the two doped semiconductor layers with opposite conduction types included in the back contact cell without physical contact, the prior art usually opens a groove between the two doped semiconductor layers, and the bottom of the groove is a semiconductor substrate. However, in actual use, when the photovoltaic module formed by using the back contact cell is covered with leaves, dust, snow and other shading objects, hot spot effect will occur in the photovoltaic module, affecting the performance of the photovoltaic module.

[0004] Common anti-hot spot structure of back contact cell (patent CN 118825109 A, CN 118472069B): the thickness of the first doped semiconductor layer located in the first region and the thickness of the second doped semiconductor layer located in the second region are both greater than the thickness of the conductive channel, that is, the upper part of the conductive channel is a spare area. The above-mentioned spare area can play an insulating role to prevent leakage from occurring, thereby realizing the control of leakage. Further, the conductive channel with a thickness smaller than the thickness of the first doped semiconductor layer located in the first region and the thickness of the second doped semiconductor layer located in the second region can ensure the normal operation of the back contact cell, and when the back contact cell is shaded, the current can be transmitted through the first doped semiconductor layer, the conductive channel and the second doped semiconductor layer. At this time, the conductive channel not only can reduce the reverse voltage between the two ends of the back contact cell, effectively reduce the hot spot effect of the back contact cell, but also can avoid the shaded back contact cell from becoming a load to consume the energy generated by other illuminated cell pieces, further reducing the risk of hot spots. When the conductive channel includes a co-doped semiconductor layer, since the co-doped semiconductor layer has a higher doping concentration and smaller resistance, it is beneficial to current passing and easier to realize conduction, thereby ensuring the anti-hot spot effect.

[0005] However, most of the existing anti-hot spot structures of back contact cells have the problem of excessive leakage loss and local overheating. SUMMARY

[0006] To solve the above technical problems, the present application provides a back contact cell anti-hot spot structure and a preparation method thereof. The back contact cell anti-hot spot structure of the present application can effectively reduce the loss of leakage current while reducing the risk of hot spot effect at the module end.

[0007] The specific technical solutions of the present application include: In a first aspect, a back contact cell anti-hot spot structure is provided, which comprises: a silicon substrate, the back surface of which is provided with p regions and n regions arranged alternately, and an isolation region between the p regions and the n regions; a boron-doped layer provided on the surface of the p region; a phosphorus-doped layer provided on the surface of the n region; at least one extended phosphorus-doped layer provided on the surface of the isolation region, connected to the phosphorus-doped layer, extending towards the boron-doped layer, and provided with a gap between the boron-doped layer; a conductive channel provided at the bottom of the boron-doped layer, the phosphorus-doped layer, the extended phosphorus-doped layer, and the gap.

[0008] Specifically, the conductive channel is composed of a boron diffusion layer and a phosphorus diffusion layer; the bottom of the phosphorus-doped layer and the extended phosphorus-doped layer is provided with a phosphorus diffusion layer; the bottom of the boron-doped layer is provided with a boron diffusion layer; and the bottom of the gap is provided with a phosphorus diffusion layer.

[0009] In the above-mentioned back contact cell anti-hot spot structure of the present application, the gap breaks the connection between the boron-doped layer and the extended phosphorus-doped layer (in the conventional anti-hot spot structure, the connection is continuous, i.e., there is no gap, and the extended phosphorus-doped layer is directly connected to the opposite boron-doped layer); the boron diffusion layer and the phosphorus diffusion layer (co-doped with phosphorus atoms and boron atoms) can form a conductive channel, which is located inside the silicon substrate (formed by the diffusion of boron / phosphorus atoms into the silicon substrate and the diffusion to the surrounding); this design can avoid the generation of larger leakage current.

[0010] As an embodiment, the gap is a polished surface or a pyramid suede surface.

[0011] The gap (polished surface or pyramid suede surface) breaks the connection between the extended phosphorus-doped layer and the boron-doped layer, which can reduce parasitic absorption and is beneficial to obtaining higher optical performance compared to the conventional anti-hot spot design.

[0012] As an embodiment, the surface of the non-extended phosphorus-doped layer of the isolation region and the non-gap region is a pyramid suede surface.

[0013] As an embodiment, the width of the gap (i.e., the lateral dimension, the distance from the extended phosphorus-doped layer to the opposite boron-doped layer) is 1 / 10 to 4 / 5 of the total width of the isolation region.

[0014] The lateral dimension of the gap needs to be optimized. If the lateral dimension is too small, the risk of leakage will be too high. Conversely, if the lateral dimension is too large, conduction will not be possible.

[0015] Secondly, a method for preparing the aforementioned back contact battery anti-hot spot structure is provided, which specifically includes the following steps: S1. Polish the silicon substrate on both sides.

[0016] S2, UV laser oxidation of the n-region, extended phosphorus doped layer, and interstitial preset region, forming an oxide layer in the region.

[0017] The purpose of forming an oxide layer in the extended phosphorus doped layer and the pre-set gap region in step S2 is as follows: (1) Since the passivation layer formed in S3 cannot effectively protect the surface of the isolation region of the bottom silicon substrate during the subsequent alkaline cleaning process in S6, the boron diffusion layer below the passivation layer will be removed simultaneously during the alkaline etching process, resulting in a significant height difference between the subsequent p-region and n-region, making it impossible to form a conductive design between the p-region and n-region on the same horizontal plane; the pre-set n-region has a similar effect. If it is not oxidized, the p-region and n-region cannot be kept on the same horizontal plane during the subsequent alkaline cleaning process; (2) By retaining the boron diffusion layer below the passivation layer after boron diffusion, the phosphorus doped atoms can be co-doped with the initial boron doped atoms in the bottom region of the extended phosphorus doped layer and the gap during the subsequent phosphorus diffusion process, thereby playing a conductive role. For this reason, the present invention adopts an ultraviolet laser oxidation method, which can selectively oxidize only the pre-designed extended phosphorus doped layer and the pre-set gap region on the back side of the silicon substrate to form an oxide layer. This oxide layer can effectively resist the corrosion of the bottom silicon substrate surface by alkaline solution, thereby ensuring that the bottom diffusion layer of the treated area is not damaged.

[0018] S3, passivation layer and i-poly-Si layer deposited on the back side.

[0019] S4. Boron diffusion: This transforms the inner and outer layers of the i-poly-Si layer into boron-doped and BSG layers, respectively, and simultaneously transforms the surface layer of the silicon substrate in all regions into a boron-diffused layer. Furthermore, the oxide layer formed in S2 is thicker than the passivation layer in S3, resulting in a higher concentration of boron doped atoms at the bottom of the passivation layer and a lower concentration at the bottom of the oxide layer during boron diffusion. S5. Laser removal of the BSG layer in the predetermined n-region and isolation region prepares the ground for subsequent alkaline washing.

[0020] S6. Alkali washing removes the boron-doped layer and passivation layer in the preset areas of the n-region and isolation region; acid washing removes the oxide layer.

[0021] Alkaline washing can remove the boron-doped layer and passivation layer in the S5 laser-treated area. Because the silicon substrate surface in the n-region, extended phosphorus-doped layer, and interstitial region has a pre-existing oxide layer, the alkaline solution cannot penetrate the oxide layer to corrode the underlying silicon substrate. Simultaneously, the boron-doped layer in the non-laser-treated area is protected by a BSG layer, which effectively prevents damage during alkaline washing. Subsequently, the oxide layer (which is alkali-resistant but not acid-resistant) is removed using the low-concentration acid (HF) bath integrated into the alkaline washing tank. Since the BSG layer on the boron-doped layer surface in the non-laser-treated area is thicker, only a small portion is removed, with most remaining intact.

[0022] S7. Ultraviolet laser secondary oxidation gap preset area, forming an oxide layer, followed by annealing treatment.

[0023] The function of forming an oxide layer in the pre-defined interstitial region is similar to that in S2. Furthermore, during UV oxidation, a high degree of UV oxidation makes it difficult for phosphorus-doped atoms to penetrate the oxide layer and enter the silicon substrate during subsequent phosphorus diffusion. This results in a low phosphorus atom concentration on the silicon substrate surface, leading to poor conductivity in this area and preventing the formation of an effective conductive structure with the p-region on the other side. Conversely, a low degree of UV oxidation makes it impossible to ensure the bottom phosphorus diffusion layer remains intact during subsequent wet alkaline etching. When the interstitial region is a polished surface, high-temperature annealing is required to repair the oxide layer to simultaneously satisfy both oxide layer characteristics. High-temperature annealing promotes atomic diffusion and bonding recombination within the oxide layer, eliminates local stress, and makes the oxide layer more compact, effectively blocking subsequent wet alkaline etching. Simultaneously, during densification, the oxide layer thickness will locally thin due to internal atomic flow, forming controllable nanoscale pinholes. These pinholes are not defects in the traditional sense, but rather "selective channels" controlled by annealing. The presence of pinholes provides a low-resistance tunneling path for charge carriers (such as electrons or holes) and some doped atoms to diffuse into the silicon substrate (when the passivation layer is a tunneling oxide layer), thus improving the conductivity of the battery. When the interstitial region has a pyramidal textured surface, it is only necessary to make the oxide layer formed by the ultraviolet laser thinner (but the thickness should be greater than the passivation layer thickness). On the one hand, this allows phosphorus doped atoms to penetrate the oxide layer and enter the silicon substrate during phosphorus diffusion, thereby forming a conductive structure in the future. On the other hand, it can slow down the corrosion of this area during texturing, resulting in a shallower corrosion depth. This allows some of the phosphorus diffusion layer at the bottom of the oxide layer to not be completely removed, and a conductive structure can still be formed in the future.

[0024] S8, backside secondary deposition passivation layer, i-poly-Si layer.

[0025] S9, Phosphorus diffusion; transforms the inner and outer layers of the i-poly-Si layer into phosphorus-doped and PSG layers, respectively, and simultaneously transforms the boron diffusion layers in the isolation region and the preset n-region into phosphorus diffusion layers.

[0026] Because the oxide layer in S7 undergoes annealing, some pinholes will appear in the oxide layer. These pinholes help phosphorus dopants penetrate the oxide layer and enter the silicon substrate, thus transforming the boron diffusion layer into a phosphorus diffusion layer.

[0027] S10, laser removal of the PSG layer in the preset area of ​​the non-extended phosphorus doped layer in the p-region and isolation region, can pave the way for subsequent S12 alkaline washing texturing and acid washing.

[0028] S11. Remove the wrap-around plating. The purpose of this step is to remove the wrap-around plating on the front and sides of the silicon substrate.

[0029] S12, alkaline washing and texturing, acid washing to remove residual PSG layer, BSG layer and oxide layer.

[0030] The silicon substrate with the coating removed is placed in an alkaline texturing bath for integrated wet cleaning and texturing. Since the front side of the silicon substrate has no oxide areas after the coating removal, a pyramidal textured surface can be formed during the texturing process. For the p-region on the back side of the silicon substrate, the outermost PSG layer, phosphorus-doped layer, and passivation layer can be washed away during wet texturing. The boron-doped layer in the p-region is protected from alkaline corrosion by the BSG layer. For the n-region on the back side of the silicon substrate, since no laser treatment is performed, the surface PSG layer protects the phosphorus diffusion layer from damage during wet texturing. For the isolation region on the back side of the silicon substrate, the PSG layer extending to the surface of the phosphorus-doped layer protects the bottom from damage. In the gap region, the surface PSG layer is removed by laser, and the bottom phosphorus-doped layer is simultaneously cleaned during alkaline texturing until the oxide layer interface formed by UV oxidation stops (the phosphorus diffusion layer remains undamaged, thus providing conductivity), thereby forming a polished surface gap structure. Furthermore, in the non-extended phosphorus-doped layer region of the isolation zone and the interstitial region (when the interstitial surface is designed as a pyramidal textured surface), a light-trapping pyramidal textured surface can be formed simultaneously during the texturing process. After texturing, the texturing tank is equipped with an acid (HF) washing tank to further remove the residual PSG layer, BSG layer, and oxide layer on the silicon substrate surface, ultimately achieving the disconnection of p-poly and n-poly on the silicon substrate surface, while the bottom diffusion layer of the passivation layer forms a p-region and n-region conductive structure.

[0031] S13, double-sided coating.

[0032] S14, screen printing, sintering, photoinjection.

[0033] In one implementation, the conditions for the ultraviolet laser in S2 are: laser wavelength 300-400nm, power 5-100W, processing time 1-20s, and oxide layer thickness 2-50nm.

[0034] In one embodiment, in S4, the conditions for boron diffusion are: boron diffusion temperature 800–950°C, diffusion time 5–50 min, BCl3 flow rate 5–500 sccm, O2 flow rate 500–2000 sccm; oxidation propulsion temperature 900–1050°C, O2 flow rate 5000–30000 sccm, propulsion time 30–80 min, and the thickness of the resulting BSG layer is 30–70 nm.

[0035] In one embodiment, in S6, the alkaline washing conditions are: KOH solution concentration of 1.7-2.2 wt% and temperature of 75-85°C; the acid washing conditions are: HF solution concentration in the acid washing tank of 1-10 wt% and time of 30-60 s.

[0036] In one implementation, in S7, the conditions for the ultraviolet laser are: laser wavelength 300-400nm, power 20-100W, processing time 5-20s, and oxide layer thickness 5-50nm.

[0037] In one implementation, in S7, when the gap is a polished surface, the conditions for the ultraviolet laser are: laser wavelength 300-400nm, power 20-100W, processing time 5-20s, and oxide layer thickness 5-50nm; or when the gap is a pyramidal textured surface, the conditions for the ultraviolet laser are: laser wavelength 300-400nm, power 2-10W, processing time 1-5s, and oxide layer thickness 1-10nm.

[0038] This invention allows for the formation of either a polished or pyramidal textured surface in the gap area by controlling the UV oxidation process conditions in S7. When the oxide layer formed in S7 is thick, it can protect the phosphorus diffusion layer from damage during subsequent texturing, thus ultimately forming a polished surface. Conversely, when the oxide layer is thin, it cannot effectively protect the phosphorus diffusion layer from damage during subsequent texturing, but the degree of corrosion is not as great as in other areas of the isolation zone. Therefore, while forming a pyramidal textured surface in the gap area, a conductive design can still be achieved at the bottom.

[0039] As one implementation method, in S7, the annealing conditions are as follows: tubular annealing is used, inert gas (Ar, N2, etc.) atmosphere, annealing conditions are 800-1050℃, 10-60min.

[0040] In one implementation, in S9, the phosphorus diffusion conditions are as follows: first, a mixed gas of POCl3 and O2 is introduced at a temperature of 750–850°C for a diffusion time of 5–30 min, with a flow rate of POCl3 carried by N2 of 500–1200 sccm and an O2 flow rate of 500–1000 sccm; then, O2 is introduced for oxidation propulsion at a temperature of 850–950°C for a propulsion time of 20–60 min and an O2 flow rate of 1000–10000 sccm, resulting in a PSG layer with a thickness of 30–70 nm.

[0041] Compared with the prior art, the beneficial effects of the present invention are: (1) The present invention provides a back contact battery heat spot prevention structure, which disconnects the boron doped layer and the extended phosphorus doped layer through a gap; wherein the boron diffusion layer and the phosphorus diffusion layer (co-doped with phosphorus atoms and boron atoms) can form a conductive channel, which is located inside the silicon substrate, thus avoiding the generation of larger conduction leakage.

[0042] (2) The present invention optimizes the lateral dimension of the gap. If the lateral dimension is too small, the risk of leakage will be too high. Conversely, if the lateral dimension is too large, conduction cannot be formed.

[0043] (3) The present invention disconnects the boron-doped layer from the extended phosphorus-doped layer by creating a gap. This design reduces the parasitic absorption of the diffusion layer (poly-Si) itself and is more conducive to obtaining higher optical performance compared with conventional hot spot prevention designs. Attached Figure Description

[0044] Figure 1 This is a cross-sectional schematic diagram of the heat-prevention structure of the back contact battery in Example 1.

[0045] Figure 2 for Figure 1 Top view.

[0046] Figure 3 for Figure 1 A magnified view of a portion of the central isolation zone.

[0047] Figure 4 This is a schematic diagram (top view) of the structure of the silicon substrate after S2 treatment in Example 2.

[0048] Figure 5 This is a schematic diagram (top view) of the structure of the silicon substrate after S4 boron diffusion in Example 2.

[0049] Figure 6 This is a schematic diagram (top view) of the structure of the silicon substrate after S7 treatment in Example 2.

[0050] Figure 7 This is a schematic diagram (top view) of the structure of the silicon substrate after S9 treatment in Example 2.

[0051] Figure 8 This is a schematic diagram of the battery structure in Comparative Example 1.

[0052] The attached figures are labeled as follows: silicon substrate 1, passivation layer 2, boron doped layer 3, phosphorus doped layer 4, pyramid textured surface 5, electrode 6, phosphorus diffusion layer 7, boron diffusion layer 8, extended phosphorus doped layer 9, gap 10, oxide layer 11. Detailed Implementation

[0053] The present invention will be further described below with reference to embodiments.

[0054] General Implementation Examples In a first aspect, a back-contact battery heat-prevention structure includes: The silicon substrate has alternating p-regions and n-regions on its back side, with an isolation region between the p-regions and n-regions; The p-region surface is sequentially provided with a passivation layer, a boron doped layer, and an electrode; The surface of the n-region is sequentially provided with a passivation layer, a phosphorus doped layer, and an electrode; The isolation region surface has at least one extended phosphorus-doped layer connected to the phosphorus-doped layer and extending towards the boron-doped layer. A gap exists between the extended phosphorus-doped layer and the boron-doped layer. The silicon substrate surface layer in the extended phosphorus-doped layer region consists of a passivation layer and a phosphorus diffusion layer, arranged from top to bottom. The silicon substrate surface layer in the gap region is a phosphorus diffusion layer. The silicon substrate surface layer at the bottom of the p-region passivation layer is a boron diffusion layer, and the silicon substrate surface layer at the bottom of the n-region passivation layer is a phosphorus diffusion layer. The phosphorus diffusion layer and the boron diffusion layer are connected to form a conductive channel.

[0055] In some preferred embodiments, the gap is a polished surface or a pyramidal velvet surface.

[0056] In some preferred embodiments, the remaining surfaces of the isolation zone are pyramidal velvet surfaces.

[0057] In some preferred embodiments, the width of the gap is 1 / 10 to 4 / 5 of the total width of the isolation zone.

[0058] Secondly, a method for preparing the above-mentioned back contact battery heat-resistant structure specifically includes the following steps: S1, polishing the silicon substrate on both sides.

[0059] In some preferred embodiments, the N-type silicon substrate cut by diamond wire is placed in an alkaline polishing bath for double-sided polishing, with the temperature maintained at 75-85°C for 6-8 minutes, the polishing thickness at 3-7 μm, and the thinning amount at 0.35-0.45 g.

[0060] S2. A preset region of the n-region, extended phosphorus doped layer, and gap is oxidized by ultraviolet laser in one step, forming an oxide layer in this region. The purpose of forming an oxide layer in the preset region of the extended phosphorus doped layer and gap is: (1) Since the passivation layer formed in S3 cannot effectively protect the surface of the isolation region of the bottom silicon substrate during the subsequent alkaline washing process in S6, the boron diffusion layer below the passivation layer will be removed simultaneously during the alkaline etching process, resulting in a significant height difference between the subsequent p-region and n-region, making it impossible to form a p-region and n-region conduction design on the same horizontal plane; (2) The boron diffusion layer below the tunneling oxygen after boron diffusion is retained, so that during the subsequent phosphorus diffusion process, phosphorus doped atoms can be co-doped with the initial boron doped atoms in the bottom region of the extended phosphorus doped layer and gap, thereby playing a conduction role. For this reason, the present invention adopts ultraviolet laser oxidation method, which can selectively oxidize only the preset region of the extended phosphorus doped layer and gap on the back side of the silicon substrate to form an oxide layer. This oxide layer can effectively resist the corrosion of the bottom silicon substrate surface by alkaline solution, thereby ensuring that the bottom diffusion layer of the treated area is not damaged.

[0061] In some preferred embodiments, the conditions for the ultraviolet laser are: laser wavelength 300-400nm, power 5-100W, processing time 1-20s, and oxide layer thickness 2-50nm.

[0062] S3, passivation layer and i-poly-Si layer deposited on the back side.

[0063] In some preferred embodiments, the deposition conditions of the passivation layer are as follows: LPCVD method, O2 flow rate 10000-80000 sccm, temperature 400-800℃, time 200-1000s, and passivation layer thickness 1-10nm; the deposition conditions of the i-poly-Si layer are as follows: LPCVD method, SiH4 flow rate 300-2000 sccm, temperature 500-700℃, time 2-4h, working gas pressure 100-500mTorr, and i-poly-Si layer thickness 100-300nm.

[0064] S4, Boron diffusion: This transforms the inner and outer layers of the i-poly-Si layer into boron-doped and BSG layers, respectively, and simultaneously transforms the surface layer of the silicon substrate in all regions into a boron-diffused layer. Furthermore, the oxide layer formed in S2 is thicker than the passivation layer in S3, resulting in a higher concentration of boron doped atoms at the bottom of the passivation layer and a lower concentration at the bottom of the oxide layer during boron diffusion.

[0065] In some preferred embodiments, the boron diffusion conditions are as follows: boron diffusion temperature 800–950℃, diffusion time 5–50 min, BCl3 flow rate 50–500 sccm, O2 flow rate 500–2000 sccm; oxidation propulsion temperature 900–1050℃, O2 flow rate 5000–30000 sccm, propulsion time 30–80 min, and the thickness of the resulting BSG layer is 30–70 nm.

[0066] S5. Laser removal of the BSG layer in the preset areas of the n-zone and isolation zone prepares the ground for subsequent alkaline washing.

[0067] In some preferred embodiments, the laser conditions are: laser wavelength 400-600nm, frequency 500-700KHz, marking speed 40000-50000mm / s, power 10-50W, and processing time 1-5s.

[0068] S6. Alkaline washing removes the boron-doped and passivation layers in the n-region and the preset isolation region; acid washing removes the oxide layer. Alkaline washing removes the boron-doped and passivation layers in the S5 laser-treated area. Because the silicon substrate surface in the n-region, extended phosphorus-doped layer, and the preset interstitial region has a pre-existing oxide layer, the alkaline solution cannot penetrate the oxide layer to corrode the underlying silicon substrate. Simultaneously, the boron-doped layer in the non-laser-treated area is protected by a BSG layer, which effectively prevents damage during alkaline washing. Subsequently, the oxide layer (which is alkali-resistant but not acid-resistant) is removed using the low-concentration acid (HF) bath integrated into the alkaline washing tank. The BSG layer on the surface of the boron-doped layer in the non-laser-treated area is thicker, so only a small portion is removed, with most remaining intact.

[0069] In some preferred embodiments, the alkaline washing conditions are: KOH solution concentration of 1.7–2.2 wt% and temperature of 75–85 °C; the acid washing conditions are: HF solution concentration of 1–10 wt% in the acid washing tank and time of 30–60 s.

[0070] S7. Secondary UV laser oxidation of the pre-defined gap region forms an oxide layer, followed by annealing. The function of forming the oxide layer in the pre-defined gap region is similar to that in S2. However, during UV oxidation, if the degree of UV oxidation is high, phosphorus-doped atoms will have difficulty penetrating the oxide layer into the silicon substrate during subsequent phosphorus diffusion. This results in a low phosphorus atom concentration on the silicon substrate surface, leading to poor conductivity in this area and preventing the formation of an effective conductive structure with the p-region on the other side. If the degree of UV oxidation is low, the phosphorus-doped layer at the bottom cannot be guaranteed to remain intact during subsequent wet alkaline etching. When the gap region is a polished surface, high-temperature annealing is required to repair the oxide layer to simultaneously meet the above two oxide layer characteristics. High-temperature annealing promotes atomic diffusion and bonding recombination within the oxide layer, eliminates local stress, and makes the oxide layer more compact overall, effectively preventing subsequent wet alkaline etching. Simultaneously, during densification, the oxide layer thickness will locally thin due to internal atomic flow, forming controllable nanoscale pinholes. These pinholes are not defects in the traditional sense, but rather "selective channels" regulated by annealing. The presence of pinholes provides a low-resistance tunneling path for charge carriers (such as electrons or holes) and some doped atoms to diffuse into the silicon substrate, improving the battery's conductivity. When the interstitial region has a pyramidal textured surface, it is only necessary to make the oxide layer formed by ultraviolet laser thinner (but thicker than the passivation layer). On the one hand, this allows phosphorus doped atoms to penetrate the oxide layer and enter the silicon substrate during phosphorus diffusion, thereby forming a conductive structure later. On the other hand, it slows down the corrosion of this area during texturing, resulting in a shallower corrosion depth, allowing some of the phosphorus diffusion layer at the bottom of the oxide layer to remain intact and still form a conductive structure later.

[0071] In some preferred embodiments, when the gap is a polished surface, the ultraviolet laser conditions are: laser wavelength 300–400 nm, power 20–100 W, processing time 5–20 s, and oxide layer thickness 5–50 nm; or when the gap is a pyramidal textured surface, the ultraviolet laser conditions are: laser wavelength 300–400 nm, power 2–10 W, processing time 1–5 s, and oxide layer thickness 1–10 nm. In some preferred embodiments, the annealing conditions are: tubular annealing, inert gas (Ar, N2, etc.) atmosphere, annealing conditions of 800–1050 °C, 10–60 min.

[0072] S8, backside secondary deposition passivation layer, i-poly-Si layer.

[0073] In some preferred embodiments, the deposition conditions of the passivation layer are as follows: LPCVD method, O2 flow rate 10000-80000 sccm, temperature 400-800℃, time 200-1000s, and passivation layer thickness 1-10nm; the deposition conditions of the i-poly-Si layer are as follows: LPCVD method, SiH4 flow rate 300-2000 sccm, temperature 500-700℃, time 2-4h, working gas pressure 100-500mTorr, and i-poly-Si layer thickness 100-300nm.

[0074] S9, Phosphorus diffusion; This transforms the inner and outer layers of the i-poly-Si layer into phosphorus-doped and PSG layers, respectively, and simultaneously transforms the boron diffusion layers in the isolation region and the preset n-region into phosphorus diffusion layers. Because the oxide layer in S7 undergoes annealing, some pinholes appear in the oxide layer. These pinholes facilitate the penetration of phosphorus-doped atoms through the oxide layer into the silicon substrate, thus transforming the boron diffusion layer into a phosphorus diffusion layer.

[0075] In some preferred embodiments, the phosphorus diffusion conditions are as follows: first, a mixed gas of POCl3 and O2 is introduced at a temperature of 750–850°C for a diffusion time of 5–30 min, with a flow rate of POCl3 carried by N2 of 500–1200 sccm and an O2 flow rate of 500–1000 sccm; then, O2 is introduced for oxidation propulsion at a temperature of 850–950°C for a propulsion time of 20–60 min and an O2 flow rate of 1000–10000 sccm, resulting in a PSG layer with a thickness of 30–70 nm.

[0076] S10, laser removal of the PSG layer in the preset area of ​​the non-extended phosphorus doped layer in the p-region and isolation region, can pave the way for subsequent S12 alkaline washing texturing and acid washing.

[0077] In some preferred embodiments, the laser conditions are: laser wavelength 400-600nm, frequency 500-700KHz, marking speed 40000-50000mm / s, power 10-50W, and processing time 1-5s.

[0078] S11. Remove the wrap-around plating. The purpose of this step is to remove the wrap-around plating on the front and sides of the silicon substrate.

[0079] In some preferred embodiments, a chain etching machine is used to remove the coating on the front and sides of the silicon substrate. The volume ratio of hydrofluoric acid solution to nitric acid solution in the acid bath is 1:2 to 1:8, wherein the concentration of hydrofluoric acid solution is 45 to 55 wt% and the concentration of nitric acid solution is 65 to 75 wt%, and the belt speed is 1 to 10 m / min.

[0080] S12. Alkaline texturing and acid washing remove residual PSG, BSG, and oxide layers. The silicon substrate with the wrap-around coating removed is placed in an alkaline texturing bath for integrated wet cleaning and texturing. Since the front side of the silicon substrate has no oxide areas after the wrap-around coating has been removed, a pyramidal textured surface can be formed during the texturing process. For the p-region on the back side of the silicon substrate, the outermost PSG layer, phosphorus doping layer, and passivation layer can be washed away during the wet texturing process. The boron doped layer in the p-region is protected by the BSG layer and is not corroded by the alkaline solution. For the n-region on the back side of the silicon substrate, since no laser treatment has been performed, the surface PSG layer protects the phosphorus diffusion layer from damage during the wet texturing process. For the isolation region on the back side of the silicon substrate, the PSG layer extending to the surface of the phosphorus doping layer protects the bottom phosphorus doping layer from damage. In the gap region, since the surface PSG layer is removed by laser, the bottom phosphorus doping layer can be simultaneously cleaned during the alkaline texturing process until the oxide layer interface formed by UV oxidation stops (the phosphorus diffusion layer remains undamaged, thus providing conductivity), thereby forming a polished surface gap structure. Furthermore, in the non-extended phosphorus-doped layer region of the isolation zone and the interstitial region (when the interstitial surface is designed as a pyramidal textured surface), a pyramidal textured surface can be formed simultaneously during the texturing process. After texturing, the texturing tank is subsequently equipped with an acid (HF) washing tank to further remove the residual PSG layer, BSG layer, and oxide layer on the silicon substrate surface, ultimately achieving the disconnection of p-poly and n-poly on the silicon substrate surface, while the bottom diffusion layer of the passivation layer forms a p-region and n-region conductive structure.

[0081] In some preferred embodiments, the alkaline washing and texturing conditions are: KOH solution concentration 1.5–1.8 wt%, temperature 80–85°C, and time 6–12 min. The acid washing conditions are: HF solution concentration in the acid washing tank 20–40 wt%, and time 60–200 s.

[0082] S13, double-sided coating.

[0083] In some preferred embodiments, an ALD (Al₂O₃) deposition method is used to deposit passivation and antireflection films on both sides of the treated silicon substrate. The ALD-deposited passivation and antireflection films on the treated silicon substrate are formed by the reaction of Al(CH₃)₃ with water vapor, with a thickness of 8–10 nm, and the process temperature is controlled at 220–280 °C. Subsequently, a tubular PECVD (Pipeline PECVD) device is used to deposit SiN on both sides of the silicon substrate. x The film has a thickness of 80–120 nm and a refractive index of 1.9–2.1. The reaction gases in the tubular cavity are SiH4 and NH3. The working pressure is 1500–1700 mTorr, the power is 10000–15000 W, the temperature is 400–600 °C, the SiH4 gas flow rate is 900–2000 sccm, the NH3 gas flow rate is 7000–12000 sccm, and the deposition time is 5–20 min.

[0084] S14, screen printing, sintering, photoinjection.

[0085] In some preferred embodiments, the double-sided coated silicon substrate is screen-printed onto the back side to form electrodes, which are then sintered at high temperature to form Ag-Si ohmic contacts. Finally, the finished battery is obtained by photoinjection repair. Specific Implementation Example 1 (the gap area is a polished surface) A back-contact battery heat-spot protection structure, such as Figures 1-3 As shown (in this embodiment, the passivation layer is a tunneling oxide layer), it includes: a silicon substrate 1, with alternating p-regions and n-regions on the back side, and an isolation region between the p-regions and n-regions; The p-region surface is sequentially provided with a passivation layer 2, a boron doped layer 3, and an electrode 6; The surface of the n-region is sequentially provided with a passivation layer 2, a phosphorus doping layer 4, and an electrode 6; An extended phosphorus-doped layer 9, connected to the phosphorus-doped layer and extending towards the boron-doped layer, is located on the surface of the isolation region. A gap 10 (a polished surface, 1 / 5 the width of the total width of the isolation region) is provided between the extended phosphorus-doped layer and the boron-doped layer. A passivation layer 2 and a phosphorus diffusion layer 7 (located between the silicon substrate and the passivation layer in this region) are sequentially located at the bottom of the extended phosphorus-doped layer. A phosphorus diffusion layer 7 is located at the bottom of the gap. A boron diffusion layer 8 (located between the p-region silicon substrate and the passivation layer) is located at the bottom of the p-region passivation layer. A phosphorus diffusion layer (located between the n-region silicon substrate and the passivation layer) is located at the bottom of the n-region passivation layer. The remaining surface of the isolation region is a pyramidal textured surface 5. The phosphorus diffusion layer and the boron diffusion layer are connected to form a conductive channel.

[0087] Example 2 A method for preparing a back contact battery heat-preventing structure (Example 1) includes the following steps: S1, placing the N-type silicon substrate cut by diamond wire into an alkaline polishing bath for double-sided polishing, maintaining the temperature at 75°C for 6 minutes, polishing thickness of about 4 μm, and thinning amount of 0.42 g.

[0088] S2, UV laser oxidation of the n-region, extended phosphorus doped layer, and pre-defined interstitial region, forming an oxide layer in this region, such as... Figure 4 As shown. The conditions for the ultraviolet laser were: laser wavelength 355nm, power 7W, processing time 3.5s, and oxide layer thickness approximately 12nm.

[0089] S3. A passivation layer and an i-poly-Si layer are deposited on the back side in a single deposition. The deposition conditions for the passivation layer are: LPCVD, O2 flow rate 40000 sccm, temperature 600℃, time 600s, and the passivation layer thickness is approximately 3nm. The deposition conditions for the i-poly-Si layer are: LPCVD, SiH4 flow rate 920 sccm, temperature 550℃, time 3.3h, working gas pressure 300mTorr, and the i-poly-Si layer thickness is approximately 290nm.

[0090] S4, Boron diffusion; This transforms the inner and outer layers of the i-poly-Si layer into boron-doped and BSG layers, respectively, and simultaneously transforms the surface layer of the silicon substrate in all regions into a boron-diffused layer, such as... Figure 5 As shown. The conditions for boron diffusion were: boron diffusion temperature 850℃, diffusion time 10 min, BCl3 flow rate 200 sccm, O2 flow rate 1200 sccm; oxidation propulsion temperature 950℃, O2 flow rate 7000 sccm, propulsion time 30 min, and the thickness of the resulting BSG layer was approximately 45 nm.

[0091] S5. Laser removal of the BSG layer in the preset areas of the n-zone and isolation zone prepares the ground for subsequent alkaline washing. The laser conditions are: laser wavelength 532nm, frequency 600KHz, marking speed 45000mm / s, power 50W, and processing time 3s.

[0092] S6. Alkaline washing removes the boron-doped and passivation layers in the n-region and the preset isolation region; acid washing removes the oxide layer. Alkaline washing removes the boron-doped and passivation layers in the S5 laser-treated area. Because the silicon substrate surface in the n-region, extended phosphorus-doped layer, and the preset gap (i.e., polished surface) region has a pre-existing oxide layer, the alkaline solution cannot penetrate the oxide layer to corrode the underlying silicon substrate. Simultaneously, the boron-doped layer in the non-laser-treated area is protected by a BSG layer, effectively preventing damage during alkaline washing. Subsequently, the oxide layer (which is alkali-resistant but not acid-resistant) is removed using the low-concentration acid (HF) bath integrated into the alkaline washing tank. The BSG layer on the surface of the boron-doped layer in the non-laser-treated area is thicker, so only a small portion is removed, with most remaining. The alkaline washing conditions are: KOH solution concentration 2.0 wt%, temperature 80℃; the acid washing conditions are: HF solution concentration in the acid washing tank 5 wt%, time 40 seconds.

[0093] S7. A pre-defined area is formed by secondary oxidation using ultraviolet laser to create an oxide layer, followed by annealing. Figure 6 As shown. The ultraviolet laser conditions were: laser wavelength 355nm, power 25W, processing time 7s, and oxide layer thickness approximately 15nm. The annealing conditions were: tubular annealing, inert gas N2 atmosphere, annealing temperature 980℃, 30min.

[0094] S8. Secondary deposition of passivation layer and i-poly-Si layer on the back side. The deposition conditions for the passivation layer are: LPCVD, O2 flow rate 40000 sccm, temperature 600℃, time 600s, and the passivation layer thickness is approximately 3nm; the deposition conditions for the i-poly-Si layer are: LPCVD, SiH4 flow rate 920 sccm, temperature 550℃, time 3.3h, working gas pressure 300mTorr, and the i-poly-Si layer thickness is approximately 290nm.

[0095] S9, Phosphorus diffusion; This transforms the inner and outer layers of the i-poly-Si layer into phosphorus-doped and PSG-doped layers, respectively, and simultaneously transforms the boron diffusion layers in the isolation region and the preset n-region into phosphorus-diffused layers, such as... Figure 7 As shown. The conditions for phosphorus diffusion are as follows: First, a mixed gas of POCl3 and O2 is introduced at a temperature of 790℃ for a diffusion time of 20 min, with a flow rate of POCl3 carried by nitrogen of 1100 sccm and an O2 flow rate of 700 sccm; then, O2 is introduced for oxidation propulsion at a temperature of 890℃ for a propulsion time of 40 min, with an O2 flow rate of 3000 sccm, resulting in a PSG layer with a thickness of approximately 42 nm.

[0096] S10, laser removal of the PSG layer in the pre-defined area of ​​the non-extended phosphorus doped layer in the p-region and isolation region, lays the groundwork for subsequent S12 alkaline washing texturing and acid washing. The laser conditions are: laser wavelength of 532nm, frequency of 600KHz, marking speed of 45000mm / s, power of 25W, and processing time of 2.7s.

[0097] S11, Removal of Wrap-on Plating: A chain etching machine is used to remove the wrap-on plating layer on the front and sides of the silicon substrate. The volume ratio of hydrofluoric acid solution to nitric acid solution in the acid bath is 1:4, with the concentration of hydrofluoric acid solution being 49wt% and the concentration of nitric acid solution being 69wt%. The belt speed is 1.3m / min.

[0098] S12. Alkaline texturing followed by acid washing to remove residual PSG, BSG, and oxide layers. The alkaline texturing conditions are: KOH solution concentration 1.7wt%, temperature 82℃, time 7min; the acid washing conditions are: HF solution concentration 30wt%, time 120s. The silicon substrate with the removed coating is placed in the alkaline texturing bath for integrated wet cleaning and texturing. Since the front side of the silicon substrate has no oxide areas after the coating is removed, a pyramidal textured surface can be formed during texturing. For the p-region on the back side of the silicon substrate, the outermost PSG layer, phosphorus doping layer, and passivation layer can be washed away during wet texturing. The boron doped layer in the p-region is protected by the BSG layer and is not damaged by alkaline corrosion. For the n-region on the back side of the silicon substrate, since no laser treatment is performed, the surface PSG layer protects the phosphorus diffusion layer from damage during wet texturing. For the isolation region on the back side of the silicon substrate, the extended PSG layer on the surface of the phosphorus-doped layer protects the underlying phosphorus-doped layer from damage. In the interstitial region, due to laser removal of the surface PSG layer, the underlying phosphorus-doped layer can be simultaneously cleaned during alkaline texturing until the oxide layer interface formed by UV oxidation stops (the phosphorus diffusion layer remains intact, thus providing conductivity). Furthermore, after texturing the non-extended phosphorus-doped region of the isolation area, a pyramidal textured surface can be formed simultaneously during the texturing process. The texturing tank subsequently includes an acid (HF) washing tank to further remove residual PSG, BSG, and oxide layers from the silicon substrate surface, ultimately achieving a disconnect between the p-poly and n-poly connections on the silicon substrate surface, while the bottom diffusion layer of the passivation layer forms a p-region and n-region conductive structure.

[0099] S13. Double-sided Coating: A passivation and antireflection films are deposited on both sides of the treated silicon substrate using ALD deposition. The ALD-deposited passivation and antireflection films on the treated silicon substrate are formed by the reaction of Al(CH3)3 with water vapor, with a thickness of approximately 8 nm, and the process temperature is controlled at 250℃. Subsequently, SiN is deposited on both sides of the silicon substrate using a tubular PECVD system. x The film has a thickness of approximately 82 nm and a refractive index of 1.95. The reaction gases in the tubular cavity are SiH4 and NH3. The working pressure is 1600 mTorr, the power is 12000 W, the temperature is 450℃, the SiH4 gas flow rate is 1300 sccm, the NH3 gas flow rate is 11000 sccm, and the deposition time is 10 min.

[0100] S14, screen printing, sintering, and photoinjection: The double-sided coated silicon substrate is screen printed onto the back side to form electrodes, which are then sintered at high temperature to form Ag-Si ohmic contacts. Finally, the substrate is repaired by photoinjection to obtain the finished battery.

[0101] Example 3 (the only difference from Example 2 is that the gap area is a pyramid-patterned textured surface) The difference in the preparation method lies in steps S7 and S12; the remaining steps are the same as in Example 2. S7. A secondary oxidation process using ultraviolet laser is performed in the pre-defined gap area to form an oxide layer, followed by annealing. The ultraviolet laser conditions are: laser wavelength 355nm, power 3W, processing time 2.3s, and oxide layer thickness approximately 5nm. The annealing conditions are: tubular annealing, inert gas N2 atmosphere, annealing temperature 980℃, 30min.

[0102] S12. Alkaline texturing followed by acid washing to remove residual PSG, BSG, and oxide layers. The alkaline texturing conditions are: KOH solution concentration 1.7wt%, temperature 82℃, time 7min; the acid washing conditions are: HF solution concentration 30wt%, time 120s. The silicon substrate with the removed coating is placed in the alkaline texturing bath for integrated wet cleaning and texturing. Since the front side of the silicon substrate has no oxide areas after the coating is removed, a pyramidal textured surface can be formed during texturing. For the p-region on the back side of the silicon substrate, the outermost PSG layer, phosphorus doping layer, and passivation layer can be washed away during wet texturing. The boron doped layer in the p-region is protected by the BSG layer and is not damaged by alkaline corrosion. For the n-region on the back side of the silicon substrate, since no laser treatment is performed, the surface PSG layer protects the phosphorus diffusion layer from damage during wet texturing. For the isolation region on the back side of the silicon substrate, the PSG layer extending the surface of the phosphorus-doped layer can protect the underlying phosphorus-doped layer from damage. In the oxide layer region between the extended phosphorus-doped layer and the boron-doped layer, the surface PSG layer is removed by laser, allowing simultaneous cleaning of the underlying phosphorus-doped layer during alkaline texturing. However, because the oxide layer formed by this ultraviolet laser is relatively thin, it cannot effectively protect the underlying phosphorus-doped layer from damage during wet texturing, thus forming a pyramidal textured surface, albeit with less corrosion compared to the isolation regions on either side. After texturing, the texturing tank is further equipped with an acid (HF) washing tank to remove the remaining PSG, BSG, and oxide layers on the silicon substrate surface, ultimately achieving a disconnect between the p-poly and n-poly connections on the silicon substrate surface, while the bottom diffusion layer of the passivation layer forms a p-region and n-region conductive structure.

[0103] Comparative Example 1 The only difference between Comparative Example 1 and Example 2 is that the extended phosphorus-doped layer is directly connected to the opposite boron-doped layer (i.e., without gaps, such as...). Figure 8 (As shown).

[0104] Performance testing The electrical performance of the solar cells prepared in each embodiment and comparative example was tested, and the data are shown in the table below: Serial number η (%) V oc (mV) J sc (mA / cm 2 )]]> FF (%) Irev2 Example 2 26.82 745.3 42.57 84.53 1.84 Example 3 26.69 744.9 42.45 84.42 1.61 Comparative Example 1 Example 4 26.64 744.8 42.40 84.35 3.52 Firstly, regarding Example 2, since the gap region is a polished surface, the conduction design of the p-region and n-region is located in their respective tunneled SiO2.x At the bottom of the layer, compared to the direct through-hole design in Comparative Example 1, this design achieves both hot spot prevention and reduced short-circuit leakage current (Irev2). Furthermore, since there is no poly-Si at this gap location, the overall poly area on the back of the battery is reduced, resulting in less parasitic absorption of incident light and improved optical performance (J). sc The performance of Example 2 is better than that of Example 3 (where the gap area has a pyramidal textured surface). Secondly, compared to Example 3 (where the gap area has a polished surface), the internal reflection effect of this area is better than that of the pyramidal textured surface, resulting in the best overall battery performance. Example 3, compared to Comparative Example 1, further reduces the risk of short-circuit conduction and parasitic absorption of poly-Si, thus its performance is also better than Comparative Example 1. However, in the process of Example 3, the conductive parts are prone to excessive wet etching, making it impossible to form a more effective conductive structure. This increases the risk that the module cannot resist hot spots, thus its overall performance is weaker than that of Example 2.

[0105] Unless otherwise specified, the raw materials and equipment used in this invention are all commonly used in the field; unless otherwise specified, the methods used in this invention are all conventional methods in the field.

[0106] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any simple modifications, alterations, and equivalent transformations made to the above embodiments based on the technical essence of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A back-contact battery heat-prevention structure, characterized in that... include: The silicon substrate has alternating p-regions and n-regions on its back side, with an isolation region between the p-regions and n-regions; A boron-doped layer is disposed on the surface of the p-region; A phosphorus-doped layer is disposed on the surface of the n-region; At least one extended phosphorus doped layer is disposed on the surface of the isolation region, connected to the phosphorus doped layer, extending toward the boron doped layer and having a gap between it and the boron doped layer; Conductive channels are located at the bottom of the boron-doped layer, the phosphorus-doped layer, the phosphorus-doped layer, and the gap.

2. The back contact battery heat-prevention structure according to claim 1, characterized in that: The conductive channel is formed by connecting a boron diffusion layer and a phosphorus diffusion layer; A phosphorus diffusion layer is provided at the bottom of the phosphorus doped layer and the extended phosphorus doped layer; The bottom of the boron-doped layer is provided with a boron diffusion layer; A phosphorus diffusion layer is provided at the bottom of the gap.

3. The back contact battery heat-prevention structure according to claim 1, characterized in that: The gap is a polished surface or a pyramidal velvet surface; The surface of the non-extended phosphorus-doped layer and the non-interstitial region of the isolation zone is a pyramidal textured surface. The width of the gap is 1 / 10 to 4 / 5 of the total width of the isolation zone.

4. A method for preparing a back contact battery heat-resistant structure according to any one of claims 1-3, characterized in that... include: An oxide layer is formed by oxidizing the n-region, the extended phosphorus doped layer, and the pre-defined interstitial region with ultraviolet laser in a single step. Backside passivation layer and i-poly-Si layer are deposited; Boron diffusion; Remove the BSG layer from the preset areas of region n and the isolation region; One alkaline wash removes the boron-doped layer and passivation layer from the preset areas of the n-region and isolation region; one acid wash removes the oxide layer. Pre-defined gap area for secondary oxidation by ultraviolet laser, followed by annealing; Backside passivation layer and i-poly-Si layer are deposited; Phosphorus diffusion; Remove the PSG layer from the preset regions of the non-extended phosphorus doped layer in the p-region and isolation region; Remove the plating; The process involves two alkaline washings for flocking and two acid washings.

5. The preparation method according to claim 4, characterized in that: The conditions for the ultraviolet laser oxidation are: laser wavelength 300~400 nm, power 5~100 W, processing time 1~20 s, and the thickness of the resulting oxide layer 2~50 nm.

6. The preparation method according to claim 4, characterized in that: The conditions for boron diffusion are as follows: boron diffusion temperature 800–950℃, diffusion time 5–50 min, BCl3 flow rate 50–500 sccm, O2 flow rate 500–2000 sccm; oxidation propulsion temperature 900–1050℃, O2 flow rate 5000–30000 sccm, propulsion time 30–80 min, and the thickness of the resulting BSG layer is 30–70 nm.

7. The preparation method according to claim 4, characterized in that: The conditions for the first alkaline wash are: KOH solution concentration 1.7~2.2 wt%, temperature 75~85℃; The conditions for the first pickling are: the concentration of HF solution in the pickling tank is 1~10 wt%, and the time is 30~60 s.

8. The preparation method according to claim 1 or 5, characterized in that: The gap is a polished surface; the conditions for the ultraviolet laser secondary oxidation are: laser wavelength 300~400 nm, power 20~100 W, processing time 5~20 s, and the resulting oxide layer thickness 5~50 nm; or The gap is a pyramidal textured surface; the conditions for the ultraviolet laser secondary oxidation are: laser wavelength 300~400 nm, power 2~10 W, processing time 1~5 s, and the thickness of the resulting oxide layer 1~10 nm.

9. The preparation method according to claim 4, characterized in that: The annealing conditions are as follows: tubular annealing, inert gas atmosphere, annealing temperature of 800~1050℃, 10~60 min.

10. The preparation method according to claim 4, characterized in that: The phosphorus diffusion conditions are as follows: first, a mixed gas of POCl3 and O2 is introduced at a temperature of 750~850℃ for a diffusion time of 5~30 min, with a flow rate of POCl3 carried by N2 of 500~1200 sccm and an O2 flow rate of 500~1000 sccm; then, O2 is introduced for oxidation propulsion at a temperature of 850~950℃ for a propulsion time of 20~60 min and an O2 flow rate of 1000~10000 sccm, resulting in a PSG layer with a thickness of 30~70 nm.

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