Efficient PWM modulator with interpolation

Abstract

The present invention is in the field of underlying electronic circuits, in particular to digital signal processors for streaming audio applications, more particularly to pulse width modulators, integrated circuits comprising said electronic circuits, and devices (e.g., audio devices) comprising said electronic circuits or said integrated circuits.

Description

Technical Field

[0001] This invention belongs to the field of basic electronic circuits, and more specifically, relates to a digital signal processor for streaming audio applications, and more specifically, to a pulse width modulator, an integrated circuit including the electronic circuit, and a device including the electronic circuit or the integrated circuit (e.g., an audio device).

[0002] Related applications

[0003] This application claims priority to Dutch patent application NL2034425, filed on March 25, 2023, in the name of Axign IP BV of the Netherlands.

[0004] The entire contents of the foregoing application and all priority documents referenced in any existing or future application data sheets filed with this application are incorporated herein by reference for all purposes. Background Technology

[0005] This invention relates, in one aspect, to a digital controller that outputs a pulse width modulation (PWM) signal. It also relates to embodiments that use feedback of the output signal to correct for any errors. Furthermore, it relates to embodiments where the feedback signal originates from the output of an analog-to-digital converter (ADC) to create a "mixed-signal PWM controller."

[0006] The primary application of this type of controller is in audio amplifiers, where the PWM signal can be used to drive a switching (Class D) amplifier. An output filter is typically placed after the switching amplifier to eliminate high-frequency switching components and produce a smooth output signal. This output signal can then be fed to a speaker. The ADC in this type of controller is able to measure the signal directly at the speaker (i.e., after the output filter). Subsequently, a digital controller can be further configured, for example, with high loop gain, to suppress signal non-ideals that may occur in the switching amplifier and output filter.

[0007] Traditionally, switched amplifiers either use no feedback at all or use an analog feedback loop that provides feedback before the output filter. These analog systems typically have only moderate filter complexity (most commonly a second-order loop filter). Research has found that this results in lower loop gain and worse non-ideal suppression of the switched amplifier, and even no suppression of non-ideals originating from the output filter at all.

[0008] An audio power amplifier comprises basic electronic circuitry that amplifies low-power audio signals entering the circuitry to a sufficiently high power to drive loudspeakers. Audio power amplifiers have a wide range of applications. They can be integrated into electronic components or chains of electronic circuits, each performing an individual task or participating in a collective task. Essentially, any audio signal can be supplied to a power amplifier, which is common practice. The output signal power of an audio amplifier can range from less than a few watts to tens or hundreds of watts, and sometimes even several times that. Power amplifiers are typically integrated into (final) products or integrated circuits.

[0009] Design parameters for audio power amplifiers include frequency response, gain, noise, and distortion, which are often interdependent.

[0010] Class D amplifiers are commonly used in modern consumer electronics audio products, subwoofers, and sound reinforcement systems. Amplifiers can include filters, preamplifiers, power output stages, etc. Audio filters are typically frequency-dependent circuits. They are designed to operate within a specific audio frequency range. Note that the human hearing range is generally considered to be from 20 Hz to 20,000 Hz. However, there is considerable individual variation, especially at high frequencies. Furthermore, there is a general decrease in sensitivity to high frequencies with age. Additionally, sensitivity to specific frequencies may also vary with said frequency. Therefore, the audio frequency range commonly used in audio amplifiers is approximately 20 Hz to 20 kHz, and sometimes up to 40 kHz or even 100 kHz. Audio filters are configured to amplify, pass through, or attenuate a specific frequency range. Many types of filters exist (e.g., low-pass filters, high-pass filters, band-pass filters, and full-pass filters, etc., which affect the phase of a given frequency component).

[0011] Analog pulse width modulators do not have limitations on quantization step size, but are constrained by typical analog technology drawbacks (e.g., chip area, power consumption, offset, mismatch, etc.) and require digital-to-analog conversion before the modulator. Digital pulse width modulators have extremely low power consumption and are easy to implement in digital ICs, but their performance is severely limited by quantization noise due to the finite time granularity constrained by the system clock frequency.

[0012] When pulse width modulators (PWMs) are used in applications where signal-to-noise ratio (SNR) is critical (e.g., in Class D amplifiers), PWM resolution is a limiting factor for system performance. In the prior art, increasing the system clock frequency reduces the time step and improves resolution. This comes at a high cost, as power consumption increases rapidly as the clock frequency approaches its technical limits.

[0013] Figure 1An exemplary prior art analog Class D system is illustrated, featuring feedback before or after an LC filter (or both). The resolution of the analog pulse width modulator is unlimited, effectively providing an infinite pulse width granularity.

[0014] Figure 2 An exemplary digital counterpart of the system is shown when used in an IC. The limited resolution of the digital pulse width modulator leads to quantization noise sources in the system.

[0015] Figure 3 A typical digital pulse width modulator is shown. The digital carrier (stepped carrier) is generated by digital logic operating on a system clock. The system clock frequency is limited by the capabilities of CMOS technology.

[0016] In computing and electronic processing, clock rate (also known as clock speed) refers to the frequency (in Hz) at which the processor's clock generator can produce pulses. These pulses are typically used to synchronize the operation of various components. They clearly indicate the processor's speed. Clock rates gradually increase from kHz to GHz over time.

[0017] Figure 4 The effect of quantization on the PWM signal relative to its analog counterpart is illustrated. Theoretically, comparing the input signal to a continuous triangular wave should not produce errors, but the discrete PWM carrier introduces quantization errors, resulting in delay.

[0018] By increasing the carrier resolution, quantization error can be reduced, such as... Figure 5 As shown. Quantization error is shaped outside the audio band in feedback-based implementations, but error suppression is typically limited by a finite amount of loop gain. Lower quantization noise will improve the signal-to-noise ratio. Due to power and area limitations on the chip, increasing the clock frequency to tens or hundreds of MHz is not always an attractive option.

[0019] Incidentally, US2004 / 222866A1 describes a digital technique for pulse width modulation (PWM) that utilizes a tapped delay line to receive a reference clock and generate multiple reference clock transitions with a finer time resolution than the reference clock signal. A multiplexer receives the multiple time-delayed reference clock transitions as its input and produces an output when one of the multiple time-delayed reference clock transitions is addressed. An accumulator circuit generates a control timing signal associated with the input signal sampling rate Fsample, which is used to select the output representing the pulse width modulation output signal from delay line 304.

[0020] The purpose of this invention is to overcome the shortcomings of existing pulse width modulators and amplifiers without compromising functionality and advantages. Summary of the Invention

[0021] In a first aspect, the present invention relates to an electronic circuit (1) for pulse width modulation, comprising: at least one clock generator (60) configured to provide an operating clock speed for a coarse time grid, specifically wherein the coarse time grid is provided to an input signal; at least one digital pulse width modulator (DPWM) (10) configured to receive the input and configured to provide an output to at least one delay line (20) and an interpolator (30) of at least one interpolation circuit (100), wherein the at least one interpolation circuit (100) comprises: at least one delay line (DL) (20) configured to provide an output individually to at least one edge selector (4), The DL includes a delay controller (21) configured to control the delay of at least one DL and configured to provide an output to at least one edge selector (40); at least one interpolator (30) configured to receive inputs from DPWM, from a digital carrier generator, and from a digital PWM modulator, and to provide an interpolated output to at least one edge selector (40), wherein the interpolator (30) includes a step detector configured to detect an increase in the carrier signal exceeding that of the input signal; and at least one edge selector (40) configured to provide a time-quantized PWM output, specifically, wherein quantization is provided at a frequency higher than that of at least one clock generator. The carrier signal and the input signal are configured to "cross" or "intersect" each other, and the step detector is configured to detect a change in the carrier signal when the carrier signal intersects with the input signal. Consistent with the detection of an increase, a decrease can be detected; in the context of this circuit, "increase" or "decrease" is actually related to the positive or negative sign of the signal, etc. This electronic circuit can be used in low-power amplifiers (e.g., amplifiers as low as 10mW), such as headphones consuming ~10mW, stereo systems consuming ~1kW, and PA systems, motor control, and RF systems consuming ~1MW. Furthermore, a pulse width modulator (PWM) (which can be an on-chip PWM) that increases effective resolution using interpolation is proposed. On-chip pulse width modulation (PWM) can be implemented in both analog and digital modes. This invention avoids the need to increase the system clock frequency by interpolating the coarse PWM signal. Interpolation is achieved using delay lines and edge-selection logic. The delay lines can be implemented by a DLL or reused from an existing PLL (e.g., an on-chip PLL). This invention is based on... Figure 3The diagram illustrates a pulse width modulator (PWM) and additionally provides an interpolation system. Interpolation is achieved by measuring the magnitude of the error between the input signal and the carrier signal and calculating the required delay within one system clock cycle; this is designed to be the smallest digital time step achievable by the carrier. Therefore, any type or form of carrier signal can be used. Furthermore, it can be different or the same in each (subsequent) clock cycle. An equivalent delay code is then used to select specific edges from the delay line that are locked to the clock frequency of the PWM (typically the same clock as the rest of the chip) in some way. This basic principle is illustrated in Figure 6. This invention can be applied to any application that uses digital pulse width modulation and requires reduced quantization noise. Most notably, this will include applications with relatively high-speed PWM where conventional clock resolution is insufficient for high-quality PWM (e.g., in audio applications, RF amplifiers, motor controllers, microcontrollers, etc.). Therefore, this invention uses relatively low power and is also relatively simple in design. Figure 2 In similar embodiments, one aspect of the invention relates to a digital controller that outputs a pulse width modulation (PWM) signal. The invention also relates to embodiments that use feedback of the output signal to correct for any errors. Furthermore, the invention relates to embodiments where the feedback signal originates from the output of an analog-to-digital converter (ADC) to create a "mixed-signal PWM controller."

[0022] This electronic circuit can "feed" multiple PWM modulators using a single delay line ("scalability of multiple PWM channels on a single chip, eliminating the need for unnecessary component reuse"). Instead of relying on a dedicated "DLL" (similar to existing technologies) designed for PWM modulators, it relies on a "PLL" that initially provides a clock with a "coarse" time grid for the entire chip (the "system clock" can have a lower frequency), making the entire chip relatively economical in terms of power consumption. The delay line (deployed as a "ring oscillator" within the PLL) is then used to select the PWM edges with a finer time grid. The values ​​of the PWM error signal "error" (the difference between the input and the carrier), the coarse PWM signal "coarse PWM," and the carrier signal "carrier" are available on the "coarse" time grid. The "interpolator" also calculates on the coarse time grid which edge of the delay line / ring oscillator the "edge selector" should select (see...). Figure 13 ).

[0023] In the context of this application, the phrase "at least one of..." is considered to primarily include the option "one". In its simplest form, the identified element appears only once. However, stacked structures (e.g., Axign's AX5689 chip) can be considered. These stacked structures can be viewed as parallel structures. Similarly, serial structures can be considered. Therefore, the phrase "at least one of..." covers such more complex structures, which are, in some way, multiplexed structures. The claims cover simple embodiments of the invention.

[0024] The term "quantization" involves the subdivision of a quantum. Therefore, quantization provides discrete values, also known as "quanta." A quantum is any very small discrete increment that forms the smallest or smallest unit into which the value of a physical quantity (or parameter) increases or decreases. In this invention, the physical parameter being quantized is time.

[0025] This delay-line locked loop (commonly referred to as a "delay-locked loop") is considered only one implementation method for controlling the delay of a delay line. Essentially, the requirement for a delay line is that N delays equal one clock cycle or a portion thereof, for example, equal to half a clock cycle when using two edges of a clock. Several methods exist to make the delay of a delay line equal to one clock cycle, and using a DLL is one of them. In this embodiment, the inventors also used an associated PLL.

[0026] This electronic circuit also relates in some respects to elements mentioned in the prior art, which can be combined with other aspects; this also applies to other aspects of the invention.

[0027] In a second aspect, the present invention relates to a delay line (20) for an electronic circuit, wherein the delay line (20) is configured to provide an output individually to at least one edge selector (40), wherein the DL includes a controller (21) configured to control the delay of the DL and configured to provide an output to at least one edge selector (40).

[0028] Another aspect of the invention relates to a pulse width interpolator (30) for an electronic circuit, wherein the interpolator (30) is configured to provide an interpolation output to at least one edge selector (40) and receive an error signal from at least one digital pulse width modulator (DPWM) (10) and an input from a digital PWM modulator, and an input from a digital carrier generator 80. The interpolator (30) includes: a step detector configured to detect an increase in the carrier signal exceeding that of the input signal; and specifically a comparator configured to compare the value of the carrier signal with the value of the input signal and provide an error signal; and a converter configured to convert the error signal into an integer value based on the number of quantization time grid elements and the magnitude and step size of the error signal.

[0029] Another aspect of the present invention relates to an integrated circuit including an electronic circuit according to the present invention, or a delay line (20) according to the present invention, or an interpolator (30) according to the present invention.

[0030] Another aspect of the present invention relates to an electronic device including an integrated circuit according to the invention or an electronic circuit according to the invention, specifically, wherein the electronic device is a product, more specifically, wherein the product is selected from audio amplifiers, active loudspeaker systems, active noise reduction systems, high-speed closed-loop controllers, high-resolution low-latency data converters, A / D converters, power controllers, RF amplifiers, motor controllers (specifically, high-speed motor controllers), industrial controllers, microcontrollers, digital audio converters, digital amplifier controllers, and combinations thereof.

[0031] Therefore, the present invention provides a solution to one or more of the above-mentioned problems.

[0032] The advantages of this description are explained in detail throughout. Detailed Implementation

[0033] The present invention relates, in a first aspect, to electronic circuits.

[0034] In an exemplary embodiment of this electronic circuit, the controller (21) is configured to provide a delay-locked loop with a fine DL time grid, the fine DL time grid being 1 / N smaller than the coarse time grid of at least one clock generator, specifically, where N∈[2,2]. 10 In other words, a coarse time grid is provided to quantize it into a fine time grid of 1 / N of the quantum of the coarse time grid (such as that provided by a clock generator).

[0035] In an exemplary embodiment of this electronic circuit, at least one DL (20) is selected from analog delay lines and digital delay lines, specifically, an analog delay line.

[0036] In an exemplary embodiment of this electronic circuit, at least one DL (20) is controlled by a locking loop selected from a delay-locked loop (DLL) (35) and a phase-locked loop (PLL) (36).

[0037] In an exemplary embodiment of the present electronic circuit, at least one DL (20) is part of a DLL (35), wherein the DLL (35) includes a phase frequency detector (PFD) (26) configured to receive inputs from at least one clock generator (60) and from the DL (20), and a loop filter (27) configured to receive inputs from the PFD and provide outputs to at least one DL (20).

[0038] In an exemplary embodiment of this electronic circuit, at least one DL (20) is part of a PLL (36), wherein the PLL (36) includes a phase frequency detector (PFD) (26) configured to receive inputs from at least one clock generator (60) and from the DL (20), a loop filter (27) configured to receive inputs from the PFD and provide outputs to at least one DL (20), and specifically, wherein the outputs of at least one DL are configured to be fed back to their inputs to form at least one oscillator (21a), specifically, at least one n-stage ring oscillator.

[0039] In an exemplary embodiment of this electronic circuit, at least one oscillator (21a) and at least one clock generator (60) are one and the same.

[0040] In an exemplary embodiment, this electronic circuit includes 2-M DPWMs (10), specifically, where M∈[2,2... 6 ].

[0041] In an exemplary embodiment, the electronic circuit includes a DL (20). In an exemplary embodiment, the electronic circuit includes an edge selector (40).

[0042] In an exemplary embodiment of this electronic circuit, at least one interpolator (30) includes a step size detector configured to detect an increase in the carrier signal exceeding that of the input signal, a comparator configured to compare the value of the carrier signal with the value of the input signal and provide an error signal, and a converter configured to convert the error signal into an integer value based on the number of quantization time grid elements and the magnitude and step size of the error signal.

[0043] In an exemplary embodiment of this electronic circuit, at least one clock generator (60) is configured to provide an operating clock speed of 5MHz-20GHz, specifically 10MHz-5GHz, more specifically 30MHz-1GHz, and even more specifically 50MHz-100MHz.

[0044] In an exemplary embodiment, the electronic circuit further includes at least one digital carrier generator (80) configured to receive input from at least one clock generator (60), and at least one adder (90) configured to receive input from at least one digital carrier generator (80) and provide output to at least one digital pulse width modulator (DPWM) (10) and at least one interpolator (30). Specifically, each individual digital carrier generator is configured to provide output to a plurality of DPWMs and / or interpolators, specifically, the plurality being 2-2. 10 (For example, 2) 2 -2 8 ).

[0045] Although the invention has been described in detail in an exemplary context, it can be better understood in conjunction with the accompanying examples and drawings. Attached Figure Description

[0046] Figures 1-15 Details of this digital signal processor and its various aspects are shown.

[0047] The accompanying drawings are exemplary in nature. The elements in the drawings can be combined.

[0048] In the attached image:

[0049] 1 Electronic Circuits

[0050] 10 Digital Pulse Width Modulator

[0051] 20 delay lines

[0052] 21 controllers

[0053] 21a oscillator

[0054] 26-phase frequency detector

[0055] 27-loop filter

[0056] 30PWM interpolator

[0057] 35 Delay Locking Ring

[0058] 36 phase-locked loops

[0059] 40 edge selector

[0060] 60 clock generator

[0061] 80 digital carrier generator

[0062] 90 adders

[0063] 100 interpolation circuit

[0064] Figure 1 A typical implementation of an analog Class D amplifier is shown.

[0065] Figure 2 An Axign digital Class D amplifier is shown.

[0066] Figure 3 A typical pulse width modulator is shown.

[0067] Figure 4 A comparison of time-continuous carriers and time-discrete carriers used to generate PWM signals is shown.

[0068] Figure 5The effect of increasing the digital PWM resolution on PWM delay error is shown.

[0069] Figure 6a , Figure 6b A digital pulse width modulator with an additional interpolation system is shown. Further illustrated, a digital carrier generator is configured to provide a carrier output to interpolator 30.

[0070] Figure 7 (Top) An example implementation of a digital PWM modulator with interpolation logic is shown. Figure 7 (Bottom) An example implementation of the interpolation logic required to predict and select the correct delayed edge based on the difference between the coarse-quantized PWM and the error signal from the digital PWM modulator is shown. Zero crossings can be detected in the error signal when an intersection occurs between the input signal and the carrier signal. The sign of the error signal is used to output logic "1" when positive and logic "0" when negative. As described above, the digital carrier generator provides an output signal to a step size detector configured to provide an output in the form of a step size, and similarly, n is divided by the step size and then output to a multiplier; or similarly, the output is output to a divider for dividing the input * n by the step size.

[0071] A circuit with a flip-flop combined with an XOR gate can be used. This circuit generates an enable pulse to capture the digital value of the error signal into a register.

[0072] The captured error signal can be converted into a fine control word by subtracting the captured error signal from the step size of the digital carrier waveform generated by the system clock. The result is normalized to the step size, and its absolute value is taken to obtain a value in the range of 0 to 1. Then, this value is multiplied by the number of fine quantization steps "n" in the clock cycle of the system clock and rounded down to obtain an integer in the range of 0 to n-1.

[0073] The mathematical operations are as follows:

[0074] Fine control = floor(n*abs((step size - error) / step size))

[0075] It can be rewritten as:

[0076] Fine control = (n-1) - floor(abs(A*error))

[0077] Where A = n / step size.

[0078] The extra "-1" comes from removing n and the minus sign from the mathematical floor operation. Note that the final delay associated with a fine PWM edge versus a coarse PWM edge is:

[0079] Delay = n / step size * abs (step size - error)

[0080] Figure 8 Interpolation of a coarse PMM signal using delay lines and selector logic is shown. Figure 8 The interpolation operation is illustrated in more detail. A delay line with n elements (each providing a delay of ∆T) is tuned such that the signals at the beginning and end of the delay line match the coarse PWM grid and are limited by the system clock rate. Due to the principle of interpolation, the coarse time step of the system clock is subdivided into n isochronous steps ∆T. The coarse PWM signal is fed into this delay line, and then, based on digital interpolation logic, one of these (delay) paths is selected, thereby reducing the minimum time step of the PWM modulator and thus increasing the number of possible pulse widths.

[0081] Figure 9 An example of an "edge selector" circuit is shown. Figure 9 An example of edge selector logic that can be used to select the correct delayed PWM signal based on fine control codes generated by interpolation logic is shown. The invention can also be integrated with system-level DLLs or PLLs (typically already implemented on the IC), as shown below. Figure 10 and Figure 11 As shown. In this case, the coarse PWM signal is not used as an input to the delay line, but rather a more comprehensive edge selector is used because the delay line or ring oscillator is locked to the same phase as the digital PWM modulator. Figure 12 The document also provides examples for these selector blocks.

[0082] Figure 10 The method demonstrates the generation of n edges using a single DLL locked to the system clock. Multiple (m) PWM subsystems can use the same edges for interpolation, proving the scalability of the solution.

[0083] Figure 11 This demonstrates the use of a single ring oscillator-based PLL as a source of interpolation edges, which can be utilized by multiple (m) PWM subsystems.

[0084] Figure 12 An example implementation of an edge selector using a PLL ring oscillator as the source of the interpolation time grid is shown.

[0085] Figure 13 An exemplary multi-channel controller is illustrated. A reference clock input provides a clock signal to a PLL, the fine grid of which is provided to multiple edge selectors. Multi-channel digital inputs (e.g., audio sources) are provided to digital control circuitry, which provides inputs to multiple DPWM modulators that receive the clock signal from the PLL. Each DPWM modulator provides an output to an interpolator, as shown in Figure 6 and... Figure 7 As described in the diagram, each interpolator provides fine control to each edge selector. Then, an output PWM output m is provided.

[0086] Figure 14 An exemplary embodiment of a pseudo-differential ring oscillator is shown, where n=8. The pseudo-differential ring oscillator operates by cascading pseudo-differential delay units, each capable of outputting a time-delayed version of the input signal. This time delay can be manipulated by a control signal such as "vctrl". An oscillating signal is generated during typical operation by cascading multiple delay units as shown, with the output of the last delay unit connected inversely to the first delay unit. Each output of the pseudo-differential ring oscillator contains a slightly delayed version of this oscillating signal. If the oscillating signal on a single output is considered as the "system clock" on a coarse time grid, the multiple other outputs can be considered as time-delayed versions of the system clock, thus producing a fine time grid.

[0087] Figure 15 An exemplary embodiment of a single pseudo-differential delay line cell, which may be referred to as a "Helleputte" cell, is shown. This cell can be described as a system of two coupled CMOS inverters with two inputs (in+ and in-) and two outputs (out+ and out-). An inverter is a circuit whose output is logically inverted compared to its inputs. By coupling these inverters, their outputs will change state simultaneously even if the inputs do not switch simultaneously. A time delay between the inputs and outputs of the coupled inverters can be generated by limiting the rate at which the gate-source capacitors charge or discharge. A series PMOS transistor connecting the coupled inverters to the power supply regulates the rate of the output rising edge transition, and a series NMOS transistor between the coupled inverters and ground regulates the rate of the output falling edge transition. The amount of regulation is controlled by manipulating the voltage at the "vctrl" node. To limit the capacitive load on the output node (which affects circuit performance), the inverters are placed to isolate and buffer signals used by other circuits, such as edge selectors.

Claims

1. An electronic circuit (1) for pulse width modulation, comprising: A clock generator (60) is configured to provide an operating clock speed for a coarse time grid, specifically, wherein the coarse time grid is provided to the input signal. A digital pulse width modulator (DPWM) (10) is configured to receive input and to provide output to the delay line (20) and interpolator (30) of the interpolation circuit (100). The interpolation circuit (100) includes: A delay line DL (20) is configured to provide an output to an edge selector (40), wherein the DL includes a delay controller (21) configured to control the delay of the DL and configured to provide an output to the edge selector (40). An interpolator (30) is configured to receive inputs from the DPWM and error signals from the digital PWM modulator, and to provide an interpolated output to the edge selector (40), wherein the interpolator (30) includes a step size detector configured to detect an increase in the carrier signal exceeding that of the input signal, and The edge selector (40) is configured to provide a time-quantized PWM output.

2. The electronic circuit for pulse width modulation according to claim 1, wherein, The delay controller (21) is configured to provide a delay-locked loop with a DL fine-quantization time grid, wherein the DL fine-quantization time grid is 1 / N of the coarse time grid of the clock generator, specifically, where N∈[2,2]. 10 ].

3. The electronic circuit for pulse width modulation according to any one of claims 1 to 2, wherein, The DL (20) is selected from analog delay lines and digital delay lines, specifically, analog delay lines.

4. The electronic circuit for pulse width modulation according to any one of claims 1 to 3, wherein, The DL (20) is configured to be controlled by a locking loop selected from a delayed locking loop DLL (35) and a phase-locked loop PLL (36).

5. The electronic circuit for pulse width modulation according to claim 4, wherein, The DL (20) is part of the DLL (35), and the DLL (35) includes a phase frequency detector PFD (26) configured to receive inputs from the clock generator (60) and from the DL (20), and a loop filter (27) configured to receive inputs from the PFD and provide an output to the DL (20).

6. The electronic circuit for pulse width modulation according to claim 4, wherein, The DL (20) is part of a PLL (36), wherein the PLL (36) includes a phase frequency detector PFD (26) configured to receive inputs from the clock generator (60) and from the DL (20), and a loop filter (27) configured to receive inputs from the PFD and provide an output to the DL (20), wherein the output of the DL is configured to be fed back to its input to form an oscillator (21a), specifically an n-stage ring oscillator.

7. The electronic circuit for pulse width modulation according to claim 6, wherein, The oscillator (21a) and the clock generator (60) are one and the same.

8. The electronic circuit for pulse width modulation according to any one of claims 1 to 7, comprising 2-M DPWMs (10), specifically, wherein, M∈[2,2 6 ]。 9. The electronic circuit for pulse width modulation according to any one of claims 1 to 8, comprising a DL (20).

10. The electronic circuit for pulse width modulation according to any one of claims 1 to 9, comprising an edge selector (40).

11. The electronic circuit for pulse width modulation according to any one of claims 1 to 10, wherein, The interpolator (30) includes a comparator and a converter, the comparator being configured to compare the value of the carrier signal with the value of the input signal and provide an error signal, and the converter being configured to convert the error signal into an integer value based on the number of quantization time grid elements and the magnitude and step size of the error signal.

12. The electronic circuit for pulse width modulation according to any one of claims 1 to 11, wherein, The clock generator (60) is configured to provide an operating clock speed of 5MHz-20GHz, specifically, 10MHz-5GHz, more specifically, 30MHz-1GHz, and even more specifically, 50MHz-100MHz.

13. The electronic circuit for pulse width modulation according to any one of claims 1 to 12, further comprising a digital carrier generator (80) and an adder (90), the digital carrier generator (80) being configured to receive an input from the clock generator (60), the adder (90) being configured to receive an input from the digital carrier generator (80) and provide an output to the digital pulse width modulator DPWM (10) and the interpolator (30).

14. Delay line (20) for electronic circuits, wherein, The delay line (20) is configured to provide an output to an edge selector (40), wherein the DL includes a controller (21) configured to control the delay of the DL and configured to provide an output to the edge selector (40).

15. A pulse width interpolator (30) for electronic circuits, wherein, The interpolator (30) is configured to provide an interpolation output to the edge selector (40) and receive inputs from the digital pulse width modulator (DPWM) (10) and an error signal from the digital PWM modulator, and includes a step detector configured to detect that the increase of the carrier signal exceeds the input signal, specifically including a comparator configured to compare the value of the carrier signal with the value of the input signal and provide an error signal, and a converter configured to convert the error signal into an integer value based on the number of quantization time grid elements and the magnitude and step size of the error signal.

16. An integrated circuit comprising an electronic circuit according to any one of claims 1 to 13, or a delay line (20) according to claim 14, or an interpolator (30) according to claim 15.

17. An electronic device comprising the integrated circuit according to claim 16, or the electronic circuit according to any one of claims 1 to 13, wherein, The electronic device is a product, and more specifically, the product is selected from audio amplifiers, active speaker systems, active noise reduction systems, high-speed closed-loop controllers, high-resolution low-latency data converters, A / D converters, power controllers, RF amplifiers, motor controllers, industrial controllers, microcontrollers, digital audio converters, digital amplifier controllers, and combinations thereof, wherein the motor controller is specifically a high-speed motor controller.

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