Core head apparatus equipped with x-ray imaging system and method for semiconductor package alignment

Abstract

The invention provides a die head apparatus and method for semiconductor package alignment equipped with an X-ray imaging system. The semiconductor package alignment apparatus includes: a radiation source emitting radiation to a plurality of semiconductor chips; a radiation sensor detecting radiation passing through the plurality of semiconductor chips; a head coupled with one of the radiation source and the radiation sensor; an alignment portion that aligns and bonds the plurality of semiconductor chips based on detection information acquired by the radiation sensor; and a processor controlling at least one of the radiation source, the head, the radiation sensor, the alignment portion, and any combination thereof, where the processor identifies a second semiconductor chip to be coupled to a first semiconductor chip of the plurality of semiconductor chips coupled to at least a portion of the head based on identification of the first semiconductor chip, and control at least one of the head portion, the alignment portion, and any combination thereof to match a first reference mark included in the first semiconductor chip and a second reference mark included in the second semiconductor chip.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0065088, filed on May 20, 2024, and Korean Patent Application No. 10-2024-0141332, filed on October 16, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a chiplethead alignment apparatus and method for aligning semiconductor packages with an X-ray imaging system. Background Technology

[0004] With the development of artificial intelligence technology, research and development of AI modules are ongoing. Therefore, research on miniaturizing individual chips through process miniaturization and technologies that can realize multifunctional chips by packaging chips with various functions are attracting attention in the field of AI modules. Furthermore, advanced packaging technologies are being actively developed, represented by a hybrid approach of vertical stacking techniques for securing high-capacity wafers or chips.

[0005] To address this, 2.5D / 3D integration technologies using silicon interposers and through-silicon vias (TSVs) have been developed. However, to date, if semiconductor chips are bonded (during chip-to-chip bonding), methods have been employed that use optical methods to identify the bonding location, remember the bonding location, and perform mechanical bonding. Alternatively, methods can be used where a die head equipped with an optical system identifies alignment marks on the exterior of the lower die and aligns and attaches the upper die to the lower die. Summary of the Invention

[0006] This disclosure is intended to solve the aforementioned problems in the prior art while fully retaining the advantages of the prior art implementation.

[0007] One aspect of this disclosure provides a semiconductor packaging alignment apparatus and method, which improves bonding accuracy and thus semiconductor production yield by detecting radiation sources during the bonding of multiple semiconductor chips and by continuously performing fine alignment on the semiconductor chips.

[0008] Another aspect of the present disclosure provides a high-precision X-ray chip alignment head for a semiconductor chiplet, which can align an attachment surface of a semiconductor chip that can not be visually recognized, while recognizing interconnections or TSVs of attached upper / lower chips using X-ray vision, and an alignment method using the same.

[0009] Still another aspect of the present disclosure provides a semiconductor package alignment apparatus and method for relatively improving alignment precision, improving package yield, thereby reducing production costs, and improving price competitiveness, compared to bonding based on an optical alignment method.

[0010] Still another aspect of the present disclosure provides a semiconductor package alignment apparatus and method for preventing an alignment mark of an optical system located outside a chiplet head from losing an area of a lower chip, thereby increasing package integration, thereby reducing production costs and improving price competitiveness.

[0011] Still another aspect of the present disclosure provides a semiconductor package alignment apparatus and method capable of accurately bonding interconnections or miniaturized TSVs as the number of bonding members per unit area of an upper chip and a lower chip increases, thereby improving the yield of semiconductor chips.

[0012] Still another aspect of the present disclosure provides a method that can be used even in a bump process according to the related art, but can accurately detect bonding members during hybrid bonding, which is a next-generation technology that will be used if interconnections or TSVs are miniaturized as the number of bonding members increases, thereby improving yield and improving the performance of semiconductors.

[0013] Still another aspect of the present disclosure provides a semiconductor chip package alignment apparatus and method for irradiating low-dose radiation or transmitting radiation only to a partial area where an alignment mark and / or a TSV is located, rather than an entire semiconductor chip area, thereby preventing damage to a semiconductor chip.

[0014] Technical problems to be solved by the present disclosure are not limited to the above-mentioned problems, and any other technical problems not mentioned herein will be clearly understood by those skilled in the art from the following description.

[0015] According to an aspect of the disclosure, a semiconductor package alignment apparatus includes a radiation source that emits radiation toward a plurality of semiconductor chips; a head coupled to at least a portion of the radiation source and causing at least one of movement, rotation, and any combination thereof of the radiation source; a radiation sensor that detects the radiation passing through the plurality of semiconductor chips; an alignment portion that aligns and joins the plurality of semiconductor chips based on detection information acquired by the radiation sensor; and a controller that controls at least one of the radiation source, the head, the radiation sensor, the alignment portion, and any combination thereof, wherein the processor identifies a second semiconductor chip of the plurality of semiconductor chips to be coupled to a first semiconductor chip of the plurality of semiconductor chips based on identification of the first semiconductor chip of the plurality of semiconductor chips coupled to at least a portion of the head, and the processor controls at least one of the head, the alignment portion, and a combination thereof to match a first reference mark included in the first semiconductor chip and a second reference mark included in the second semiconductor chip. BRIEF DESCRIPTION OF DRAWINGS

[0016] The above and other objects, features and advantages of the present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 An example of a block diagram related to a semiconductor package core particle alignment apparatus according to an embodiment of the present disclosure is illustrated;

[0018] Figure 2 is a schematic diagram illustrating an example of a semiconductor package core particle alignment apparatus according to an embodiment of the present disclosure;

[0019] Figure 3A and Figure 3B An example of an arrangement of a semiconductor chip package alignment apparatus according to an embodiment of the present disclosure is illustrated;

[0020] Figure 4A An example of matching an image of an alignment mark according to an embodiment of the present disclosure is illustrated;

[0021] Figure 4B An example of matching an image of a TSV according to an embodiment of the present disclosure is illustrated;

[0022] Figure 5 An example of a flowchart related to a semiconductor package alignment method according to an embodiment of the present disclosure is illustrated; and

[0023] Figure 6 An example of a flowchart related to a semiconductor package alignment method according to an embodiment of the present disclosure is illustrated. DETAILED DESCRIPTION

[0024] In the following, some embodiments of the present disclosure will be described in detail with reference to the exemplary accompanying drawings. When adding reference numerals to components in each drawing, it should be noted that even if the same or equivalent components are shown in other drawings, they are represented by the same numbers. Furthermore, in describing embodiments of the present disclosure, a detailed description will be omitted if it is determined that a detailed description of a related known configuration or function would interfere with the understanding of the embodiments of the present disclosure.

[0025] Furthermore, in describing components of embodiments of this disclosure, terms such as first, second, "A", "B", (a), and (b) may be used. These terms are intended only to distinguish one component from others, and they do not limit the nature, order, or sequence of the components. Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0026] In the following text, reference will be made to Figures 1 to 6 The embodiments of this disclosure are described in detail.

[0027] Figure 1 An example block diagram relating to a semiconductor package die alignment apparatus according to an embodiment of the present disclosure is shown.

[0028] refer to Figure 1 According to embodiments of the present disclosure, a semiconductor packaging alignment apparatus 100 may include a processor 110, a radiation source 120, a head 130, a radiation sensor 140, and an alignment unit 150. The processor 110, radiation source 120, head 130, radiation sensor 140, or alignment unit 150 may be electrically connected and / or operatively connected to each other via electronic components including a communication bus.

[0029] In the following description, operatively coupled hardware may include states where direct and / or indirect connections are established between hardware via wired and / or wireless means, such that the second hardware is controlled by the first hardware within the hardware. Although different boxes are shown, embodiments are not limited thereto.

[0030] The semiconductor package alignment apparatus 100 according to an embodiment may include hardware for processing data based on one or more instructions. The hardware for processing data may include a processor 110.

[0031] For example, the hardware used for processing data may include an arithmetic and logic unit (ALU), a floating-point unit (FPU), a field-programmable gate array (FPGA), a central processing unit (CPU), and / or an application processor (AP). The processor 110 may include a single-core processor architecture or a multi-core processor architecture, including dual-core, quad-core, hexa-core, or octa-core processors.

[0032] The following description may include operations performed by the processor 110 controlling other hardware. For example, the operation of the radiation source 120 emitting radiation may include the operation of the radiation source 120 being controlled by the processor 110 to emit radiation. For example, the processor 110 may control at least one of the radiation source 120, head 130, radiation sensor 140, alignment unit 150, and any combination thereof.

[0033] For example, processor 110 can control at least one of radiation source 120, head 130, radiation sensor 140, alignment unit 150, and any combination thereof to align a plurality of semiconductors arranged perpendicularly to a reference plane.

[0034] In this embodiment, radiation source 120 can emit radiation toward a plurality of semiconductor chips. Radiation source 120 may include a device that emits radiation due to the decay of a radioactive element or an X-ray generating device that allows at least one of a material, accelerated electrons, and any combination thereof to collide with a target to generate X-rays. Semiconductor package alignment device 100 may include shielding in directions other than the direction in which the plurality of semiconductor chips are located, so that radiation emitted from radiation source 120 is radiated onto the plurality of semiconductor chips.

[0035] For example, a plurality of semiconductor chips may include semiconductor chips. For example, a semiconductor chip may include volatile memory, including at least one of dynamic random access memory (DRAM), static random access memory (SRAM), and any combination thereof. For example, a semiconductor chip may include non-volatile memory, including at least one of phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), and any combination thereof.

[0036] For example, alignment device 100 can fabricate artificial intelligence semiconductors by bonding multiple chips with different functions to a single master chip. For example, alignment device 100 can fabricate high-bandwidth memory (HBM) by stacking a single layer of memory semiconductors.

[0037] Each of the multiple semiconductor chips may include a semiconductor device, which comprises multiple individual devices. These multiple individual devices may include a variety of microelectronic devices. For example, the multiple individual components may include: metal-oxide-semiconductor field-effect transistors (MOSFETs) containing complementary metal-oxide-semiconductor (CMOS) transistors, system-scale integrated circuits (LSIs), image sensors containing CMOS imaging sensors (CISs), microelectromechanical systems (MEMSs), active components, and / or passive components.

[0038] Multiple semiconductor chips may include logic semiconductor chips and / or memory semiconductor chips. For example, logic semiconductor chips may include application processors (APs), microprocessors, central processing units (CPUs), controllers, graphics processing units (GPUs), neural processing units (NPUs), high-bandwidth memory (HBMs), field-programmable gate arrays (FPGAs), and / or application-specific integrated circuits (ASICs).

[0039] For example, embodiments of the present invention can also be used in processes for connecting an upper chip to an interposer in a chip-on-wafer-on-substrate (CoWoS) process or for connecting an interposer to which the upper chip is coupled to a main substrate. Embodiments of the present invention can be used in processes for attaching various semiconductor chips (including chip-on-chip (CoC) and / or chip-on-wafer (CoW) processes) to at least one of another chip, an interposer, a substrate, and any combination thereof.

[0040] For example, radiation source 120 may include an X-ray source. X-rays may include wavelengths from 0.01 nm to 10 nm. Since X-rays contain minimal errors caused by the thickness of the semiconductor chip and penetrate the semiconductor chip, radiation sensor 140 can detect radiation passing through the semiconductor chip. Therefore, even in semiconductor packaging processes measured in nm (including μm), semiconductor package alignment device 100 can identify the alignment of semiconductor chips, and thus can reduce the defect rate due to alignment errors between semiconductor chips and can significantly increase yield.

[0041] In an embodiment, the head 130 may be coupled to at least a portion of the radiation source 120. For example, the head 130 may be coupled to at least a portion of the radiation source 120 to cause the radiation source 120 to move, rotate, and at least one combination thereof.

[0042] In this embodiment, the head 130 and the radiation source 120 can be arranged to face each other. For example, the head 130 can be positioned above the semiconductor to be aligned, and the radiation source 120 can be positioned below the semiconductor to be aligned. If the head 130 is positioned on the upper side and the radiation source 120 is positioned on the lower side, a radiation sensor 140 for detecting the radiation from the radiation source 120 can be coupled to the head 130.

[0043] In one embodiment, the radiation sensor 140 can detect radiation passing through a plurality of semiconductor chips. The radiation sensor 140 may include a detector for detecting radiation. For example, the radiation sensor 140 can detect radiation by detecting changes in current and / or voltage resulting from collisions with particles (e.g., photons) emitted from the radiation source 120.

[0044] For example, multiple semiconductor chips can be arranged perpendicularly to a reference plane. For example, the reference plane can include ground. However, embodiments of this disclosure are not limited to those described above.

[0045] For example, radiation source 120 can be located above the uppermost semiconductor chip in a plurality of semiconductor chips.

[0046] For example, the radiation sensor 140 may be located below the bottommost semiconductor chip among a plurality of semiconductor chips.

[0047] For example, radiation sensor 140 can detect the current caused by collisions with particles emitted from radiation source 120. The integral value of the current detected by radiation sensor 140 can be proportional to the radiation energy incident on radiation sensor 140.

[0048] In an embodiment, the radiation sensor 140 may acquire detection information based on the detected radiation passing through the plurality of semiconductor chips. For example, the detection information may include the coefficient rate of radiation, radiation energy, and at least one of any combination thereof. However, embodiments of this disclosure are not limited to those described above.

[0049] For example, radiation sensor 140 can detect radiation in a specific region comprising multiple semiconductor chips. For example, radiation sensor 140 can detect the coefficient rate of radiating particles incident on a detection point in the specific region. If light is perpendicularly radiated onto multiple semiconductor chips, the multiple semiconductor chips can be included in the generated phase region. For example, if the phase region is generated by perpendicularly radiating light onto multiple semiconductor chips, radiation sensor 140 can generate visualization information (e.g., an image) based on the coefficient rate of each point.

[0050] For example, the radiation sensor 140 can use shading effects to generate visual information. For instance, as the coefficient of the radiation sensor 140 increases, a relatively large amount of radiation passes through, and therefore the corresponding area can be displayed with a color that has high brightness; conversely, as its coefficient of magnitude decreases, a relatively small amount of radiation passes through, and therefore the corresponding area can be displayed with a color that has low brightness. However, embodiments of this disclosure are not limited to those described above.

[0051] In an embodiment, the radiation sensor 140 may include a resolution in nm, which includes a resolution in μm.

[0052] In one embodiment, the processor 110 can control the head 130 using detection information acquired by the radiation sensor 140. For example, the processor 110 can align multiple semiconductor chips based on the control of the head 130 using the detection information.

[0053] The semiconductor packaging alignment apparatus 100 according to an embodiment may further include a lower plate located below a lower semiconductor chip, which is located at the lowermost side of a plurality of semiconductor chips and is in contact with at least a portion of the lower semiconductor chip.

[0054] For example, processor 110 can control the lower board using detection information acquired by radiation sensor 140. For example, processor 110 can align multiple semiconductor chips based on control of the lower board using the detection information acquired by radiation sensor 140.

[0055] For example, each of a plurality of semiconductor chips may include at least one of alignment marks, through-silicon vias (TSVs), and any combination thereof.

[0056] For example, the detection information may include positional information associated with at least one of the alignment mark, TSV, and any combination thereof. For example, at least one of the alignment mark, TSV, and any combination thereof may be formed of a material with a radiation transmittance lower than a specified value.

[0057] For example, alignment marks, TSVs, and at least one of any combination thereof can be formed of a material including at least one of nickel, tin, and any combination thereof, and have low X-ray transmittance and high X-ray absorptivity.

[0058] In this case, if the radiation sensor 140 detects radiation passing through the multiple semiconductor chips, then no radiation is detected or undetectable in the portion corresponding to the location where the alignment mark and / or TSV are formed, thus the location information of the alignment mark and TSV of each of the multiple semiconductor chips 231 and 233 can be identified.

[0059] Therefore, the semiconductor chip packaging alignment apparatus 100 can align multiple semiconductor chips 231 and 233 by matching the positions of alignment marks (or phases) or matching the positions of TSVs (or phases). For example, the semiconductor packaging alignment apparatus 100 can align multiple semiconductor chips by controlling the head 130.

[0060] In an embodiment, processor 110 may control alignment unit 150 based on position information associated with at least one of alignment marks, TSVs, and any combination thereof. For example, processor 110 may align multiple semiconductor chips by controlling alignment unit 150 based on position information associated with at least one of alignment marks, TSVs, and any combination thereof.

[0061] In an embodiment, the processor 110 can match the phase of an alignment mark or the phase of a TSV based on control of the alignment unit 150, using position information associated with at least one of the alignment mark, TSV, and any combination thereof. For example, the processor 110 can align multiple semiconductor chips by matching the phase of the alignment mark or the phase of the TSV.

[0062] The semiconductor packaging alignment apparatus 100 according to an embodiment may further include a camera for acquiring images of a plurality of semiconductor chips.

[0063] For example, a camera may include one or more optical sensors (e.g., charge-coupled device (CCD) sensors and CMOS sensors) that generate electrical signals indicating the color and / or brightness of light. Multiple optical sensors included in a camera may be arranged in a two-dimensional array.

[0064] A camera can acquire electrical signals from multiple optical sensors essentially simultaneously to generate an image or frame that corresponds to the light arriving at the optical sensors in a two-dimensional array, comprising multiple pixels arranged in a two-dimensional pattern. For example, photographic data captured by a camera can represent multiple images obtained from the camera.

[0065] In one embodiment, the processor 110 can control the radiation source 120 to radiate radiation onto a designated area based on the position of at least one of alignment marks, TSVs, and any combination thereof obtained from the camera.

[0066] In an embodiment, radiation source 120 can be configured to radiate radiation to a designated area based on the position of alignment marks and / or TSVs obtained from the camera.

[0067] For example, radiation may affect semiconductor devices included in a semiconductor chip due to the excitation of at least some electrons during the radiative transfer process. Semiconductor devices may correspond to sensitive components, and therefore, if radiation from radiation source 120 passes through them, the semiconductor device may be damaged. Therefore, the semiconductor package alignment device 100 can prevent damage to the semiconductor chip by directing radiation to a portion of the alignment marks and / or TSVs located, rather than the entire area of ​​the semiconductor chip. The designated area, set based on the position of the alignment marks and / or TSVs obtained from a camera, may include the portion of the alignment marks and / or TSVs located within them.

[0068] For example, designated regions can be set differently in multiple semiconductor chips, and these designated regions can be set to include the locations of alignment marks and / or TSVs included in each of the multiple semiconductor chips. Each alignment mark and / or each TSV included in each of the multiple semiconductor chips can be formed to include the same coordinates on a plane perpendicular to the direction in which the radiation is radiated.

[0069] According to an embodiment, the semiconductor packaging alignment apparatus 100 can optically align multiple semiconductor chips based on the positions of multiple semiconductor chips primarily captured by a camera.

[0070] The semiconductor package alignment apparatus 100 according to an embodiment may further include a memory. For example, the memory may include a storage device.

[0071] For example, the semiconductor package alignment device 100 may store in memory coordinate values ​​indicating the position of each alignment mark and / or each TSV in each of a plurality of semiconductor chips.

[0072] For example, the processor 110 of the semiconductor package alignment apparatus 100 can control the head 130 and / or the alignment section 150 based on the stored coordinate values ​​indicating the position of alignment marks and / or TSVs to align multiple semiconductor chips.

[0073] For example, processor 110 can align multiple semiconductor chips primarily based on coordinate values ​​stored in memory, and can finely align multiple semiconductor chips by using radiation source 120.

[0074] The semiconductor package alignment apparatus 100 according to this embodiment may also include a display. For example, the display can provide visual information to a user. For instance, the display can be controlled by at least one of a processor 110, a GPU, and any combination thereof to output visual information.

[0075] The semiconductor package alignment apparatus 100 according to an embodiment may further include an operation unit for manipulating the alignment unit 150. For example, the operation unit may control the alignment unit 150 based on input received from a user. For example, the operation unit may send a signal corresponding to the input to the processor 110 based on the input received from the user. The processor 110, which receives the signal corresponding to the input, may control the alignment unit 150.

[0076] For example, the processor 110 can output detection information to the user via a display. For example, the processor 110 can control the alignment unit 150 based on input received from the control unit.

[0077] In an embodiment, processor 110 can identify a first semiconductor chip among a plurality of semiconductor chips that is coupled to at least a portion of head 130. For example, processor 110 can identify a second semiconductor chip among a plurality of semiconductor chips that will be coupled to the first semiconductor chip. For example, processor 110 can identify a second semiconductor chip among a plurality of semiconductor chips that will be coupled to the first semiconductor chip based on the identification of the first semiconductor chip among a plurality of semiconductor chips that is coupled to at least a portion of head 130.

[0078] For example, radiation source 120 can detect radiation passing through multiple semiconductor chips, and head 130 can be coupled to one of the radiation source and radiation sensor.

[0079] In this embodiment, the processor 110 can control at least one of the head 130, the alignment portion 150, and any combination thereof to align a first reference mark included in a first semiconductor chip and a second reference mark included in a second semiconductor chip with each other. For example, the first reference mark may include at least one of a first alignment mark, a first TSV, and any combination thereof. For example, the second reference mark may include at least one of a second alignment mark, a second TSV, and any combination thereof.

[0080] In this embodiment, the processor 110 may control at least one of the head 130, the alignment portion 150, and any combination thereof to match a first TSV included in a first semiconductor chip and a second TSV included in a second semiconductor chip. In another embodiment, the processor 110 may control at least one of the head 130, the alignment portion 150, and any combination thereof to match a first alignment mark included in a first semiconductor chip and a second alignment mark included in a second semiconductor chip.

[0081] In an embodiment, the processor 110 may control the head 130, the alignment portion 150, and at least one of any combination thereof, which are included in the first semiconductor chip, the first alignment mark, and any combination thereof, to couple (or attach) the first semiconductor chip and the second semiconductor chip based on the matching of at least one of the first TSV, the first alignment mark, and any combination thereof included in the first semiconductor chip with each other, and the second TSV, the second alignment mark, and any combination thereof included in the second semiconductor chip.

[0082] Figure 2 This is a schematic diagram illustrating an example of a semiconductor package die alignment apparatus according to an embodiment of the present disclosure.

[0083] refer to Figure 2 According to an embodiment, the semiconductor packaging alignment apparatus 200 (e.g., Figure 1 The semiconductor packaging alignment device 100 may include a radiation source 220 and a head 230.

[0084] The processor of the semiconductor packaging alignment apparatus 200 according to the embodiment (e.g., Figure 1 The processor 110 in the middle can control the alignment part (e.g., Figure 1 The alignment section 150 is used to align multiple semiconductor chips 231 and 233.

[0085] For example, the processor can rotate the head 230 about the optical axis 225 of the radiation source 220 to align with a plurality of semiconductor chips 231 and 233. Although the rotation of the head 230 about the optical axis 225 of the radiation source 220 has been described, the embodiments are not limited thereto. For example, the processor can rotate the head 230 about the central axis of the head 230 to align with a plurality of semiconductor chips 231 and 233.

[0086] For example, the processor can move the head 230 on at least one of the x-axis, y-axis, z-axis, and any combination thereof. For example, the processor can move the head 230 on at least one of the x-axis, y-axis, z-axis, and any combination thereof to align a plurality of semiconductor chips 231 and 233.

[0087] For example, multiple semiconductor chips 231 and 233 may include alignment marks 241, 242, 251 and 252.

[0088] For example, the processor can control the head 230 to match the first alignment mark 241 included in the first semiconductor chip 231 and the second alignment mark 251 included in the second semiconductor chip 233.

[0089] For example, multiple semiconductor chips 231 and 233 can be arranged perpendicularly to the reference surface 270. For example, multiple semiconductor chips 231 and 233 can be arranged perpendicularly to be parallel to the reference plane 270.

[0090] For example, the processor can control the head 230 based on detection information obtained from the radiation source 220 to align a plurality of semiconductor chips 231 and 233 arranged vertically relative to the reference plane 270.

[0091] For example, the processor can control the head 230 to match the third alignment mark 242 included in the first semiconductor chip 231 and the fourth alignment mark 252 included in the second semiconductor chip 233.

[0092] For example, the processor can rotate the head 230 in a first direction d1. For example, the processor can rotate the head 230 in the first direction d1 to align the first semiconductor chip 231 and the second semiconductor chip 233. For example, if viewed from above, the first direction d1 may include a direction in which the head 230 rotates counterclockwise based on a reference axis perpendicular to the reference plane 270. However, embodiments of this disclosure are not limited to those described above.

[0093] According to this embodiment, the semiconductor packaging alignment apparatus 200 may further include a lower plate 260. For example, the semiconductor packaging alignment apparatus 200 may control the lower plate 260 to align the first semiconductor chip 231 and the second semiconductor chip 233.

[0094] For example, the semiconductor packaging alignment device 200 can control the lower plate 260 to align the first semiconductor chip 231 and the second semiconductor chip 233 based on the detection information obtained by the radiation source 220.

[0095] Figure 3A and Figure 3B An example of the arrangement of a semiconductor chip package alignment apparatus according to an embodiment of the present disclosure is shown.

[0096] Figure 4A An example of an image with matching alignment marks according to an embodiment of the present invention is described.

[0097] Figure 4B An example of an image matching TSV according to an embodiment of this disclosure is shown.

[0098] refer to Figure 3A and Figure 3B Packaging alignment device (e.g., Figure 1 Semiconductor packaging alignment device 100 and / or Figure 2The semiconductor packaging alignment device 200 can align multiple semiconductor chips 311, 313, 361, and 363 in a vertically arranged state.

[0099] For example, among the plurality of semiconductor chips 311, 313, 361, and 363, the first semiconductor chip 311 may be positioned closer to the radiation source 300 than the second semiconductor chip 313. For example, among the plurality of semiconductor chips 311, 313, 361, and 363, the second semiconductor chip 313 may be positioned closer to the radiation sensor 330 than the first semiconductor chip 311.

[0100] For example, each of the plurality of semiconductor chips 311, 313, 361, and 363 may include at least one of alignment marks, TSVs, and any combination thereof. For example, all of the plurality of semiconductor chips 311, 313, 361, and 363 may include alignment marks, or all of the plurality of semiconductor chips 311, 313, 361, and 363 may include TSVs.

[0101] For example, alignment marks may include marks formed in specific areas of each semiconductor chip to align multiple semiconductor chips 311, 313, 361 and 363.

[0102] For example, the TSV may include a through-hole formed such that the semiconductor chips are electrically connected if they are bonded. The TSV can be connected to electrodes inside the plurality of semiconductor chips 311, 313, 361, and 363 through fine holes in the semiconductor chips 311, 313, 361, and 363 to transmit electrical signals. Prior to the packaging process using a semiconductor chip packaging alignment apparatus, at least one of alignment marks, TSVs, and any combination thereof can be generated in a process including an exposure process and / or a deposition process. However, embodiments of this disclosure are not limited to those described above.

[0103] At least one of alignment marks, TSVs, and any combination thereof may be formed at a specific location on each of the plurality of semiconductor chips 311, 313, 361, and 363 to align the plurality of semiconductor chips 311, 313, 361, and 363. For example, a semiconductor package alignment apparatus may form alignment marks such that the plurality of semiconductor chips 311, 313, 361, and 363 are aligned if the positions (or phases) of the alignment marks match. For example, a semiconductor package alignment apparatus may form TSVs such that the plurality of semiconductor chips 311, 313, 361, and 363 are aligned if the positions (or phases) of the TSVs match.

[0104] refer to Figure 3AThe first semiconductor chip 311 may include a first alignment mark 321. The second semiconductor chip 313 may include a second alignment mark 323.

[0105] The first alignment mark 321 and the second alignment mark 323 may include complementary shapes to identify whether the positions of the first alignment mark 321 and the second alignment mark 323 match each other. As an example, in Figure 4A In this configuration, the first alignment mark 401 may include a cross shape, and the second alignment mark 403 may include a quadrilateral shape. For example, the processor may determine whether the phase of the first alignment mark 401 is in contact with the phase of the second alignment mark 403, and control the head (e.g., Figure 1 The head 130 and / or Figure 2 The head 230 is aligned with the positions of the first semiconductor chip 311 and the second semiconductor chip 313.

[0106] For example, the first semiconductor chip 311 may include interconnects or TSV 321-1. For example, the second semiconductor chip 313 may include interconnects or TSV 323-2.

[0107] For example, the processor can use the interconnect of the first semiconductor chip 311 or TSV 321-1 and the interconnect of the second semiconductor chip 313 or TSV 323-1 as reference marks to align the first semiconductor chip 311 and the second semiconductor chip 313.

[0108] refer to Figure 3B The first semiconductor chip 361 may include a first TSV 371. The second semiconductor chip 363 may include a second TSV 373. For example, the first TSV 371 and the second TSV 373 may be formed at substantially the same location to vertically connect the first TSV 371 and the second TSV 373, and thus align the first semiconductor chip 361 and the second semiconductor chip 363. As an example, in Figure 4B In this configuration, the first TSV and the second TSV may include cylindrical structures. For example, when viewed from the outside, the cylindrical structure may be formed as a quadrilateral or a circle, and its shape is not limited to these.

[0109] Return to reference Figure 3B For example, the phase of the first TSV 371 and the phase of the second TSV 373 detected by the radiation sensor 370 can overlap with each other. For example, based on the radiation radiated from the radiation source 350 and passing through the first semiconductor chip 361 and the second semiconductor chip 363, and the detection information obtained by the radiation sensor 370, the processor can control the head to align with the first semiconductor chip 361 and the second semiconductor chip 363. Figure 3BThe text describes a radiation sensor 370, but the semiconductor package alignment device may include a lower plate that includes the radiation sensor 370, and a detector may be included in the lower plate.

[0110] For example, the alignment device may include a head 355. For example, the head 355 may be referred to as a core head. For example, the head 355 may include a radiation source or a detector.

[0111] Reference Figure 4B The first example 410 may include an example in which a first connection portion 411, including a first interconnect and / or a first TSV, is not aligned with a second connection portion 413, including a second interconnect and / or a second TSV. The second example 420 may include an example in which the first connection portion 421 and the second connection portion 423 are aligned.

[0112] In this embodiment, the processor of the alignment device can change the state of the first connection portion 411 and the second connection portion 413 from an unaligned state to an aligned state, and can engage the semiconductor chip in the changed state.

[0113] Figure 5 An example of a flowchart relating to a semiconductor package alignment method according to an embodiment of the present invention is shown.

[0114] In the following text, it is assumed that... Figure 1 The semiconductor packaging alignment device 100 performs Figure 5 The process. Furthermore, in Figure 5 As can be understood from the description, the operations described as being performed by the device are controlled by the processor 110 of the semiconductor package alignment device 100.

[0115] Figure 5 At least one operation can be performed by Figure 1 The semiconductor packaging alignment device 100 performs the alignment. Figure 5 At least one operation can be performed by Figure 1 The processor 110 controls it. Figure 5 Operations can be executed sequentially, but not necessarily in that order. For example, the order of operations can be changed, and at least two operations can be executed in parallel.

[0116] refer to Figure 5 In operation S501, the semiconductor package alignment method according to the embodiment may include the operation of emitting radiation to a plurality of semiconductor chips.

[0117] For example, a semiconductor packaging alignment method may include the operation of emitting radiation to multiple semiconductor chips using a radiation source.

[0118] In operation S503, the semiconductor package alignment method according to the embodiment may include the operation of detecting radiation passing through a plurality of semiconductor chips.

[0119] In operation S505, the semiconductor package alignment method according to the embodiment may include operations of aligning and bonding a plurality of semiconductor chips by controlling the head based on detection information obtained by a radiation sensor.

[0120] For example, a semiconductor packaging alignment method may include aligning multiple semiconductor chips by controlling a head coupled to at least a portion of a radiation source to rotate the radiation source.

[0121] For example, a semiconductor package alignment method may include aligning multiple semiconductor chips by controlling a head coupled to at least a portion of a radiation source to rotate the radiation source or a lower plate (e.g., a platform) on which multiple semiconductor chips are disposed.

[0122] Figure 6 An example of a flowchart relating to a semiconductor package alignment method according to an embodiment of the present invention is shown.

[0123] In the following text, it is assumed that... Figure 1 The semiconductor packaging alignment device 100 performs Figure 6 The process. Furthermore, in Figure 6 As can be understood from the description, the operations described as being performed by the device are controlled by the processor 110 of the semiconductor package alignment device 100.

[0124] Figure 6 At least one operation can be performed by Figure 1 The semiconductor packaging alignment device 100 performs the alignment. Figure 6 At least one operation can be performed by Figure 1 The processor 110 controls it. Figure 6 Operations can be executed sequentially, but not necessarily in that order. For example, the order of operations can be changed, and at least two operations can be executed in parallel.

[0125] refer to Figure 6 In operation S601, the semiconductor package alignment method according to the embodiment may include the following operation: based on the identification of a first semiconductor chip among a plurality of semiconductor chips that is coupled to at least a portion of the head, identifying a second semiconductor chip among the plurality of semiconductor chips to be coupled to the first semiconductor chip.

[0126] For example, a first semiconductor chip coupled to at least a portion of the head among a plurality of semiconductor chips may include a first reference mark. For example, the first reference mark may include at least one of a first alignment mark, a first TSV, and any combination thereof.

[0127] For example, each of a plurality of semiconductor chips may include at least one of alignment marks, TSVs, fan-in or fan-out interconnects, interposer interconnects, and any combination thereof.

[0128] For example, a second semiconductor chip among a plurality of semiconductor chips may include a second reference mark. For example, the second reference mark may include at least one of a second alignment mark, a second TSV, and any combination thereof.

[0129] In operation S603, the semiconductor package alignment method according to the embodiment may include at least one of a control head, an alignment part, and any combination thereof, to match a first reference mark included in a first semiconductor chip and a second reference mark included in a second semiconductor chip.

[0130] For example, a semiconductor package alignment method may include the operation of moving or rotating a head. For example, the head may move in a plane parallel to the surface on which the second semiconductor chip is disposed. For example, the head may rotate about a central axis of the head. For example, the head may be controlled by at least one of a semiconductor package alignment apparatus, a processor included in the semiconductor package alignment apparatus, and any combination thereof, and thus rotate about the center of the head or move in a plane parallel to the surface on which the second semiconductor chip is disposed.

[0131] Furthermore, the head may include a radiation source. For another example, the head may be coupled to at least a portion of a radiation source. For instance, the head may include a radiation source to help generate data for determining whether a first semiconductor chip and a second semiconductor chip are matched. For example, a semiconductor package alignment method may include using a radiation source included in or coupled to at least a portion of the head to determine whether at least one of a first alignment mark, a first TSV, and any combination thereof included in the first semiconductor chip matches at least one of a second alignment mark, a second TSV, and any combination thereof included in the second semiconductor chip.

[0132] For example, if the first reference mark and the second reference mark do not match each other, the semiconductor package alignment method may include operations to control the head to match the first reference mark and the second reference mark.

[0133] For example, if at least one of the first alignment mark, the first TSV, and any combination thereof does not match the second alignment mark, the second TSV, and any combination thereof, the semiconductor package alignment method may include controlling a head to match the first alignment mark, the first TSV, and any combination thereof with the second alignment mark, the second TSV, and any combination thereof.

[0134] For example, a semiconductor package alignment method may include the following operation: aligning a first alignment mark included in the first semiconductor chip and a second alignment mark included in the second semiconductor chip by moving or rotating a head coupled (or attached) to a first semiconductor chip.

[0135] For example, a semiconductor package alignment method may include the following operation: aligning a first TSV included in the first semiconductor chip and a second TSV included in the second semiconductor chip by moving or rotating a head coupled (or attached) to a first semiconductor chip.

[0136] For example, a semiconductor package alignment method may include the operation of identifying at least one of a first alignment mark, a first TSV, and any combination thereof included in a first semiconductor chip. For example, a semiconductor package alignment method may include the operation of identifying at least one of a second alignment mark, a second TSV, and any combination thereof included in a second semiconductor chip.

[0137] For example, a semiconductor package alignment method may include adjusting the head to match a first alignment mark and a second alignment mark.

[0138] For example, a semiconductor package alignment method may include adjusting the head to match a first TSV and a second TSV.

[0139] For example, adjusting the head can include rotating or moving the head around its central axis.

[0140] As described above, the semiconductor package alignment method according to the embodiments may include the following operation: using a radiation source included in or coupled to the head to identify whether at least one of a first alignment mark, a first TSV, and any combination thereof included in a first semiconductor chip matches at least one of a second alignment mark, a second TSV, and any combination thereof included in a second semiconductor chip.

[0141] If at least one of a first alignment mark, a first TSV, and any combination thereof does not match with at least one of a second alignment mark, a second TSV, and any combination thereof, the semiconductor package alignment method may include the operation of controlling the header to which the first semiconductor chip is coupled to align at least one of the first alignment mark, the first TSV, and any combination thereof with at least one of the second alignment mark, the second TSV, and any combination thereof. For example, the semiconductor package alignment method may include the operation of coupling the first semiconductor chip and the second semiconductor chip based on the matching of at least one of the first alignment mark, the first TSV, and any combination thereof with at least one of the second alignment mark, the second TSV, and any combination thereof. The semiconductor package alignment method may include the operation of aligning and coupling (or attaching) the first semiconductor chip and the second semiconductor chip by performing the above operations.

[0142] Semiconductor package alignment devices can be implemented as hardware components, software components, and / or combinations of hardware and software components. For example, the devices and components described in the embodiments can be implemented using one or more general-purpose or special-purpose computers, such as processors, controllers, arithmetic logic units (ALUs), digital signal processors, microcomputers, field-programmable gate arrays (FPGAs), programmable logic units (PLUs), microprocessors, or any other device capable of executing and responding to instructions. The processing device can execute an operating system (OS) and one or more software applications running on the operating system. Furthermore, the processing device can access, store, manipulate, process, and generate data in response to the execution of software. For ease of understanding, the use of a single processing device is described. However, those skilled in the art will recognize that a processing device can include multiple processing elements and / or various types of processing elements. For example, a processing device can include multiple processors or one processor and one controller. Furthermore, the processing device can be other processing configurations, such as parallel processors.

[0143] Software may include computer programs, code, instructions, or combinations thereof, and may configure a processing device to operate as needed, or to command the processing device independently or collectively. Software and / or data may be interpreted by the processing device or embodied in any type of machine, component, physical device, computer storage medium, or device that provides instructions or data to the processing device. Software may be distributed across networked computer systems and stored or executed in a distributed manner. Software and data may be stored on one or more computer-readable recording media.

[0144] The method according to the embodiments can be implemented in the form of program instructions, which can be executed by various computer devices and recorded on a computer-readable medium. In this case, the medium can continuously store a computer-executable program, or it can temporarily store a computer-executable program for execution or download. Furthermore, the medium can be various recording devices or various storage devices in the form of a single piece of hardware or coupled pieces of hardware, and is not limited to media directly connected to any computer system, but can be distributed across a network. Examples of media can include magnetic media (such as hard disks, floppy disks, and magnetic tapes), optical recording media (such as CD-ROMs and DVDs), magneto-optical media (such as optical discs and ROMs), RAM, flash memory, etc., and can be configured to store program instructions. Other examples of media can include recording media or storage media managed by app stores that distribute applications, sites that provide or distribute various other software, servers, etc.

[0145] According to this disclosure, a radiation source can be used to detect interconnects or TSVs on the bonding surfaces that may not be visually identifiable in a process of bonding multiple semiconductor chips. Fine alignment on the semiconductor chips can be performed continuously, which can improve bonding accuracy and thus improve semiconductor production yield.

[0146] Furthermore, according to this disclosure, compared with bonding based on optical alignment methods, the alignment accuracy can be relatively improved, the packaging yield can be increased, and therefore the production cost can be reduced, and the price competitiveness can be increased.

[0147] Furthermore, according to this disclosure, low-dose radiation can be radiated, or radiation can be transmitted only to the portion of the alignment mark and / or TSV located, rather than the entire area of ​​the semiconductor chip, thereby preventing damage to the semiconductor chip.

[0148] Furthermore, according to this disclosure, the alignment mark area of ​​the lower chip of the alignment optical system mounted outside the chip head according to the related technology can be reduced, and thus the chip integration can be increased.

[0149] In addition, it can provide various effects that are directly or indirectly known through this article.

[0150] As described above, embodiments have been described with reference to limited examples and accompanying drawings; however, those skilled in the art can derive various modifications and changes from the above description. For example, suitable results can be achieved even if the described techniques are performed in a different order than the described methods, and / or the described components (such as systems, structures, devices, and circuits) are coupled or combined in a different form than the described methods, or replaced or substituted by other components or equivalents. Therefore, other implementations, other embodiments, and those equivalent to the appended claims also fall within the scope of the appended claims.

Claims

1. A semiconductor packaging alignment apparatus, comprising: A radiation source configured to emit radiation toward multiple semiconductor chips; A radiation sensor configured to detect radiation passing through the plurality of semiconductor chips; The head is coupled to one of the radiation source and the radiation sensor; An alignment unit is configured to align and join the plurality of semiconductor chips based on detection information acquired by the radiation sensor; as well as A processor configured to control at least one of the radiation source, the head, the radiation sensor, the alignment unit, and any combination thereof. The processor is configured as follows: Based on the identification of a first semiconductor chip that is coupled to at least a portion of the head among the plurality of semiconductor chips, a second semiconductor chip among the plurality of semiconductor chips to be coupled to the first semiconductor chip is identified; as well as Control the head, the alignment portion, and at least one of any combination thereof to match a first reference mark included in the first semiconductor chip and a second reference mark included in the second semiconductor chip.

2. The semiconductor packaging alignment apparatus according to claim 1, further comprising: The lower plate is located below the lowest semiconductor chip among the plurality of semiconductor chips, and is in contact with at least a portion of the lower semiconductor chip. The processor is configured to align the plurality of semiconductor chips based on control of the lower plate using the detection information.

3. The semiconductor packaging alignment apparatus according to claim 1, wherein, Each of the plurality of semiconductor chips includes at least one of alignment marks, through-silicon vias (TSVs), fan-in or fan-out interconnects, interposer interconnects, and any combination thereof.

4. The semiconductor packaging alignment apparatus according to claim 3, wherein, The detection information includes position information associated with at least one of the alignment mark, the TSV, and any combination thereof, and The processor is configured to control the alignment unit to align the plurality of semiconductor chips based on the position information.

5. The semiconductor packaging alignment apparatus according to claim 4, wherein, The processor is configured to match the phase of the alignment mark or the phase of the TSV based on the control of the alignment unit using the position information, in order to align the plurality of semiconductor chips.

6. The semiconductor packaging alignment apparatus according to claim 3, wherein, At least one of the alignment mark, the TSV, and any combination thereof is formed of a material whose transmittance of the radiation is less than a specified value.

7. The semiconductor packaging alignment apparatus according to claim 3, further comprising: A camera is configured to acquire images of the plurality of semiconductor chips. The processor is configured to control the radiation source to radiate the radiation to a designated area set based on the position of at least one of the alignment mark, the TSV, and any combination thereof obtained from the camera.

8. The semiconductor packaging alignment apparatus according to claim 1, wherein, The plurality of semiconductor chips are arranged perpendicularly to the reference surface. The radiation source is located above the uppermost semiconductor chip among the plurality of semiconductor chips, and... The radiation sensor is located below the lowest semiconductor chip among the plurality of semiconductor chips.

9. The semiconductor packaging alignment apparatus according to claim 1, further comprising: monitor; as well as An operating unit is used to operate the alignment unit. The processor is configured as follows: The detection information is output and provided to the user through the display; and The alignment unit is controlled based on the input received from the operation unit.

10. The semiconductor packaging alignment apparatus according to claim 1, wherein, The radiation source includes an X-ray source.

11. The semiconductor packaging alignment apparatus according to claim 1, wherein, The radiation sensor has a resolution in nm, where nm includes μm.

12. A semiconductor package alignment method, comprising: The processor emits radiation towards multiple semiconductor chips; Detecting radiation passing through the plurality of semiconductor chips; The head is controlled based on detection information obtained from radiation sensors to align and engage the multiple semiconductor chips. Based on the identification of a first semiconductor chip that is coupled to at least a portion of the head, a second semiconductor chip to be coupled to the first semiconductor chip is identified among the plurality of semiconductor chips in order to align the plurality of semiconductor chips. as well as Control the head, the alignment portion, and at least one of any combination thereof to match a first reference mark included in the first semiconductor chip and a second reference mark included in the second semiconductor chip.

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