Peak filter circuit for keeping pulse width of input signal

Abstract

The invention discloses a peak filter circuit capable of keeping the pulse width of an input signal, which comprises an input circuit, a first positive feedback filter circuit, a second positive feedback filter circuit and a filter output selection circuit, the output end of the input circuit is connected with the input end of the first positive feedback filter circuit and the input end of the second positive feedback filter circuit, and the output end of the first positive feedback filter circuit and the output end of the second positive feedback filter circuit are connected with the input end of the filter output selection circuit. The output end of the filter output selection circuit generates an output signal VOUT. According to the invention, the pulse width of the input signal can be maintained while the expected peak voltage is filtered, and the reliability of communication between chips is improved.

Description

Technical Field

[0001] This invention relates to a filtering circuit, and more particularly to a spike filtering circuit that maintains the pulse width of the input signal, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] With the development of technology and the ever-increasing demand for big data computing power and transportation capacity, chip data transmission rates are constantly improving. The operating environment for chips is also becoming increasingly complex, with more interference factors, making them prone to unwanted voltage spikes and glitches, affecting the normal operation of communication lines. Especially for synchronous serial communication, where clock and data signals have a one-to-one correspondence, extra spikes and glitches in the clock / data signals during normal communication can directly cause errors in the receiver's decoding logic, leading to errors in the entire signal transmission. Therefore, for inter-chip communication, filtering circuits are typically added to the chip's input stage to eliminate spikes in the communication signal.

[0003] Digital methods typically employ digital filters to handle signal glitches. The receiver waits for multiple clock cycles before determining the output digital signal, thus filtering out glitches. Digital methods can filter out glitches with relatively small footprints. However, they cannot handle voltage spikes with a time width shorter than a clock cycle, and they also cannot handle glitches in time-based signals.

[0004] The basic principle of voltage spike filtering using analog methods is as follows: Figure 5 As shown, the circuit includes NMOS transistors MN1-MN4, PMOS transistors MP1-MP4, resistor R1, and capacitor C1. Ignoring non-ideal factors such as the on-resistance and parasitic capacitance of transistors MN1-MN4 and MP1-MP4, as well as the delay of the inverter they form, and assuming the inverter's switching threshold voltage is VDD / 2, this circuit can filter out high-level and low-level glitches with a time width less than 0.693R1C1. When the input signal changes from low to high, the voltage at node 103 also increases. At this time, the power supply charges the capacitor through the resistor, and the voltage at node 104 increases exponentially from 0, which can be expressed as:

[0005] When the voltage at node 104 rises to the switching threshold of the inverter, the voltages at nodes 105 and 106 flip.

[0006]

[0007] Therefore, when the high-level duration of the input signal is less than this duration, the input signal does not flip, and such short pulses are considered unexpected spikes and are filtered out. Similarly, when the input signal changes from a high level to a low level, a similar filtering effect occurs. The final signal transmission effect is as follows: Figure 6 As shown.

[0008] As can be seen, under ideal conditions, the delay between the rising edge of the input signal and the rising edge of the output signal, as well as the delay between the falling edge of the input signal and the falling edge of the output signal, are both... Therefore, the input signal and the input signal time width remain consistent.

[0009] However, if we consider the non-ideal factors that cannot be ignored in reality, firstly Figure 5 The on-resistance of transistors MP2 and MN2 in the input signal is difficult to guarantee to remain constant under varying PVT conditions. Therefore, for the rising and falling edges of the input signal, the resistance in formula (1) is... Furthermore, load capacitance typically has a voltage coefficient, meaning that the capacitance value changes for different voltage drops. The magnitude of this voltage coefficient depends on the capacitor type and manufacturing process. Additionally, for the parasitic capacitance of the non-negligible MOS transistor, its voltage coefficient is usually large. During the rising edge filtering phase of the input signal, the voltage drop across the load capacitor is low, while during the falling edge filtering phase, the voltage drop across the load capacitor is high. Therefore, in formula (1)... Furthermore, this can lead to a difference of up to 20% between the rising and falling edge delays. Finally, the threshold voltage of the inverter's switching voltage is not fixed at VDD / 2, but varies with the PVT condition, which also results in inconsistencies in the rising and falling edge delays of the final output signal. This inconsistency in delay causes the filter to have different filtering capabilities for positive and negative voltage spikes, and it also modulates the input signal, causing changes in the duration of high and low levels between the input and output signals. For some high-speed inter-chip communications, the timing requirements for input digital signals are extremely stringent; the presence of this filter alters the original timing characteristics of the input signal, reducing the chip's reliability.

[0010] In addition, Figure 6 In the schematic diagram of the traditional analog filtering method shown, after the voltage at node 106 flips, the voltage at node 104 remains near VDD / 2 for a considerable period before slowly building up to VDD or GND. When the input voltage is near the switching threshold voltage of the inverter, both the PMOS and NMOS of the inverter are in the on state, resulting in a large quiescent current and thus increasing circuit power consumption. Summary of the Invention

[0011] The technical problem to be solved by the present invention is to provide a spike filter circuit that maintains the pulse width of the input signal while filtering out unwanted spike voltages.

[0012] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A spike filter circuit for maintaining the pulse width of an input signal includes an input circuit, a first positive feedback filter circuit, a second positive feedback filter circuit, and a filter output selection circuit. The input terminal of the input circuit is connected to the input signal VIN, and the output terminal of the input circuit is connected to the input terminals of the first and second positive feedback filter circuits. The output terminals of the first and second positive feedback filter circuits are connected to the input terminal of the filter output selection circuit, and the output terminal of the filter output selection circuit generates an output signal VOUT.

[0013] Furthermore, the input circuit includes inverters INV1 and INV2. The input terminal of inverter INV1 serves as the input terminal of the input circuit, and the output terminal of inverter INV1 is connected to the input terminal of inverter INV2. The output terminal of inverter INV2 serves as the output terminal of the input circuit.

[0014] Furthermore, the first positive feedback filter circuit includes inverters INV3 to INV6, a first filter unit circuit, and a first output positive feedback circuit. The input terminal of inverter INV3 serves as the input terminal of the first positive feedback filter circuit. The output terminal of inverter INV3 is connected to the input terminal of inverter INV4. The output terminal of inverter INV4 is connected to the input terminal of the first filter unit circuit. The output terminal of the first filter unit circuit is connected to the input terminal of inverter INV5 and the output terminal of the first output positive feedback circuit. The output terminal of inverter INV5 is connected to the input terminal of inverter INV6. The output terminal of inverter INV6 is connected to the input terminal of the first output positive feedback circuit and serves as the output terminal of the first positive feedback filter circuit.

[0015] Furthermore, the first filter unit circuit includes a resistor R1 and a capacitor C1. One end of the resistor R1 serves as the input terminal of the first filter unit circuit, and the other end of the resistor R1 is connected to one end of the capacitor C1 and serves as the output terminal of the first filter unit circuit. The other end of the capacitor C1 is grounded.

[0016] Furthermore, the first output positive feedback circuit includes a NAND gate NAND1, a NOR gate NOR1, a PMOS transistor MP1, and an NMOS transistor MN1. The first input terminal of the NAND gate NAND1 is connected to the second input terminal of the NOR gate NOR1 and serves as the input terminal of the first output positive feedback circuit. The second input terminal of the NAND gate NAND1 is connected to the first input terminal of the NOR gate NOR1, the output terminal of the inverter INV4, and the input terminal of the first filter unit. The output terminal of the NAND gate NAND1 is connected to the gate of the PMOS transistor MP1, and the output terminal of the NOR gate NOR1 is connected to the gate of the NMOS transistor MN1. The source of the PMOS transistor MP1 is connected to the power rail. The drain of the PMOS transistor MP1 and the drain of the NMOS transistor MN1 serve as the output terminal of the first output positive feedback circuit. The source of the NMOS transistor MN1 is grounded.

[0017] Furthermore, the second positive feedback filter circuit includes inverters INV7 to INV10, a second filter unit circuit, and a second output positive feedback circuit. The input terminal of inverter INV7 serves as the input terminal of the second positive feedback filter circuit. The output terminal of inverter INV7 is connected to the input terminal of the second filter unit circuit. The output terminal of the second filter unit circuit is connected to the input terminal of inverter INV8 and the output terminal of the second output positive feedback circuit. The output terminal of inverter INV8 is connected to the input terminal of inverter INV9. The output terminal of inverter INV9 is connected to the input terminal of the second output positive feedback circuit and the input terminal of inverter INV10. The output terminal of inverter INV10 also serves as the output terminal of the second positive feedback filter circuit.

[0018] Furthermore, the second filter unit circuit includes a resistor R2 and a capacitor C2. One end of the resistor R2 serves as the input terminal of the second filter unit circuit, and the other end of the resistor R2 is connected to one end of the capacitor C2 and serves as the output terminal of the second filter unit circuit. The other end of the capacitor C2 is grounded.

[0019] Furthermore, the second output positive feedback circuit includes a NAND gate NAND2, a NOR gate NOR2, a PMOS transistor MP2, and an NMOS transistor MN2. The first input terminal of the NAND gate NAND2 is connected to the second input terminal of the NOR gate NOR2 and serves as the input terminal of the second output positive feedback circuit. The second input terminal of the NAND gate NAND2 is connected to the first input terminal of the NOR gate NOR2, the output terminal of the inverter INV7, and the input terminal of the second filter unit. The output terminal of the NAND gate NAND2 is connected to the gate of the PMOS transistor MP2, and the output terminal of the NOR gate NOR2 is connected to the gate of the NMOS transistor MN2. The source of the PMOS transistor MP2 is connected to the power rail. The drain of the PMOS transistor MP2 and the drain of the NMOS transistor MN2 serve as the output terminal of the second output positive feedback circuit. The source of the NMOS transistor MN2 is grounded.

[0020] Furthermore, the filter output selection circuit includes a NOR gate (NOR3), a NAND gate (NAND3), an inverter (INV11), a NAND gate (NAND4), a NAND gate (NAND5), and an inverter (INV12). The first input terminal of the NOR gate (NOR3) is connected to the first input terminal of the NAND gate (NAND3) and serves as the first input terminal of the filter output selection circuit. The second input terminal of the NOR gate (NOR3) is connected to the second input terminal of the NAND gate (NAND3) and serves as the second input terminal of the filter output selection circuit. The output terminal of the NOR gate (NOR3) is connected to the input terminal of the inverter (INV11). The output terminal of the inverter (INV11) is connected to the first input terminal of the NAND gate (NAND4). The output terminal of the NAND gate (NAND3) is connected to the second input terminal of the NAND gate (NAND5). The output terminal of the NAND gate (NAND4) is connected to the input terminal of the inverter (INV12) and the first input terminal of the NAND gate (NAND5). The output terminal of the NAND gate (NAND5) is connected to the second input terminal of the NAND gate (NAND4). The output terminal of the inverter (INV12) serves as the output terminal of the filter output selection circuit.

[0021] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a spike filter circuit that maintains the pulse width of the input signal, which can filter out unwanted spike voltages while maintaining the pulse width of the input signal, thereby improving the reliability of inter-chip communication. This circuit can also be applied to chip communication application scenarios. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a spike filter circuit that maintains the pulse width of the input signal according to the present invention.

[0023] Figure 2 This is a circuit diagram of a spike filter circuit that maintains the pulse width of the input signal according to the present invention.

[0024] Figure 3 This is a schematic diagram of the operation of the first positive feedback filter circuit of the present invention.

[0025] Figure 4 This is a schematic diagram of a spike filter circuit that maintains the pulse width of the input signal according to the present invention.

[0026] Figure 5 This is a circuit diagram of an existing analog spike voltage filter circuit.

[0027] Figure 6 This is a schematic diagram of the operation of an existing analog spike voltage filter circuit. Detailed Implementation

[0028] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0029] like Figure 1 and Figure 2 As shown, a spike filter circuit for maintaining the pulse width of an input signal according to the present invention includes an input circuit, a first positive feedback filter circuit, a second positive feedback filter circuit, and a filter output selection circuit. The input terminal of the input circuit is connected to the input signal VIN, and the output terminal of the input circuit is connected to the input terminals of the first positive feedback filter circuit and the second positive feedback filter circuit. The output terminals of the first positive feedback filter circuit and the second positive feedback filter circuit are connected to the input terminal of the filter output selection circuit, and the output terminal of the filter output selection circuit generates an output signal VOUT.

[0030] The input circuit includes inverters INV1 and INV2. The input terminal of inverter INV1 serves as the input terminal of the input circuit, and the output terminal of inverter INV1 is connected to the input terminal of inverter INV2. The output terminal of inverter INV2 serves as the output terminal of the input circuit.

[0031] The first positive feedback filter circuit includes inverters INV3 to INV6, a first filter unit circuit, and a first output positive feedback circuit. The input terminal of inverter INV3 serves as the input terminal of the first positive feedback filter circuit. The output terminal of inverter INV3 is connected to the input terminal of inverter INV4. The output terminal of inverter INV4 is connected to the input terminal of the first filter unit circuit. The output terminal of the first filter unit circuit is connected to the input terminal of inverter INV5 and the output terminal of the first output positive feedback circuit. The output terminal of inverter INV5 is connected to the input terminal of inverter INV6. The output terminal of inverter INV6 is connected to the input terminal of the first output positive feedback circuit and serves as the output terminal of the first positive feedback filter circuit.

[0032] The first filter unit circuit includes a resistor R1 and a capacitor C1. One end of the resistor R1 serves as the input terminal of the first filter unit circuit, and the other end of the resistor R1 is connected to one end of the capacitor C1 and serves as the output terminal of the first filter unit circuit. The other end of the capacitor C1 is grounded.

[0033] The first output positive feedback circuit includes a NAND gate NAND1, a NOR gate NOR1, a PMOS transistor MP1, and an NMOS transistor MN1. The first input terminal of the NAND gate NAND1 is connected to the second input terminal of the NOR gate NOR1 and serves as the input terminal of the first output positive feedback circuit. The second input terminal of the NAND gate NAND1 is connected to the first input terminal of the NOR gate NOR1, the output terminal of the inverter INV4, and the input terminal of the first filter unit. The output terminal of the NAND gate NAND1 is connected to the gate of the PMOS transistor MP1, and the output terminal of the NOR gate NOR1 is connected to the gate of the NMOS transistor MN1. The source of the PMOS transistor MP1 is connected to the power rail. The drain of the PMOS transistor MP1 and the drain of the NMOS transistor MN1 serve as the output terminal of the first output positive feedback circuit. The source of the NMOS transistor MN1 is grounded.

[0034] After the voltage level at node E flips, the voltage level at intermediate node D is quickly pulled to the power rail to avoid unnecessary current consumption caused by the inverter operating under high current for an extended period. A schematic diagram of the first output positive feedback circuit in operation is shown below. Figure 3 As shown.

[0035] For simplicity, we ignore the inherent delay of the logic gates. When node B changes from low to high, node C also changes from low to high, while node E remains low initially. Therefore, node F remains high, and PMOS transistor MP1 remains off. Meanwhile, node G changes from high to low, and NMOS transistor MN1 changes from on to off. Thus, the voltage at node D starts from 0. If the high input duration is long enough, the voltage at node D rises above the inverter's switching threshold voltage. At this point, node E flips to high, and simultaneously, through the positive feedback loop, node F goes high, turning on PMOS transistor MP1 and quickly pulling the voltage at node D up, thus preventing the subsequent inverter from operating at high current for an extended period. Similarly, when node B changes from high to low, the positive feedback logic turns off both PMOS transistor MP1 and NMOS transistor MN1 until node E also changes from high to low. Then, NMOS transistor MN1 turns on, quickly pulling the voltage at node D down.

[0036] The second positive feedback filter circuit includes inverters INV7 to INV10, a second filter unit circuit, and a second output positive feedback circuit. The input terminal of inverter INV7 serves as the input terminal of the second positive feedback filter circuit. The output terminal of inverter INV7 is connected to the input terminal of the second filter unit circuit. The output terminal of the second filter unit circuit is connected to the input terminal of inverter INV8 and the output terminal of the second output positive feedback circuit. The output terminal of inverter INV8 is connected to the input terminal of inverter INV9. The output terminal of inverter INV9 is connected to the input terminal of the second output positive feedback circuit and the input terminal of inverter INV10. The output terminal of inverter INV10 also serves as the output terminal of the second positive feedback filter circuit.

[0037] The second filter unit circuit includes a resistor R2 and a capacitor C2. One end of the resistor R2 serves as the input terminal of the second filter unit circuit, and the other end of the resistor R2 is connected to one end of the capacitor C2 and serves as the output terminal of the second filter unit circuit. The other end of the capacitor C2 is grounded.

[0038] The second output positive feedback circuit includes a NAND gate NAND2, a NOR gate NOR2, a PMOS transistor MP2, and an NMOS transistor MN2. The first input terminal of the NAND gate NAND2 is connected to the second input terminal of the NOR gate NOR2 and serves as the input terminal of the second output positive feedback circuit. The second input terminal of the NAND gate NAND2 is connected to the first input terminal of the NOR gate NOR2, the output terminal of the inverter INV7, and the input terminal of the second filter unit. The output terminal of the NAND gate NAND2 is connected to the gate of the PMOS transistor MP2, and the output terminal of the NOR gate NOR2 is connected to the gate of the NMOS transistor MN2. The source of the PMOS transistor MP2 is connected to the power rail. The drain of the PMOS transistor MP2 and the drain of the NMOS transistor MN2 serve as the output terminal of the second output positive feedback circuit. The source of the NMOS transistor MN2 is grounded.

[0039] like Figure 4As shown, in the first positive feedback filter circuit, the voltage at node C of the first filter unit circuit is in phase with the input signal VIN, while in the second positive feedback filter circuit, the voltage at node H of the second filter unit circuit is out of phase with the input signal VIN. Assume that the delay of the filter unit for the falling edge of the signal is greater than its delay for the rising edge, and the duration of voltage glitches in the signal falls exactly between these two. When the input signal VIN changes from low to high, the voltage at node C also changes from low to high, while the voltage at node H changes from high to low. Therefore, after passing through the filter unit and two inverters, the rising edge of the voltage at node E is earlier than the falling edge of the voltage at node M. Since the voltage at node J is a further inversion of the voltage at node M, the rising edge of the voltage at node E is also earlier than the rising edge of the voltage at node J. The voltages at nodes E and J serve as inputs to the filter output selection module. This module only flips the final output voltage VOUT from low to high when both voltages change from low to high; therefore, the rising edge of VOUT is aligned with the rising edge of node J. Conversely, when the input signal VIN changes from high to low, the voltage at node C changes from high to low, and the voltage at node H changes from low to high. Considering the different delays of the rising and falling edges by the filtering unit, the falling edge of the voltage at node E is later than that at node J. In this case, the filter output selection module only releases the final output voltage VOUT when both nodes change from high to low, thus aligning the falling edge of VOUT with the falling edge of node E. Therefore, from the final result, the output edge of VOUT is delayed by the same amount of time compared to VIN, and is the longer of the rising / falling edge delays by the filtering unit. The pulse widths of VOUT and VIN remain unchanged, and the filtering effect on unexpected positive and negative voltage spikes is consistent. However, compared to the signals at nodes E and J that do not pass through the filter output selection module, similar to existing technologies, there is a problem of incomplete filtering of voltage spike interference. Furthermore, the high-level duration of the signals at nodes E and J differs significantly from that of the input signal, which may lead to communication failure under strict timing requirements. Therefore, this invention effectively provides reliable high-speed inter-chip communication.

[0040] The filter output selection circuit includes NOR3, NAND3, INV11, NAND4, NAND5, and INV12. The first input of NOR3 is connected to the first input of NAND3 and serves as the first input of the filter output selection circuit. The second input of NOR3 is connected to the second input of NAND3 and serves as the second input of the filter output selection circuit. The output of NOR3 is connected to the input of INV11. The output of INV11 is connected to the first input of NAND4. The output of NAND3 is connected to the second input of NAND5. The output of NAND4 is connected to the input of INV12 and the first input of NAND5. The output of NAND5 is connected to the second input of NAND4. The output of INV12 serves as the output of the filter output selection circuit. Among them, NAND4 and NAND5 form the RS latch.

[0041] When the voltages of nodes E and J are both low, node N is low, node O is high, the RS latch is in the Set state, therefore node P is high, and the output signal VOUT is low. When either node E or J changes from low to high, node N changes from low to high, node O remains high, the RS latch is in the latched state, therefore the voltages of nodes P and the output signal VOUT do not change. Subsequently, when the other node E or J also changes from low to high, node N remains high, while node O changes from high to low, the RS latch is in the Reset state, therefore node P is low, and the output signal VOUT is high.

[0042] When both nodes E and J are high, node N is high, node O is low, and the RS latch is in a reset state. Therefore, node P is low, and the output signal VOUT is high. When either node E or J changes from high to low, node N remains high, while node O changes from low to high. The RS latch is in a latched state, so the voltages of nodes P and the output signal VOUT do not change. Subsequently, when both nodes E and J change from high to high, node N remains high, while node O changes from high to low. The RS latch is in a reset state, so node P is low, and the output signal VOUT is high.

[0043] With this circuit structure, the edge of the output voltage VOUT can always be aligned with the edge of the voltage with the longer delay among nodes E and J, thus realizing the function of the filter output selection circuit mentioned above.

[0044] This invention provides a spike filter circuit that maintains the pulse width of the input signal. While filtering out unwanted spike voltages, it can maintain the pulse width of the input signal and improve the reliability of inter-chip communication. This circuit can also be applied to chip communication application scenarios.

[0045] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A spike filter circuit that maintains the pulse width of an input signal, characterized in that: It includes an input circuit, a first positive feedback filter circuit, a second positive feedback filter circuit, and a filter output selection circuit. The input terminal of the input circuit is connected to the input signal VIN, and the output terminal of the input circuit is connected to the input terminals of the first positive feedback filter circuit and the second positive feedback filter circuit. The output terminals of the first positive feedback filter circuit and the second positive feedback filter circuit are connected to the input terminal of the filter output selection circuit. The output terminal of the filter output selection circuit generates an output signal VOUT.

2. The spike filter circuit for maintaining the pulse width of the input signal according to claim 1, characterized in that: The input circuit includes inverters INV1 and INV2. The input terminal of inverter INV1 serves as the input terminal of the input circuit, and the output terminal of inverter INV1 is connected to the input terminal of inverter INV2. The output terminal of inverter INV2 serves as the output terminal of the input circuit.

3. The spike filter circuit for maintaining the pulse width of the input signal according to claim 1, characterized in that: The first positive feedback filter circuit includes inverters INV3 to INV6, a first filter unit circuit, and a first output positive feedback circuit. The input terminal of inverter INV3 serves as the input terminal of the first positive feedback filter circuit. The output terminal of inverter INV3 is connected to the input terminal of inverter INV4. The output terminal of inverter INV4 is connected to the input terminal of the first filter unit circuit. The output terminal of the first filter unit circuit is connected to the input terminal of inverter INV5 and the output terminal of the first output positive feedback circuit. The output terminal of inverter INV5 is connected to the input terminal of inverter INV6. The output terminal of inverter INV6 is connected to the input terminal of the first output positive feedback circuit and serves as the output terminal of the first positive feedback filter circuit.

4. A spike filter circuit for maintaining the pulse width of the input signal according to claim 3, characterized in that: The first filter unit circuit includes a resistor R1 and a capacitor C1. One end of the resistor R1 serves as the input terminal of the first filter unit circuit, and the other end of the resistor R1 is connected to one end of the capacitor C1 and serves as the output terminal of the first filter unit circuit. The other end of the capacitor C1 is grounded.

5. A spike filter circuit for maintaining the pulse width of the input signal according to claim 3, characterized in that: The first output positive feedback circuit includes a NAND gate NAND1, a NOR gate NOR1, a PMOS transistor MP1, and an NMOS transistor MN1. The first input terminal of the NAND gate NAND1 is connected to the second input terminal of the NOR gate NOR1 and serves as the input terminal of the first output positive feedback circuit. The second input terminal of the NAND gate NAND1 is connected to the first input terminal of the NOR gate NOR1, the output terminal of the inverter INV4, and the input terminal of the first filter unit. The output terminal of the NAND gate NAND1 is connected to the gate of the PMOS transistor MP1, and the output terminal of the NOR gate NOR1 is connected to the gate of the NMOS transistor MN1. The source of the PMOS transistor MP1 is connected to the power rail. The drain of the PMOS transistor MP1 and the drain of the NMOS transistor MN1 serve as the output terminal of the first output positive feedback circuit. The source of the NMOS transistor MN1 is grounded.

6. A spike filter circuit for maintaining the pulse width of the input signal according to claim 1, characterized in that: The second positive feedback filter circuit includes inverters INV7 to INV10, a second filter unit circuit, and a second output positive feedback circuit. The input terminal of inverter INV7 serves as the input terminal of the second positive feedback filter circuit. The output terminal of inverter INV7 is connected to the input terminal of the second filter unit circuit. The output terminal of the second filter unit circuit is connected to the input terminal of inverter INV8 and the output terminal of the second output positive feedback circuit. The output terminal of inverter INV8 is connected to the input terminal of inverter INV9. The output terminal of inverter INV9 is connected to the input terminal of the second output positive feedback circuit and the input terminal of inverter INV10. The output terminal of inverter INV10 also serves as the output terminal of the second positive feedback filter circuit.

7. A spike filter circuit for maintaining the pulse width of the input signal according to claim 6, characterized in that: The second filter unit circuit includes a resistor R2 and a capacitor C2. One end of the resistor R2 serves as the input terminal of the second filter unit circuit, and the other end of the resistor R2 is connected to one end of the capacitor C2 and serves as the output terminal of the second filter unit circuit. The other end of the capacitor C2 is grounded.

8. A spike filter circuit for maintaining the pulse width of the input signal according to claim 6, characterized in that: The second output positive feedback circuit includes a NAND gate NAND2, a NOR gate NOR2, a PMOS transistor MP2, and an NMOS transistor MN2. The first input terminal of the NAND gate NAND2 is connected to the second input terminal of the NOR gate NOR2 and serves as the input terminal of the second output positive feedback circuit. The second input terminal of the NAND gate NAND2 is connected to the first input terminal of the NOR gate NOR2, the output terminal of the inverter INV7, and the input terminal of the second filter unit. The output terminal of the NAND gate NAND2 is connected to the gate of the PMOS transistor MP2, and the output terminal of the NOR gate NOR2 is connected to the gate of the NMOS transistor MN2. The source of the PMOS transistor MP2 is connected to the power rail. The drain of the PMOS transistor MP2 and the drain of the NMOS transistor MN2 serve as the output terminal of the second output positive feedback circuit. The source of the NMOS transistor MN2 is grounded.

9. A spike filter circuit for maintaining the pulse width of the input signal according to claim 1, characterized in that: The filter output selection circuit includes NOR3, NAND3, INV11, NAND4, NAND5, and INV12. The first input of NOR3 is connected to the first input of NAND3 and serves as the first input of the filter output selection circuit. The second input of NOR3 is connected to the second input of NAND3 and serves as the second input of the filter output selection circuit. The output of NOR3 is connected to the input of INV11. The output of INV11 is connected to the first input of NAND4. The output of NAND3 is connected to the second input of NAND5. The output of NAND4 is connected to the input of INV12 and the first input of NAND5. The output of NAND5 is connected to the second input of NAND4. The output of INV12 serves as the output of the filter output selection circuit.

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