Dynamic comparator suitable for low-voltage high-speed analog-to-digital converter

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a dynamic comparator suitable for a low-voltage high-speed analog-to-digital converter, the dynamic comparator adopts a three-stage latch circuit structure to realize rapid comparison of weak input signals so as to generate corresponding digital signals, and the method specifically comprises the following steps of: in a pre-amplification stage, pre-amplification is carried out; the positive feedback effect of the cross-coupled transistor pair is utilized to efficiently convert a tiny input voltage difference (lt; 10mV) into a recognizable voltage difference, and then through two-stage regeneration of the main latch module and the auxiliary latch module, a logic level is quickly output to complete quantization judgment. The auxiliary latch stage is additionally arranged on the basis of a traditional cross coupling latch circuit, the working speed of the comparator is effectively increased under the condition that only small area overhead is introduced, and the probability that the dynamic comparator has a metastable state is greatly reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a dynamic comparator suitable for a low-voltage high-speed analog-to-digital converter. BACKGROUND

[0002] With the development of integrated circuit technology, low power consumption, small area and low operating voltage have become the core demands of electronic systems, especially in high-speed applications such as memory interfaces, high-speed data communication and optical communication. When the MOS process enters the 40nm and below nodes, the core supply voltage drops to 0.9V or even lower, and the device noise rises against the trend, bringing severe challenges to the design of key modules. As the core module of an analog-to-digital converter (ADC), especially a successive approximation register (SAR) ADC, the speed and noise performance of a dynamic comparator directly determines the overall indicators of the ADC, so the design pressure under low-voltage advanced process is huge.

[0003] Comparators can be divided into static comparators and dynamic comparators according to the working mode: static comparators are based on open-loop amplifiers, require constant current, have high power consumption, are limited by bandwidth and are not suitable for high-speed design, and the intrinsic gain of MOS devices decreases at low voltage, which easily causes errors, making it difficult to meet the demand for high speed and low power consumption; dynamic comparators switch the reset and regeneration stages through a clock signal, have lower power consumption and faster speed, and are more suitable for high-speed low-power SAR ADCs. The working mechanism is to reset the output node to VDD in the reset stage, and compare the discharge speed of the input pair in the regeneration stage. After multiple latches, high and low levels are output to determine the input polarity.

[0004] There are many structures of existing dynamic comparators, but the core is based on the reset-regeneration mechanism, and the typical structure still has the following defects:

[0005] Figure 1 The single-stage dynamic comparator shown in the figure takes cross-coupled inverters as the core, resets the output to VDD in the reset stage, and compares the discharge difference of the input pair in the regeneration stage. However, the gate-drain capacitance (CGD) will couple noise to the input in the regeneration stage, resulting in a large kickback noise; when the layout matching is poor, the input offset voltage will be larger.

[0006] Figure 2 The double-tail structure dynamic comparator shown in the figure increases a dynamic pre-amplification stage before the traditional latch structure, improves the comparison speed, and reduces the equivalent input offset and noise. Because the regeneration node and the drain of the input tube are indirectly connected through a shielding transistor, the kickback noise is small and more suitable for low voltage. However, below 0.9V low voltage, the threshold voltage of the NMOS input tube does not decrease proportionally with the power supply voltage, and when the input common-mode voltage is lower than the threshold, it is easy to cause slow flipping or even comparison failure.

[0007] Figure 3 The double regeneration comparator shown is based on a double-tail structure dynamic comparator, a cross-coupled inverter is introduced in the pre-amplification stage, the output swing is increased to accelerate the second stage latch regeneration, and the speed is improved to a certain extent, but the low voltage, anti-process-voltage-temperature (PVT) deviation, and suppression of kickback noise are still not ideal.

[0008] Therefore, in high-speed ADC, SerDes and other applications, there is an urgent need for a dynamic comparator design that can work at low voltage (≤0.9V) and high speed, and has strong robustness to PVT deviation and kickback noise, to adapt to the stringent requirements of advanced process nodes (such as below 28nm), and break through the bottleneck of traditional structure in speed, power consumption, noise and voltage compatibility. SUMMARY

[0009] To this end, the present application aims to solve the technical bottlenecks existing in the prior art dynamic comparator: firstly, at high clock frequency, when the input differential voltage is very small, the latch is prone to enter a long time metastable state, resulting in a significant increase in comparison delay; secondly, the first stage pre-amplifier adopts a multi-transistor stack structure, which is difficult to adapt to low power voltage (such as ≤0.6V) application scenarios.

[0010] To solve the above technical problems, the present application provides a dynamic comparator suitable for low-voltage high-speed analog-to-digital converter, the dynamic comparator comprising:

[0011] A pre-amplification module is connected to a clock control signal and a differential input signal, and under the timing control of the clock control signal, the differential input signal is compared and amplified to obtain a differential amplification signal;

[0012] A latch module is connected to the clock control signal and the inverted clock control signal, and under the cooperative control of the clock control signal and the inverted clock control signal, the differential amplification signal is latched and output to obtain a differential output signal;

[0013] The latch module includes a main latch module and an auxiliary latch module, the input end of the main latch module is connected to the output end of the pre-amplification module, the output end of the main latch module is connected to the gate of the corresponding transistor in the auxiliary latch module, the auxiliary latch module is connected to the corresponding cross-coupled transistor pair in the main latch module through the cross-coupled transistor pair, and the auxiliary latch module has a complementary enhancement relationship with the corresponding cross-coupled transistor pair in the main latch module, and the threshold voltage of the transistor in the auxiliary latch module is greater than the threshold voltage of the corresponding transistor in the main latch module, to ensure that the main latch module starts regeneration before the auxiliary latch module.

[0014] In an embodiment of the present application, the pre-amplification module includes a differential amplification unit and a reset unit; wherein,

[0015] The input end of the differential amplification unit is connected to the differential input signal, the control end is connected to the clock control signal, and the differential amplification unit performs comparison amplification operation on the differential input signal under the timing control of the clock control signal, and generates the differential amplification signal at the output end.

[0016] The reset unit is connected to the output end of the differential amplification unit, the control end is connected to the clock control signal, and the reset unit performs reset operation on the output end of the differential amplification unit under the timing control of the clock control signal, so as to restore the potential of the output end to the preset power supply voltage.

[0017] In an embodiment of the present application, the differential amplification unit comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a first PMOS tube and a second PMOS tube.

[0018] The source of the first PMOS tube is connected to the power supply voltage, the gate is connected to the drain of the second PMOS tube, and the drain is connected to the drain of the first NMOS tube; the gate of the first NMOS tube is connected to the positive electrode of the differential input signal, and the source is connected to the drain of the third NMOS tube.

[0019] The source of the second PMOS tube is connected to the power supply voltage, the gate is connected to the drain of the first PMOS tube, and the drain is connected to the drain of the second NMOS tube; the gate of the second NMOS tube is connected to the negative electrode of the differential input signal, and the source is connected to the drain of the third NMOS tube.

[0020] The gate of the third NMOS tube is connected to the clock control signal, and the source is connected to the ground.

[0021] In an embodiment of the present application, the reset unit comprises a third PMOS tube and a fourth PMOS tube.

[0022] The sources of the third PMOS tube and the fourth PMOS tube are connected to the power supply voltage, the gate of the third PMOS tube is connected to the clock control signal, and the drain is connected to the drain of the first PMOS tube.

[0023] The gate of the fourth PMOS tube is connected to the clock control signal, and the drain is connected to the drain of the second PMOS tube.

[0024] In an embodiment of the present application, the main latch module comprises a positive feedback regenerative loop and an input drive circuit.

[0025] The positive feedback regeneration loop comprises a fifth NMOS tube, a sixth NMOS tube, a sixth PMOS tube and a seventh PMOS tube; the fifth NMOS tube and the sixth PMOS tube constitute a first cross-coupled branch, the gate electrodes of which are interconnected and connected to the drain electrode of the sixth NMOS tube, and the drain electrodes of which form a first output node (OP); the sixth NMOS tube and the seventh PMOS tube constitute a second cross-coupled branch, the gate electrodes of which are interconnected and connected to the drain electrode of the fifth NMOS tube, and the drain electrodes of which form a second output node (ON);

[0026] The input driving circuit comprises a seventh NMOS tube and an eighth NMOS tube, the gate electrodes of the seventh NMOS tube and the eighth NMOS tube respectively receive the negative electrode and the positive electrode of the differential amplification signal, for converting the output signal of the preamplification module into a driving current of the main latch module; the drain electrode of the seventh NMOS tube is connected to the first output node, the drain electrode of the eighth NMOS tube is connected to the second output node, and the source electrodes of the seventh NMOS tube and the eighth NMOS tube are both grounded.

[0027] In an embodiment of the present application, the main latch module further comprises a timing control circuit, the timing control circuit comprises a fifth PMOS tube, the source electrode of which is connected to a power supply voltage, the gate electrode of which is connected to an inverted clock control signal, and the drain electrode of which is connected to the source electrodes of the sixth NMOS tube and the seventh PMOS tube.

[0028] In an embodiment of the present application, the auxiliary latch module comprises a first feedback circuit and a second feedback circuit which are symmetrically arranged at two ends of the main latch module.

[0029] The first feedback circuit comprises a ninth NMOS tube and a tenth NMOS tube, the source electrode of the ninth NMOS tube is grounded, and the drain electrode of the ninth NMOS tube is connected to the gate electrode of the tenth NMOS tube; the source electrode of the tenth NMOS tube is grounded, and the drain electrode of the tenth NMOS tube is connected to the gate electrode of the ninth NMOS tube and the first output node.

[0030] The second feedback circuit comprises an eleventh NMOS tube and a twelfth NMOS tube, the source electrode of the twelfth NMOS tube is grounded, and the gate electrode of the twelfth NMOS tube is connected to the drain electrode of the eleventh NMOS tube; the source electrode of the eleventh NMOS tube is grounded, the gate electrode of the eleventh NMOS tube is connected to the drain electrode of the twelfth NMOS tube, and the drain electrode of the eleventh NMOS tube is connected to the second output node.

[0031] In an embodiment of the present application, the auxiliary latch module further comprises a sensing driving circuit, the sensing driving circuit comprising an eighth PMOS transistor and a ninth PMOS transistor; wherein a gate of the eighth PMOS transistor is connected to the first output node, a source of the eighth PMOS transistor is connected to the power supply voltage, and a drain of the eighth PMOS transistor is connected to a drain of the ninth NMOS transistor; a source of the ninth PMOS transistor is connected to the power supply voltage, a gate of the ninth PMOS transistor is connected to the second output node, and a drain of the ninth PMOS transistor is connected to a drain of the twelfth NMOS transistor.

[0032] In an embodiment of the present application, a gate of the ninth PMOS transistor is connected to a gate of the sixth PMOS transistor.

[0033] The above technical solution of the present application has the following advantages compared with the prior art:

[0034] The present application has the following advantages compared with the prior art: BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to make the content of the present application more easily understood, the present application will be further described in detail below according to specific embodiments of the present application and in conjunction with the accompanying drawings, in which,

[0036] Figure 1 is a schematic diagram of a traditional single-pole dynamic comparator circuit structure;

[0037] Figure 2 is a schematic diagram of a double-tail structure dynamic comparator circuit structure;

[0038] Figure 3 is a schematic diagram of a double-regeneration comparator circuit structure;

[0039] Figure 4 is a schematic diagram of a circuit structure of a dynamic comparator suitable for a low-voltage high-speed analog-to-digital converter according to an embodiment of the present application;

[0040] Figure 5 is a schematic diagram of a dynamic comparator circuit according to the present application and Figure 3The simulation results of the amplification effect of the double regeneration comparator circuit on weak signals under the same clock control signal excitation are shown in the schematic diagram.

[0041] The description of the figures is as follows: 1, preamplification module; 2, latch module; 21, main latch module; 22, auxiliary latch module. DETAILED DESCRIPTION

[0042] The application will be further described below with reference to the drawings and specific embodiments, so that those skilled in the art can better understand the application and implement it. However, the embodiments are not limiting to the application.

[0043] As shown in the drawings, Figure 4 the application provides a dynamic comparator suitable for a low-voltage high-speed analog-to-digital converter, comprising: a preamplification module 1 and a latch module 2 cascaded with the preamplification module 1; wherein,

[0044] The preamplification module 1 is connected to a clock control signal CLK and a differential input signal (including a positive electrode VIP and a negative electrode VIN), and under the timing control of the clock control signal CLK, the differential input signal is compared and amplified to obtain a differential amplification signal; the latch module 2 is connected to the clock control signal CLK and an inverted clock control signal CLK z , and under the cooperative control of the clock control signal CLK and the inverted clock control signal CLK z , the differential amplification signal is latched and output to obtain a differential output signal;

[0045] The latch module 2 includes a main latch module 21 and an auxiliary latch module 22, the input end of the main latch module 21 is connected to the output end of the preamplification module 1, the output end of the main latch module 21 is connected to the gate of the corresponding transistor in the auxiliary latch module 22, the auxiliary latch module 22 is connected to the corresponding cross-coupled transistor pair in the main latch module 21 through a cross-coupled transistor pair, and forms a complementary enhancement relationship, and the threshold voltage of the transistor in the auxiliary latch module 22 is greater than the threshold voltage of the corresponding transistor in the main latch module 21, so as to ensure that the main latch module 21 starts regeneration earlier than the auxiliary latch module.

[0046] Further, in the embodiment, the preamplification module 1 includes a differential amplification unit and a reset unit; wherein,

[0047] The input end of the differential amplification unit is connected to the differential input signal, and the control end is connected to the clock control signal CLK. Under the timing control of the clock control signal CLK, the differential amplification unit performs a comparison and amplification operation on the differential input signal, and generates the differential amplification signal at the output end;

[0048] The reset unit is connected to the output end of the differential amplification unit, and its control end is connected to the clock control signal CLK. Under the timing control of the clock control signal CLK, the reset unit performs a reset operation on the output end of the differential amplification unit to restore the potential of the output end to the preset power supply voltage VDD.

[0049] Further, in the embodiment, the differential amplification unit comprises a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a first PMOS transistor P1 and a second PMOS transistor P2.

[0050] The source of the first PMOS transistor P1 is connected to the power supply voltage VDD, the gate thereof is connected to the drain of the second PMOS transistor P2, the drain thereof is connected to the drain of the first NMOS transistor N1, and the drain of the first NMOS transistor N1 corresponds to the negative pole D- of the output of the differential amplification signal; the gate of the first NMOS transistor N1 is connected to the positive pole VIP of the differential input signal, and the source thereof is connected to the drain of the third NMOS transistor N3.

[0051] The source of the second PMOS transistor P2 is connected to the power supply voltage VDD, the gate thereof is connected to the drain of the first PMOS transistor P1, the drain of the second PMOS transistor P2 is connected to the drain of the second NMOS transistor N2, the drain of the second NMOS transistor N2 corresponds to the positive pole D+ of the output of the differential amplification signal, the gate of the second NMOS transistor N2 is connected to the negative pole VIN of the differential input signal, and the source of the second NMOS transistor N2 is connected to the drain of the third NMOS transistor N3.

[0052] The gate of the third NMOS transistor N3 is connected to the clock control signal CLK, and the source thereof is connected to the ground VSS.

[0053] Further, in the embodiment, the reset unit comprises a third PMOS transistor P3 and a fourth PMOS transistor P4.

[0054] The sources of the third PMOS transistor P3 and the fourth PMOS transistor P4 are both connected to the power supply voltage VDD, the gate of the third PMOS transistor P3 is connected to the clock control signal CLK, and the drain thereof is connected to the drain of the first PMOS transistor P1.

[0055] The gate of the fourth PMOS transistor P4 is connected to the clock control signal CLK, and the drain thereof is connected to the drain of the second PMOS transistor P2.

[0056] Specifically, in the embodiment, the main latch module 21 comprises a positive feedback regenerative loop, an input driving circuit and a timing control circuit.

[0057] The positive feedback regenerative loop comprises a fifth NMOS N5, a sixth NMOS N6, a sixth PMOS P6 and a seventh PMOS P7. The fifth NMOS N5 and the sixth PMOS P6 constitute a first cross-coupled branch, the source of the fifth NMOS N5 is grounded, the gate of the fifth NMOS N5 is connected with the gate of the sixth PMOS P6, and the drain of the fifth NMOS N5 and the drain of the sixth PMOS P6 are interconnected to form a first output node OP;

[0058] The sixth NMOS N6 and the seventh PMOS P7 constitute a second cross-coupled branch, the gate of the sixth NMOS N6 is connected with the gate of the seventh PMOS P7, and the drain of the sixth NMOS N6 and the drain of the seventh PMOS P7 are interconnected to form a second output node ON;

[0059] The input driving circuit comprises a seventh NMOS N7 and an eighth NMOS N8. The gate of the seventh NMOS N7 receives a negative pole D- of a differential amplification signal, and the gate of the eighth NMOS N8 receives a positive pole D+ of the differential amplification signal, for converting the output signal of the preamplification module 1 into a driving current of the main latching module 21; the source of the seventh NMOS N7 is grounded VSS, and the drain of the seventh NMOS N7 is connected with the first output node OP;

[0060] The source of the eighth NMOS N8 is grounded VSS, and the drain of the eighth NMOS N8 is connected with the second output node ON;

[0061] The timing control circuit comprises a fifth PMOS P5, the source of the fifth PMOS P5 is connected with a power supply voltage VDD, the gate of the fifth PMOS P5 is connected with an inverted clock control signal CLK z , and the drain of the fifth PMOS P5 is connected with the source of the sixth NMOS N6 and the source of the seventh PMOS P7.

[0062] Further, in the embodiment, the auxiliary latching module 22 comprises a sensing driving circuit, and a first feedback circuit and a second feedback circuit which are symmetrically arranged at two ends of the main latching module 21;

[0063] The sensing driving circuit comprises an eighth PMOS P8 and a ninth PMOS P9; the gate of the eighth PMOS P8 is connected with the first output node OP, the source of the eighth PMOS P8 is connected with the power supply voltage VDD, and the drain of the eighth PMOS P8 is connected with the drain of the ninth NMOS P9; the source of the ninth PMOS P9 is connected with the power supply voltage VDD, and the gate of the ninth PMOS P9 is connected with the second output node ON;

[0064] The first feedback circuit comprises a ninth NMOS transistor N9 and a tenth NMOS transistor N10, the source of the ninth NMOS transistor N9 is grounded, and the drain thereof is connected with the gate of the tenth NMOS transistor N10; the source of the tenth NMOS transistor N10 is grounded, and the drain thereof is connected with the gate of the ninth NMOS transistor N9 and the first output node OP;

[0065] The second feedback circuit comprises an eleventh NMOS transistor N11 and a twelfth NMOS transistor N12, the source of the twelfth NMOS transistor N12 is grounded, and the gate thereof is connected with the drain of the eleventh NMOS transistor N11; the source of the eleventh NMOS transistor N11 is grounded, and the gate thereof is connected with the drain of the twelfth NMOS transistor N12, and the drain thereof is connected with the second output node ON;

[0066] The drain of the ninth PMOS transistor P9 is connected with the drain of the twelfth NMOS transistor N12; and the gate of the ninth PMOS transistor P9 is connected with the gate of the sixth PMOS transistor P6.

[0067] In order to further illustrate the dynamic comparator proposed in the application, the signal comparison is realized through the cooperation of the pre-amplification module 1 and the latch module 2, and the working process mainly comprises a reset stage and a comparison stage, and the specific principle is as follows:

[0068] 1) Reset stage

[0069] When the clock control signal CLK is low "0", the dynamic comparator enters the reset stage, and the working states of each module are as follows:

[0070] The third PMOS transistor P3 and the fourth PMOS transistor P4 in the reset unit are turned on, and the third NMOS transistor N3 in the differential amplification unit is cut off. At this time, the output end of the differential amplification unit, i.e. the positive electrode D+ and the negative electrode D- of the differential amplification signal, are clamped to the power supply voltage VDD (high level) by the reset unit.

[0071] The timing control circuit (fifth PMOS transistor P5) of the main latch module 21 is cut off because the inverted clock control signal CLK z is high; because the positive electrode D+ and the negative electrode D- of the differential amplification signal are pulled to the power supply voltage VDD, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are turned on because the gates thereof are connected with high level, and the first output node OP and the second output node ON are pulled down to the common ground terminal VSS; at the same time, the fifth NMOS transistor N5, the sixth NMOS transistor N6, the sixth PMOS transistor P6 and the seventh PMOS transistor P7 in the main latch module 21 are cut off, and the auxiliary latch module 22 is not activated, and the transistors thereof are all in the cut-off state.

[0072] At this time, the differential output signal outputted by the dynamic comparator through the first output node OP and the second output node ON is low, in a reset standby state.

[0073] 2) Comparison stage

[0074] When the clock control signal CLK is high "1", the dynamic comparator enters the comparison stage, which is further divided into a pre-amplification stage and a regeneration stage:

[0075] (a) Pre-amplification stage

[0076] When the dynamic comparator is in the pre-amplification stage, the differential amplification unit of the pre-amplification module 1 is started, the third NMOS tube N3 is turned on, and the reset unit (the third PMOS tube P3 and the fourth PMOS tube P4) is turned off. The first PMOS tube P1 and the second PMOS tube P2 in the differential amplification unit form a positive feedback structure, which can enhance the amplification capability of the weak differential input signal (positive VIP, negative VIN), and convert the input small voltage difference into the voltage difference of the output differential amplification signal (positive D+ and negative D-), completing the first stage signal amplification.

[0077] The differential amplification signal outputted by the pre-amplification module 1 acts on the latch module 2 through the input drive circuit (the seventh NMOS tube N7 and the eighth NMOS tube N8) of the main latch module 21: the seventh NMOS tube N7 gate is connected to the negative signal D-, and the eighth NMOS tube N8 gate is connected to the positive signal D+, which converts the discharge amount difference of the positive signal D+ and the negative signal D- into the charging amount difference of the first output node OP and the second output node ON. At this time, the positive feedback regeneration of the main latch module 21 has not started.

[0078] (b) Regeneration stage

[0079] The primary regeneration of the main latch module 21 and the secondary regeneration of the auxiliary latch module 22 form a cooperative positive feedback mechanism, and the two-stage time-separated regeneration loops accelerate the convergence of the output signal and suppress the metastable state. The specific working mechanism is as follows:

[0080] When the voltage of the first output node OP and the second output node ON rises to greater than VTH (N5, 6) and less than VDD-VTH (P8, P9), the positive feedback regeneration loop of the main latch module 21 starts: the first cross-coupled branch composed of the fifth NMOS tube N5 and the sixth PMOS tube P6, and the second cross-coupled branch composed of the sixth NMOS tube N6 and the seventh PMOS tube P7 form an "inverter interlocking" structure, which pulls one end of the first output node OP and the second output node ON to low and the other end to high through positive feedback, completing the primary signal regeneration;

[0081] Wherein, VTH(N5,6) represents the threshold voltage of the fifth NMOS tube N5 or the sixth NMOS tube N6; VDD is the power supply voltage; VTH(P8,9) is the threshold voltage of the eighth PMOS tube P8 or the ninth PMOS tube P9, usually negative.

[0082] By setting the threshold mechanism, it is ensured that the starting threshold of the auxiliary latch module 22 (the threshold voltage of the ninth NMOS tube N9 and the twelfth NMOS tube N12) is greater than the threshold voltage of the fifth NMOS tube N5 and the sixth NMOS tube N6 in the main latch module 21. When the voltages of the first output node OP and the second output node ON continue to rise to be greater than VTH(N9,12) and less than VDD-VTH(P8,9), the auxiliary latch module 22 starts regeneration: the first feedback circuit (the ninth NMOS tube N9 and the tenth NMOS tube N10) and the second feedback circuit (the eleventh NMOS tube N11 and the twelfth NMOS tube N12) of the auxiliary latch module 22 form a "complementary enhancement" relationship with the main latch module 21 through the cross-coupled structure, and through two-stage regeneration, the time constant of positive feedback can be reduced, and the voltage differentiation of the first output node OP and the second output node ON can be further accelerated, and finally the two are pulled to the power supply voltage VDD or the ground level VSS, respectively;

[0083] Wherein, VTH(N9,12) represents the threshold voltage of the ninth NMOS tube N9 or the twelfth NMOS tube N12; VTH(P8,9) represents the threshold voltage of the eighth PMOS tube P8 or the ninth PMOS tube P9.

[0084] In detail, further explain the application scenario of high-speed application (nanosecond-level switching) and sub-millivolt-level input differential signal (VDD-VTH(P8,9) is less than 100 mV)

[0085] Before the regeneration starts, when the first output node OP and the second output node ON of the differential output synchronously climb with a small voltage difference, if the transistors of the main latch module 21 and the auxiliary latch module 22 are all in the off state, the eighth PMOS tube P8 and the ninth PMOS tube P9 in the sensing and driving circuit of the auxiliary latch module 22 are turned on, and a parasitic discharge path of the first output node OP and the second output node ON is formed through the turned-on tenth NMOS tube N10 and the eleventh NMOS tube N11, which causes the voltage rising rate to slow down. By reducing the width-length ratio (W / L) of the tenth NMOS tube N10 and the eleventh NMOS tube N11, the discharge current can be reduced, and the regeneration start delay can be reduced.

[0086] ​Because threshold voltages of the ninth NMOS transistor N9 and the twelfth NMOS transistor N12 of the auxiliary latch module 22 are higher than those of the fifth NMOS transistor N5 and the sixth NMOS transistor N6, the main latch module 21 starts regeneration first, and the auxiliary latch module 22 starts regeneration later.

[0087] 1. Reduce the positive feedback time constant: The two-stage regeneration respectively undertakes part of the signal amplification task, compared with single-stage regeneration, the first output node OP and the second output node ON can be pulled to the power supply voltage VDD or the ground level VSS faster;

[0088] 2. Reduce the metastable state probability: If the probability that the first output node OP and the second output node ON are synchronously raised to the threshold voltage of the auxiliary latch module 22 is , and the discharge rate mismatch probability of the tenth NMOS transistor N10 and the eleventh NMOS transistor N11 is 1- , then the metastable state is effectively broken. At this time, the system metastable state probability is reduced from to (when , the probability is reduced to ), achieving an order of magnitude reduction.

[0089] If only the main latch module 21 is relied on, increasing its size to improve the transconductance Gm can accelerate regeneration, but will introduce larger parasitic capacitance, resulting in an increase in time constant; and the auxiliary latch module 22 realizes secondary regeneration through a very small area, improves the regeneration speed without significantly increasing the parasitic, solves the contradiction between “size-parasitic”, and meets the requirements of high speed and low parasitic.

[0090] In the double-regeneration comparator circuit shown in Figure 3 , a cross-coupled inverter is used in the pre-amplification stage, and a positive feedback mechanism is introduced to amplify the discharge amount difference between the positive D+ and the negative D- of the differential amplified signal of the first stage output. However, there are four transistors in the path from the power supply to the ground in this structure, which is not suitable for low power supply voltage scenarios of advanced processes. In contrast, the pre-amplification stage of the present application can achieve the same amplification effect through PMOS latch, and the path from the power supply to the ground only stacks three transistors, which is more suitable for low power supply voltage scenarios of advanced processes.

[0091] In addition, the latch stage of the double-regeneration comparator circuit is prone to the metastable state phenomenon that the output cannot achieve the correct comparison result in the scene where the input voltage difference is small and the clock frequency is fast. The present application realizes faster comparison through the synergistic effect of the two-stage latch circuit by only adding six small-size transistors (NMOS transistors N9-N12 and PMOS transistors P8 and P9) to form an “auxiliary latch”, effectively suppressing the metastable state.

[0092] In analog integrated circuit design, the comparator's ability to process weak signals is one of the core performance indicators. Figure 5 The comparison presents the results within the same clock signal period. Figure 3 The amplification effect of the dual regenerative comparator circuit and the dynamic comparator circuit of this invention on weak signals can be clearly explained from the dimensions of signal response, waveform quality, weak signal adaptability, and metastability suppression.

[0093] In terms of signal response speed, within the clock signal driven working cycle, the voltage waveform of this invention completes signal amplification and level switching earlier. The dual regenerative comparator ( Figure 5 The delayed response of the "traditional structure" indicates that the present invention can capture weak signal changes more quickly and improve the overall operating efficiency of the system.

[0094] Regarding output waveform quality, the edge characteristics and stability of the output waveform are directly related to signal transmission reliability. The output waveform of this invention has steeper rising and falling edges, and clearer, crisper level transitions; the output waveform of the dual regenerative comparator exhibits fluctuations and uneven transitions. This means that the output signal of this invention is more stable, effectively reducing signal interference and lowering the probability of misjudgment.

[0095] However, for weak input differential signals, the amplification process of the dual regenerator comparator is slow, and due to parasitic path and feedback mechanism defects, as well as large signal waveform fluctuations, the amplification gain and linearity for weak signals are poor, resulting in reduced reliability. This invention can quickly and stably amplify weak input signals to a recognizable logic level, such as rapidly reaching a high level, meeting the requirements of low-power, low-voltage advanced processes for weak signal processing.

[0096] Furthermore, regarding metastability suppression, the output signal waveform of the dual regenerative comparator exhibits significant fluctuations and unstable levels (such as waveform spikes). When the input signal voltage difference approaches the threshold or the clock edge is asynchronous with signal changes, it is prone to falling into metastability. The present invention features a stable waveform without such phenomena. Through two-stage latching cooperation, it effectively suppresses metastability, improving the accuracy and stability of the comparison results.

[0097] In summary, the dynamic comparator of this invention, through circuit topology optimization, threshold collaborative design, and multi-level feedback mechanism, significantly outperforms the traditional dual-regenerative comparator structure in key performance dimensions such as signal response, waveform quality, weak signal adaptation, and metastability suppression. It provides a better solution for low-voltage, high-speed, and high-precision signal processing under advanced processes, while maintaining a small area overhead.

[0098] Obviously, the above embodiments are merely example for clearly illustrating, and are not limitation to the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the embodiments are not required to be enumerated, and the obvious changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. A dynamic comparator suitable for use in a low voltage high speed analog to digital converter, characterized by, The application relates to a differential input signal amplification circuit, which comprises a pre-amplification module, a latch module and a differential input signal. The pre-amplification module is connected with a clock control signal and a differential input signal, and performs comparison amplification on the differential input signal under the time sequence control of the clock control signal to obtain a differential amplification signal. The latch module is connected with the pre-amplification module in cascade, and is connected with the clock control signal and an inverse clock control signal, and performs latch output on the differential amplification signal under the cooperative control of the clock control signal and the inverse clock control signal to obtain a differential output signal. The latch module comprises a main latch module and an auxiliary latch module, the input end of the main latch module is connected with the output end of the pre-amplification module, the output end of the main latch module is connected with the gate of a corresponding transistor in the auxiliary latch module, the auxiliary latch module is connected with a corresponding cross-coupled transistor pair in the main latch module through a cross-coupled transistor pair, a complementary enhancement relationship is formed between the cross-coupled transistor pair in the main latch module and the cross-coupled transistor pair in the auxiliary latch module, and the threshold voltage of the transistor in the auxiliary latch module is greater than the threshold voltage of the corresponding transistor in the main latch module, so that the main latch module is started before the auxiliary latch module to regenerate.

2. A dynamic comparator suitable for use in a low voltage high speed analog-to-digital converter according to claim 1, characterized in that, The pre-amplification module comprises a differential amplification unit and a reset unit. The input end of the differential amplification unit is connected with the differential input signal, the control end is connected with the clock control signal, comparison amplification is performed on the differential input signal under the time sequence control of the clock control signal, and the differential amplification signal is generated at the output end. The reset unit is connected with the output end of the differential amplification unit, the control end is connected with the clock control signal, and reset operation is performed on the output end of the differential amplification unit under the time sequence control of the clock control signal, so that the potential of the output end is restored to a preset power supply voltage.

3. A dynamic comparator suitable for use in a low voltage high speed analog-to-digital converter according to claim 2, characterized in that, The differential amplification unit comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor and a second PMOS transistor. The source of the first PMOS transistor is connected with a power supply voltage, the gate is connected with the drain of the second PMOS transistor, and the drain is connected with the drain of the first NMOS transistor. The gate of the third NMOS transistor is connected with the clock control signal, and the source is connected with the ground. The reset unit comprises a third PMOS transistor and a fourth PMOS transistor.

4. A dynamic comparator suitable for use in a low voltage high speed analog-to-digital converter according to claim 3, characterized in that, The source of the third PMOS transistor and the source of the fourth PMOS transistor are connected with the power supply voltage, the gate of the third PMOS transistor is connected with the clock control signal, and the drain is connected with the drain of the first PMOS transistor. ​ The gate of the fourth PMOS tube is connected to the clock control signal, and the drain thereof is connected to the drain of the second PMOS tube.

5. The dynamic comparator suitable for use in a low voltage high speed analog-to-digital converter according to claim 1, wherein, The main latch module comprises a positive feedback regenerative loop and an input drive circuit; The positive feedback regenerative loop comprises a fifth NMOS tube, a sixth NMOS tube, a sixth PMOS tube and a seventh PMOS tube; the fifth NMOS tube and the sixth PMOS tube form a first cross-coupled branch, the gates of which are connected to each other and connected to the drain of the sixth NMOS tube, and the drains of which are connected to each other to form a first output node (OP); the sixth NMOS tube and the seventh PMOS tube form a second cross-coupled branch, the gates of which are connected to each other and connected to the drain of the fifth NMOS tube, and the drains of which are connected to each other to form a second output node (ON); The input drive circuit comprises a seventh NMOS tube and an eighth NMOS tube, the gates of which receive a negative pole and a positive pole of a differential amplification signal respectively, for converting the output signal of the preamplification module into a drive current of the main latch module; the drain of the seventh NMOS tube is connected to the first output node, the drain of the eighth NMOS tube is connected to the second output node, and the sources of the seventh NMOS tube and the eighth NMOS tube are both grounded.

6. A dynamic comparator suitable for use in a low voltage high speed analog-to-digital converter according to claim 5, characterized in that, The main latch module further comprises a timing control circuit, which comprises a fifth PMOS tube, the source of which is connected to a power supply voltage, the gate of which is connected to an inverted clock control signal, and the drain of which is connected to the sources of the sixth NMOS tube and the seventh PMOS tube.

7. The dynamic comparator suitable for use in a low voltage high speed analog-to-digital converter according to claim 5, wherein, The auxiliary latch module comprises a first feedback circuit and a second feedback circuit which are symmetrically arranged at two ends of the main latch module; The first feedback circuit comprises a ninth NMOS tube and a tenth NMOS tube, the source of the ninth NMOS tube is grounded, and the drain thereof is connected to the gate of the tenth NMOS tube; the source of the tenth NMOS tube is grounded, and the drain thereof is connected to the gate of the ninth NMOS tube and the first output node; The second feedback circuit comprises an eleventh NMOS tube and a twelfth NMOS tube, the source of the twelfth NMOS tube is grounded, and the gate thereof is connected to the drain of the eleventh NMOS tube; the source of the eleventh NMOS tube is grounded, and the gate thereof is connected to the drain of the twelfth NMOS tube, and the drain thereof is connected to the second output node.

8. A dynamic comparator suitable for use in a low voltage high speed analog-to-digital converter according to claim 7, characterized in that, The auxiliary latch module further comprises a sensing drive circuit, which comprises an eighth PMOS tube and a ninth PMOS tube; wherein the gate of the eighth PMOS tube is connected to the first output node, the source thereof is connected to the power supply voltage, and the drain thereof is connected to the drain of the ninth NMOS tube; the source of the ninth PMOS tube is connected to the power supply voltage, the gate thereof is connected to the second output node, and the drain thereof is connected to the drain of the twelfth NMOS tube.

9. A dynamic comparator suitable for use in a low voltage high speed analog-to-digital converter according to claim 8, characterized in that, The gate of the ninth PMOS tube is connected to the gate of the sixth PMOS tube.

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