Shield gate field effect transistor and manufacturing method

Abstract

The invention provides a shield gate field effect transistor and a manufacturing method thereof, and relates to the technical field of semiconductors. The shield gate field effect transistor comprises a control gate and a shield gate, the control gate comprises a plurality of main gate electrodes and a plurality of interconnected gate electrodes, two adjacent main gate electrodes are arranged in a staggered manner, and the end parts of the two adjacent main gate electrodes are connected through the interconnected gate electrodes to form a square structure; the shield gate comprises a field plate structure and a contact structure, the contact structure is connected with the field plate structure, the field plate structure is located below the control gate, and the contact structure is located in the square structure; the projection of the shielding grid in the vertical direction is overlapped with the projection of the interconnection grid in the vertical direction, and the projection of the shielding grid and the projection of the main body grid in the vertical direction are spaced. The shield gate field effect transistor and the manufacturing method thereof have the advantage that the dynamic latch-up effect can be effectively inhibited.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a shield gate field effect transistor and a manufacturing method thereof. BACKGROUND

[0002] The shield gate MOS structure is based on the trench gate structure, and a shield gate (SG) is introduced, which is equivalent to a field plate structure and can provide lateral auxiliary depletion, so as to realize two-dimensional electric field depletion in the drift region, so that the original triangular electric field distribution becomes an approximately rectangular electric field distribution, that is, the charge balance effect. In this way, the drift region EPI resistance can be greatly reduced, the withstand voltage is improved, and the on-resistance is reduced. Therefore, under the same resistance specification, the area of the chip can be greatly reduced.

[0003] However, after the shield gate is introduced, some parasitic elements will be introduced accordingly, such as Cdsg, Rsg and Cgsg. When the drain voltage changes, the dynamic latch effect will be caused through these elements, and there are typically two kinds as follows:

[0004] 1. When the drain voltage changes, a voltage drop Vsg will be generated on the shield gate through the coupling effect of Cdsg and Rsg. The voltage drop will cause uneven distribution of the shield gate potential, thereby causing current concentration and reducing the avalanche withstand.

[0005] 2. When the shield gate has a potential change, a voltage drop will be generated on the gate through the coupling effect of Cgsg, which will cause the gate voltage to oscillate or even be mis-opened, causing the punch-through phenomenon of the upper and lower tubes of the bridge circuit.

[0006] In summary, the shield gate MOS structure in the prior art has the problem of being prone to causing the dynamic latch effect. SUMMARY

[0007] The purpose of the present application is to provide a shield gate field effect transistor and a manufacturing method thereof, so as to solve the problem of the shield gate MOS structure in the prior art being prone to causing the dynamic latch effect.

[0008] In order to achieve the above purpose, the technical solutions adopted by the embodiments of the present application are as follows:

[0009] On the one hand, the present application provides a shield gate field effect transistor, which comprises a control gate and a shield gate. The control gate comprises a plurality of main gates and a plurality of interconnection gates. Adjacent two main gates are staggered arranged, and the end positions of adjacent two main gates are connected through the interconnection gates, and form a square structure.

[0010] The shielding gate comprises a field plate structure and a contact structure, the contact structure is connected with the field plate structure, the field plate structure is located below the control gate, and the contact structure is located in the square structure;

[0011] A projection of the shielding gate in a vertical direction overlaps a projection of the interconnection gate in the vertical direction and is spaced from a projection of the main gate in the vertical direction.

[0012] Optionally, a surface of the contact structure is flush with a surface of the control gate.

[0013] Optionally, a width of the field plate structure is less than a length of the interconnection gate.

[0014] Optionally, the shielding gate field effect transistor further comprises an ILD layer and a source metal, the ILD layer is located on a surface of the control gate and the shielding gate, the source metal is located on a surface of the ILD layer, the ILD layer is provided with a first contact hole opposite to the contact structure, the first contact hole is filled with a contact metal, and the contact structure is connected to the source metal through the contact metal.

[0015] Optionally, the shielding gate field effect transistor further comprises a device layer, the device layer is provided with a groove, and the control gate and the shielding gate are located in the groove.

[0016] Optionally, the device layer comprises an epitaxial layer, a P-type body region and an N-type source region, and the epitaxial layer, the P-type body region and the N-type source region are arranged layer by layer.

[0017] The shielding gate field effect transistor further comprises an ILD layer and a source metal, the ILD layer is located on a surface of the control gate, the shielding gate and the N-type source region, the source metal is located on a surface of the ILD layer, the ILD layer is provided with a second contact hole, the second contact hole extends into the P-type body region, the second contact hole is filled with a contact metal, and the P-type body region is connected to the source metal through the contact metal.

[0018] Optionally, the number of the control gate and the shielding gate is multiple, and multiple control gates and shielding gates form multiple array-arranged gate structures, and each gate structure is located in a groove.

[0019] Each second contact hole is located between two adjacent gate structures.

[0020] Optionally, the second contact hole at least comprises a second contact hole located on the same horizontal line as the interconnection gate.

[0021] In another aspect, the embodiments of the present application also provide a method for manufacturing a shielded gate field effect transistor, which is used for manufacturing the shielded gate field effect transistor described above, and the method comprises the following steps:

[0022] providing an epitaxial layer;

[0023] etching a trench on the epitaxial layer;

[0024] manufacturing a control gate and a shield gate in the trench; wherein the control gate comprises a plurality of main gate electrodes and a plurality of interconnection gate electrodes, two adjacent main gate electrodes are staggered, the end positions of the two adjacent main gate electrodes are connected by the interconnection gate electrodes, and a square structure is formed; the shield gate comprises a field plate structure and a contact structure, the contact structure is connected with the field plate structure, the field plate structure is located below the control gate, and the contact structure is located in the square structure; the projection of the shield gate in the vertical direction overlaps the projection of the interconnection gate electrode in the vertical direction, and is spaced from the projection of the main gate electrode in the vertical direction.

[0025] Optionally, the step of manufacturing the control gate and the shield gate in the trench comprises the following steps:

[0026] growing a first field oxide layer in the trench;

[0027] etching the first field oxide layer, and depositing the field plate structure;

[0028] growing a second field oxide layer on the surface of the first field oxide layer;

[0029] etching the second field oxide layer, and depositing the contact structure, the main gate electrode and the interconnection gate electrode.

[0030] Compared with the prior art, the present application has the following beneficial effects:

[0031] The present application provides a shielded gate field effect transistor and a manufacturing method thereof, the shielded gate field effect transistor comprises a control gate and a shield gate, the control gate comprises a plurality of main gate electrodes and a plurality of interconnection gate electrodes, two adjacent main gate electrodes are staggered, the end positions of the two adjacent main gate electrodes are connected by the interconnection gate electrodes, and a square structure is formed; the shield gate comprises a field plate structure and a contact structure, the contact structure is connected with the field plate structure, the field plate structure is located below the control gate, and the contact structure is located in the square structure; the projection of the shield gate in the vertical direction overlaps the projection of the interconnection gate electrode in the vertical direction, and is spaced from the projection of the main gate electrode in the vertical direction.

[0032] By the setting mode, the shielding gate and the control gate are isolated by the thick gate oxide layer, and the projection of the shielding gate in the vertical direction only overlaps with the projection of the interconnection gate in the vertical direction, so that the intersection area between the shielding gate and the control gate is reduced, and then the gate-source coupling capacitance Cgsg is reduced. Moreover, the contact structure is independently led out, so that the contact structure is directly connected to the source metal, the gate-source coupling resistance Rsg is reduced to improve the shielding gate potential uniformity, and the dynamic latch effect is effectively inhibited.

[0033] In order to make the above objectives, characteristics and advantages of the present application more apparent, clear and easy to understand, the following will specifically describe a preferred embodiment, and the accompanying drawings will be described in detail as follows. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0035] Figure 1 A structure schematic diagram of a shielding gate field effect transistor in the prior art.

[0036] Figure 2 A structure schematic diagram of a control gate and a shielding gate provided by the embodiments of the present application.

[0037] Figure 3 A top view of a shielding gate field effect transistor provided by the embodiments of the present application.

[0038] Figure 4 A structure schematic diagram of a shielding gate field effect transistor provided by the embodiments of the present application. Figure 3 A cross-sectional schematic diagram along the cutting line AA' in the structure schematic diagram.

[0039] Figure 5 A structure schematic diagram of a shielding gate field effect transistor provided by the embodiments of the present application. Figure 3 A cross-sectional schematic diagram along the cutting line BB' in the structure schematic diagram.

[0040] Figure 6 A structure schematic diagram of a shielding gate field effect transistor provided by the embodiments of the present application. Figure 3 A cross-sectional schematic diagram along the cutting line CC' in the structure schematic diagram.

[0041] In the drawings:

[0042] 110-control gate; 111-main gate; 112-interconnection gate; 120-shielding gate; 121-field plate structure; 122-contact structure. DETAILED DESCRIPTION

[0043] To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will be combined with the accompanying drawings to make a clear and complete description of the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations.

[0044] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative labor are within the scope of protection of the present application.

[0045] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0046] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0047] The following will be combined with the accompanying drawings to make a detailed description of some embodiments of the present application. The following embodiments and features in the embodiments can be combined with each other without conflict.

[0048] Please refer to Figure 1 , a schematic diagram of a structure of a shield gate field effect transistor in the prior art, wherein Gate represents a control gate, SG represents a shield gate, Nsub represents an N-type substrate, Nepi represents an N-type epitaxial layer, Pbody represents a P-type body region, N+ represents an N-type source region, contact represents a contact hole, Cgsg represents a gate-source coupling capacitor, Rsg represents a gate-source coupling resistor, and Cdsg represents a source-drain coupling capacitor.

[0049] However, as described in the background, the shield gate field effect transistor is prone to cause a dynamic latch-up effect. The dynamic latch-up effect generally includes two types. The first type of dynamic latch-up effect is that when the drain voltage changes, a voltage drop Vsg is generated on the shield gate through the coupling effect of Cdsg and Rsg, which causes uneven distribution of the shield gate potential, thereby reducing the avalanche tolerance of the current concentration. In order to suppress the first type of dynamic latch-up effect, it is necessary to reduce the gate-source coupling resistor Rsg.

[0050] The second type of dynamic latch effect is that when there is a potential change in the shield gate, a voltage drop is generated on the gate through the coupling effect of Cgsg, which can cause gate voltage oscillation or even false turn-on, and can cause punch-through of the upper and lower transistors in the bridge circuit. In order to suppress the second type of dynamic latch effect, it is necessary to reduce the gate-source coupling capacitance Cgsg to reduce the coupling between the shield gate and the source.

[0051] Therefore, in order to solve the above problems, the shield gate field effect transistor provided by the embodiments of the present application can improve the dynamic latch phenomenon of the shield gate MOS by simultaneously reducing the gate-source coupling resistance Rsg and the gate-source coupling capacitance Cgsg.

[0052] The shield gate field effect transistor provided by the present application is exemplarily described as follows:

[0053] As an optional implementation, please refer to Figure 2 and Figure 3 The shield gate field effect transistor includes a control gate 110 and a shield gate 120. The control gate 110 includes a plurality of main gates 111 and a plurality of interconnection gates 112. Adjacent two main gates 111 are staggered. The end positions of the adjacent two main gates 111 are connected by the interconnection gate 112, and a square structure is formed. The shield gate 120 includes a field plate structure 121 and a contact structure 122. The contact structure 122 is connected with the field plate structure 121. The field plate structure 121 is located below the control gate 110. The contact structure 122 is located in the square structure. The projection of the shield gate 120 in the vertical direction overlaps the projection of the interconnection gate 112 in the vertical direction, and is spaced from the projection of the main gate 111 in the vertical direction.

[0054] In the above manner, the shield gate 120 and the control gate 110 can be isolated by a relatively thick gate oxide layer. The projection of the shield gate 120 in the vertical direction only overlaps the projection of the interconnection gate 112 in the vertical direction. Therefore, the intersection area between the shield gate 120 and the control gate 110 is reduced, and the gate-source coupling capacitance Cgsg is reduced. In addition, the contact structure 122 is independently led out, so it is convenient to be directly connected to the source metal. The gate-source coupling resistance Rsg can be reduced to improve the potential uniformity of the shield gate 120, and the dynamic latch effect can be effectively suppressed.

[0055] Please refer to Figure 4 , Figure 4 for Figure 3 the cross-sectional view of the cutting line AA' in FIG. 1B. The shield gate field effect transistor further includes a device layer. The control gate 110 and the shield gate 120 are located in a trench in the device layer.

[0056] The device layer comprises an epitaxial layer, a P-type body region, and an N-type source region, which are arranged layer by layer; the shield gate field effect transistor further comprises an ILD layer and a source metal, the ILD layer is located on the surface of the control gate 110, the shield gate 120, and the N-type source region, and the source metal is located on the surface of the ILD layer; the ILD layer is provided with a second contact hole extending into the P-type body region, and the second contact hole is filled with a contact metal; the P-type body region is connected to the source metal through the contact metal.

[0057] In addition, the number of the control gate 110 and the shield gate 120 is multiple, and the multiple control gates 110 and the multiple shield gates 120 form multiple array-arranged gate structures, each of which is located in a groove; each second contact hole is located between two adjacent gate structures.

[0058] In addition, in the second contact hole, at least a second contact hole is located on the same horizontal line as the interconnection gate 112.

[0059] It can be understood that, through the arrangement, in the AA' direction, the cross-sectional structure of the shield gate 120 field effect transistor provided by the application is consistent with the conventional structure, but the interconnection gate 112 is the gate, not the main gate 111, and on this basis, the shield gate field effect transistor provided by the application is not affected by the structure adjustment of the shield gate 120 and the control gate 110, and although the interconnection gate 112 and the field plate structure 121 exist in the projection in the vertical direction, the overall influence of the gate-source coupling capacitance Cgsg on the device is small.

[0060] Please refer to Figure 5 , Figure 5 for Figure 3 the cross-sectional view of the cutting line BB' in FIG. 1B, wherein the shield gate field effect transistor further comprises a device layer, and the device layer is provided with a groove, and the control gate 110 and the shield gate 120 are located in the groove.

[0061] In the cross-sectional view of the cutting line BB' in FIG. 1B, the surface of the contact structure 122 is flush with the surface of the control gate 110, the width of the field plate structure 121 is less than the length of the interconnection gate 112, the shield gate field effect transistor further comprises an ILD layer and a source metal, the ILD layer is located on the surface of the control gate 110 and the shield gate 120, and the source metal is located on the surface of the ILD layer; the ILD layer is provided with a first contact hole at a position opposite to the contact structure 122, the first contact hole is filled with a contact metal, and the contact structure 122 is connected to the source metal through the contact metal.

[0062] Therefore, the shield gate 120 is buried in the field oxide layer inside the trench, and provides a charge balance effect as a field plate to adjust the electric field distribution. Moreover, the buried shield gate 120 is periodically connected to the source metal through the first contact hole, so that the gate-source coupling resistance Rsg can be reduced to improve the shield gate 120 potential uniformity, thereby suppressing the first type of dynamic latch-up effect.

[0063] Please refer to Figure 6 , Figure 6 for Figure 3 the cross-sectional view of the cutting line CC' of the buried shield gate 120. As shown in the figure, along the direction of the cutting line CC', the gate and the channel unit of the buried shield gate 120 are staggered and interlinked on the left and right sides of the control gate. The control gate 110 and the buried shield gate 120 are separated by a thick field oxide layer, which reduces the overlapping area, thereby almost eliminating the parasitic capacitance Cgsg between the gate and the shield gate 120, reducing the coupling effect and thereby suppressing the second type of dynamic latch-up effect.

[0064] Therefore, by using the shield gate field effect transistor provided in the present application, the Rsg and Cgsg can be reduced at the same time, thereby greatly suppressing the dynamic latch-up caused by the parasitic elements of the shield gate 120.

[0065] Based on the above implementation manner, the present application further provides a shield gate field effect transistor manufacturing method, which comprises the following steps:

[0066] S102, providing an epitaxial layer.

[0067] S104, etching a trench based on the epitaxial layer.

[0068] S106, manufacturing a control gate and a shield gate based on the trench; wherein the control gate comprises a plurality of main gates and a plurality of interlinked gates, the adjacent two main gates are staggered and arranged, and the end positions of the adjacent two main gates are connected through the interlinked gates to form a square structure; the shield gate comprises a field plate structure and a contact structure, the contact structure is connected with the field plate structure, the field plate structure is located below the control gate, and the contact structure is located in the square structure; the projection of the shield gate in the vertical direction overlaps with the projection of the interlinked gate in the vertical direction, and is spaced from the projection of the main gate in the vertical direction.

[0069] The step S106 comprises the following steps:

[0070] S1061, growing a first field oxide layer based on the trench.

[0071] S1062, etching the first field oxide layer and depositing a field plate structure.

[0072] S1063, growing a second field oxide layer based on the surface of the first field oxide layer.

[0073] S1064, etching the second field oxide layer, and depositing the contact structure, the main gate and the interconnection gate.

[0074] That is, in the present application, the shielded gate field effect transistor can be manufactured in two layers. After a relatively large trench is etched, a first field oxide layer can be grown in the trench by oxidation or deposition process, then the first field oxide layer is etched to form a first sub-trench, and polycrystalline silicon is deposited in the first sub-trench to form a field plate structure.

[0075] It should be noted that when the first sub-trench is etched, part of the first field oxide layer at the bottom needs to be reserved, so the depth of the first sub-trench is less than the thickness of the first field oxide layer during the etching process. On this basis, when the field plate structure is manufactured, the first field oxide layer surrounds the field plate structure.

[0076] Then the second field oxide layer is grown, which needs to fill the entire trench, and a second sub-trench is etched based on the second field oxide layer. The second sub-trench includes sub-trenchs corresponding to the contact structure, the main gate and the interconnection gate. It should be noted that the second sub-trench corresponding to the contact structure needs to be etched to expose the field plate structure, and the depth of the second sub-trench corresponding to the main gate and the interconnection gate needs to be less than the thickness of the second field oxide layer. Finally, polycrystalline silicon is deposited based on the second sub-trench to form the contact structure, the main gate and the interconnection gate.

[0077] It can be understood that the first field oxide layer and the second field oxide layer form a field oxide layer as a whole, and surround the control gate and the shielded gate.

[0078] In summary, the present application provides a shielded gate field effect transistor and a manufacturing method thereof. The shielded gate field effect transistor includes a control gate and a shielded gate. The control gate includes a plurality of main gates and a plurality of interconnection gates. Adjacent two main gates are staggered arranged, and the end positions of the adjacent two main gates are connected by the interconnection gates to form a square structure. The shielded gate includes a field plate structure and a contact structure. The contact structure is connected with the field plate structure. The field plate structure is located below the control gate, and the contact structure is located in the square structure. The projection of the shielded gate in the vertical direction overlaps with the projection of the interconnection gate in the vertical direction, and is spaced apart from the projection of the main gate in the vertical direction.

[0079] Through the above arrangement, the shielded gate and the control gate are isolated by a relatively thick gate oxide layer, and the projection of the shielded gate in the vertical direction only overlaps with the projection of the interconnection gate in the vertical direction. Therefore, the intersection area between the shielded gate and the control gate is reduced, and thus the gate-source coupling capacitance Cgsg is reduced. In addition, the contact structure is independently led out, so it is convenient to be directly connected to the source metal, which can reduce the gate-source coupling resistance Rsg to improve the shielded gate potential uniformity and effectively suppress the dynamic latch-up effect.

[0080] The above description is only the preferred embodiment of the present application, and is not intended to limit the present application. The present application can have various modifications and changes for those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0081] It is apparent for those skilled in the art that the present application is not limited to the details of the above-described exemplary embodiments, but can be realized in other concrete forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered in all aspects as illustrative and not restrictive, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended to embrace all changes falling within the meaning and range of equivalents of the claims. Any reference signs in the claims should not be considered as limiting the claims involved.

Claims

1. A shielded gate field effect transistor, characterized by The shielding gate field effect transistor comprises a control gate and a shielding gate, the control gate comprises a plurality of main gates and a plurality of interconnecting gates, two adjacent main gates are staggered, and the end positions of the two adjacent main gates are connected by the interconnecting gates to form a square structure. The shielding gate comprises a field plate structure and a contact structure, the contact structure is connected with the field plate structure, the field plate structure is located below the control gate, and the contact structure is located in the square structure. The projection of the shielding gate in the vertical direction overlaps the projection of the interconnecting gate in the vertical direction and is spaced from the projection of the main gate in the vertical direction.

2. The shielded gate field effect transistor of claim 1, wherein, The surface of the contact structure is flush with the surface of the control gate.

3. The shielded gate field effect transistor of claim 1, wherein, The width of the field plate structure is less than the length of the interconnecting gate.

4. The shielded gate field effect transistor of claim 1, wherein, The shielding gate field effect transistor further comprises an ILD layer and a source metal, the ILD layer is located on the surface of the control gate and the shielding gate, the source metal is located on the surface of the ILD layer, the ILD layer is provided with a first contact hole at a position opposite to the contact structure, the first contact hole is filled with a contact metal, and the contact structure is connected to the source metal through the contact metal.

5. The shielded gate field effect transistor of claim 1, wherein, The shielding gate field effect transistor further comprises a device layer, the device layer is provided with a trench, and the control gate and the shielding gate are located in the trench.

6. The shielded gate field effect transistor of claim 5, wherein, The device layer comprises an epitaxial layer, a P-type body region and an N-type source region, and the epitaxial layer, the P-type body region and the N-type source region are arranged layer by layer. The shielding gate field effect transistor further comprises an ILD layer and a source metal, the ILD layer is located on the surface of the control gate, the shielding gate and the N-type source region, the source metal is located on the surface of the ILD layer, the ILD layer is provided with a second contact hole, the second contact hole extends into the P-type body region, the second contact hole is filled with a contact metal, and the P-type body region is connected to the source metal through the contact metal.

7. The shielded gate field effect transistor of claim 6, wherein the gate electrode is formed of a material selected from the group consisting of polysilicon, amorphous silicon, and metal. The number of the control gate and the shielding gate is a plurality, and a plurality of gate structures arranged in an array are formed by the control gate and the shielding gate, and each gate structure is located in a trench. Each second contact hole is located between two adjacent gate structures.

8. The shielded gate field effect transistor of claim 7, wherein, In the second contact hole, at least one second contact hole is located on the same horizontal line as the interconnecting gate.

9. A method of fabricating a shielded gate field effect transistor, the method comprising: The method for manufacturing the shielding gate field effect transistor as claimed in any one of claims 1 to 8 comprises: providing an epitaxial layer; etching a trench on the epitaxial layer; The control gate and the shielding gate are made in the trench, wherein the control gate comprises a plurality of main gates and a plurality of interconnection gates, two adjacent main gates are staggered, the end positions of two adjacent main gates are connected by the interconnection gates, and a square structure is formed; the shielding gate comprises a field plate structure and a contact structure, the contact structure is connected with the field plate structure, the field plate structure is located below the control gate, and the contact structure is located in the square structure; the projection of the shielding gate in the vertical direction overlaps the projection of the interconnection gate in the vertical direction, and is spaced from the projection of the main gate in the vertical direction.

10. The method of claim 9, wherein the method further comprises forming a gate dielectric layer on the substrate prior to forming the gate electrode. 10 The step of making the control gate and the shielding gate in the trench comprises: growing a first field oxide layer in the trench; etching the first field oxide layer and depositing a field plate structure; growing a second field oxide layer on the surface of the first field oxide layer; etching the second field oxide layer and depositing a contact structure, a main gate and an interconnection gate.

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