Semiconductor structure for BCD process and manufacturing method thereof
By using decoupled plasma nitriding and combined annealing processes in the BCD process, the performance and yield issues of MPS diode fuse structures under high integration were solved, improving the performance and yield of the fuse structure and saving costs.
Patent Information
- Application Number
- CN202511140758.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-14
- Publication Date
- 2025-11-21
AI Technical Summary
In the BCD process, the performance and yield of the electric fuse structure composed of MPS diodes and metal silicides are adversely affected under high integration, especially when the linewidth is small. The fuse is prone to agglomeration during the annealing process, which leads to the failure of the electric fuse structure.
A decoupled plasma nitriding process is used to form a nitriding layer on the surface of the MPS diode, which increases the diffusion barrier height during the reaction between Co and Si, raises the silicide phase transition temperature, and combines P-type ion implantation and metal silicide annealing processes to avoid or reduce metal silicide agglomeration. At the same time, the annealing process is combined to save costs.
This improved the performance and yield of the electrofused wire structure, prevented the agglomeration of metal silicides during the annealing process, and saved manufacturing costs.
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Figure CN121001392A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure for BCD process and a manufacturing method thereof. BACKGROUND
[0002] Power integrated IC is widely used in power management, motor drive, automotive electronics and industrial control fields. BCD process refers to a process technology of integrating bipolar, CMOS, DMOS, logic devices and various resistors, capacitors and diodes on the same chip. It has the characteristics of low cost, easy packaging, easy design and simpler peripheral chip, and has rapidly developed into the mainstream technology in the field of power integrated IC. Bipolar transistor in BCD technology has high analog accuracy and is mainly used in analog circuits, CMOS has high integration and is mainly used in logic circuits, and DMOS has high power (high voltage) characteristics and is often used as a switch.
[0003] Among them, the BCD process also integrates MPS diodes (Merged PiN Schottky Diode). The MPS diode skillfully combines PiN diode and Schottky diode to realize low conduction loss and fast switching characteristics in high-voltage and high-current applications. Some MPS diodes also form eFuse structures (electrical fuse structures) through metal silicides on their surfaces. Compared with the electrical fuse structure composed of MPS diode and metal silicide in the ordinary platform, the performance and yield of the electrical fuse structure composed of MPS diode and metal silicide in the BCD process are greatly adversely affected due to the higher integration (such as smaller line width) in the BCD process. SUMMARY
[0004] To solve the above technical problems, the present application provides a manufacturing method of a semiconductor structure for BCD process, comprising:
[0005] providing a substrate, forming a patterned mask layer on the surface of the substrate, and the opening of the patterned mask layer exposes the N-type doped region on the surface of the substrate;
[0006] performing P-type ion implantation to form several P-type heavily doped regions in the N-type doped region to form an MPS diode in the substrate;
[0007] removing the patterned photoresist layer and the oxide layer on the surface of the substrate;
[0008] performing decoupling plasma nitridation process to form a nitride layer on the surface of the substrate;
[0009] forming a metal silicide layer on the surface of the substrate, and taking the metal silicide as a fuse on the MPS diode.
[0010] Optionally, the step of forming the metal silicide layer further comprises:
[0011] forming a metal layer and a barrier layer sequentially to conformally cover the substrate surface;
[0012] performing a first annealing to react part of the metal layer with silicon in the substrate to form a first silicide;
[0013] performing a wet process to remove the barrier layer and unreacted metal layer;
[0014] performing a second annealing to react part of the first silicide with the nitride layer to form a second silicide, and to reserve part of the first silicide, with the first silicide and the second silicide as the metal silicide layer, the second annealing having a temperature greater than that of the first annealing.
[0015] Optionally, the metal barrier layer comprises a titanium nitride layer.
[0016] Optionally, the metal layer comprises one or more of cobalt, nickel or titanium.
[0017] Optionally, the P-type heavily doped regions are activated by the second annealing.
[0018] Optionally, the metal layer comprises cobalt, the second annealing comprises a rapid thermal annealing process, the second annealing has an annealing temperature of 850-950°C and an annealing time of 5-120 seconds.
[0019] Optionally, the metal layer comprises cobalt, the second annealing comprises a laser annealing process, the second annealing process has an annealing temperature of 1000-1200°C and an annealing time of 200-1000 microseconds.
[0020] Optionally, the decoupled plasma nitridation process has a power of 1000-2250W and a processing time of 10-120 seconds.
[0021] Based on another aspect of the present application, there is also provided a semiconductor structure for a BCD process, comprising:
[0022] a substrate;
[0023] a MPS diode disposed in the substrate, the MPS diode comprising an N-type doped region and a plurality of P-type heavily doped regions disposed in the N-type doped region
[0024] a metal silicide layer disposed on the N-type doped region and the P-type heavily doped regions and serving as a fuse disposed on the MPS diode;
[0025] A nitride layer is disposed between the MPS diode and the metal silicide layer.
[0026] Optionally, the metal silicide layer includes a first silicide with high resistance and a second silicide with low resistance.
[0027] In summary, the present application provides a semiconductor structure for BCD process and a manufacturing method thereof. The manufacturing method includes providing a substrate, forming a patterned mask layer on the surface of the substrate, the opening of the patterned mask layer exposing the N-type doped region on the surface of the substrate; performing P-type ion implantation to form a plurality of P-type heavily doped regions on the N-type doped region and form an MPS diode in the substrate; removing the patterned photoresist layer and the oxide layer on the surface of the substrate; performing a decoupled plasma nitridation process to form a nitride layer on the surface of the substrate; and forming a metal silicide layer on the surface of the substrate and using the metal silicide as a fuse on the MPS diode. In the present application, the nitride layer formed by the decoupled plasma nitridation process is disposed on the surface of the MPS diode, which can increase the diffusion barrier height of Si into CoSi during the reaction of Co and Si, resulting in an increase in the temperature for forming low-resistance and agglomerated silicide, which is equivalent to increasing the phase transition temperature from high-resistance silicide to low-resistance silicide, thereby avoiding or reducing the agglomeration of the metal silicide as a fuse during the annealing process, and improving the performance and yield of the electrical fuse structure. In addition, the present application can perform P-type ion implantation to form a plurality of P-type heavily doped regions on the N-type doped region, and can not immediately perform the annealing process, but combine the annealing process for activating the P-type heavily doped region with the subsequent annealing process for forming the metal silicide, thereby saving one annealing process and reducing costs. BRIEF DESCRIPTION OF DRAWINGS
[0028] Those skilled in the art will understand that the provided drawings are for the purpose of better illustrating the present application and do not constitute any limitation on the scope of the present application.
[0029] Figure 1 A flowchart for forming an electrical fuse structure composed of an MPS diode and a metal silicide in the related art;
[0030] Figure 2 A flowchart of the manufacturing method of the semiconductor structure for BCD process provided in the present embodiment;
[0031] Figures 3A-3G A structure schematic diagram corresponding to the corresponding steps of the manufacturing method of the semiconductor structure for BCD process provided in the present embodiment.
[0032] In the attached figures: 10-substrate; 11-NBL layer; 12-N-type doped region; 12a-first N-type doped region; 12b-second N-type doped region; 13-shallow trench isolation structure; 14-oxide layer; 21-patterned mask layer; 22-P-type heavily doped region; 23-nitride layer; 24-metal layer; 25-barrier layer; 26a-first silicide layer; 26b-second silicide layer; 26-metal silicide layer. Detailed Implementation
[0033] Figure 1 This is a flowchart illustrating the formation of an electric fuse structure composed of an MPS diode and a metal silicide in related technologies. As described in the background section, in related technologies, such as... Figure 1 As shown, the steps for forming the above-described fuse structure include: First, performing step S1', P+ ion implantation and annealing on the substrate to form a P+ doped region and activate P+ ions for forming an MPS diode in the substrate. Next, in step S2', removing the oxide layer on the substrate surface and forming cobalt metal to cover the MPS diode surface. Next, performing step S3', performing a first annealing to react some of the cobalt with silicon in the substrate to form high-resistivity cobalt silicide. Next, performing step S4', removing the remaining unreacted cobalt. Next, performing step S5', performing a second annealing to react the high-resistivity cobalt silicide into low-resistivity cobalt silicide, and using the low-resistivity cobalt silicide as the fuse of the MPS diode. The annealing temperature of the second annealing needs to be greater than 800°C and the annealing time greater than 30 seconds, for example, the commonly used annealing temperature in the industry is 820-850°C and the annealing time is 30 seconds. However, due to the small linewidth of MPS diodes in the BCD process (there are alternating ohmic and Schottky contact regions, both with small linewidths), the agglomeration temperature of the fuse (low-resistance cobalt silicide) will drop below 820℃ due to the linewidth effect. This causes some of the cobalt silicide to agglomerate during the second annealing (820-850℃), resulting in fuse failure and severely affecting the performance and yield of the electric fuse structure.
[0034] To this end, the application provides a semiconductor structure for a BCD process and a manufacturing method thereof, the manufacturing method comprising providing a substrate, forming a patterned mask layer on a surface of the substrate, openings of the patterned mask layer exposing N-type doped regions on the surface of the substrate; performing P-type ion implantation to form a plurality of P-type heavily doped regions on the N-type doped regions to form an MPS diode in the substrate; removing the patterned photoresist layer and an oxide layer on the surface of the substrate; performing a decoupled plasma nitridation process to form a nitride layer on the surface of the substrate; and forming a metal silicide layer on the surface of the substrate and taking the metal silicide as a fuse on the MPS diode. In the application, the nitride layer formed by the decoupled plasma nitridation process is arranged on the surface of the MPS diode, which can increase the diffusion barrier height of Si into CoSi in the reaction process of Co and Si, cause the temperature to increase in the formation of low-resistance and agglomeration, and equivalently increase the phase transition temperature from high-resistance silicide to low-resistance silicide, thereby avoiding or reducing the agglomeration of the metal silicide as the fuse in the annealing process, and improving the performance and yield of the electrical fuse structure. In addition, the application can perform P-type ion implantation to form a plurality of P-type heavily doped regions on the N-type doped regions, and can not immediately perform the annealing process, but combine the annealing process for activating the P-type heavily doped regions with the subsequent annealing process for forming the metal silicide, so as to save one annealing process and save costs.
[0035] To make the objectives, advantages and features of the present application more apparent, the following further describes the present application in detail with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are very simplified and not drawn to scale, and are only used to facilitate and clarify the purpose of describing the embodiments of the present application. In addition, the structures shown in the drawings are often part of the actual structures. In particular, different scales are sometimes used in the drawings to show different focuses.
[0036] As used in the present application, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally used in the sense of "and / or", the term "several" is generally used in the sense of "at least one", the term "at least two" is generally used in the sense of "two or more", and in addition, the terms "first", "second", "third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second", "third" can explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.
[0037] The embodiments of the present application provide a manufacturing method of a semiconductor structure for a BCD process.
[0038] Figure 2A flowchart of a method for manufacturing a semiconductor structure for a BCD process is provided in the present embodiment.
[0039] As shown in Figure 2 , the method for manufacturing a semiconductor structure for a BCD process provided in the present embodiment comprises:
[0040] S01: providing a substrate, forming a patterned mask layer on the surface of the substrate, the opening of the patterned mask layer exposing an N-type doped region on the surface of the substrate;
[0041] S02: performing P-type ion implantation to form several P-type heavily doped regions on the N-type doped region to form an MPS diode in the substrate;
[0042] S03: removing the patterned photoresist layer and the oxide layer on the surface of the substrate;
[0043] S04: performing a decoupling plasma nitridation process to form a nitride layer on the surface of the substrate;
[0044] S05: forming a metal silicide layer on the surface of the substrate, and using the metal silicide as a fuse on the MPS diode.
[0045] Figures 3A-3G The structure schematic diagram corresponding to the corresponding steps of the method for manufacturing a semiconductor structure for a BCD process provided in the present embodiment is shown in the following. Figures 3A-3G The method for manufacturing a semiconductor structure for a BCD process provided in the present embodiment will be described in detail in the following.
[0046] Firstly, step S01 is performed, please refer to Figure 3A , a substrate 10 is provided, a patterned mask layer 21 is formed on the surface of the substrate 10, and the opening of the patterned mask layer 21 exposes an N-type doped region 12 on the surface of the substrate 10.
[0047] The substrate 10 can be at least one of silicon, germanium, silicon germanium, silicon on insulator, silicon germanium on insulator, germanium on insulator, etc. The substrate 10 of the present application is used in a BCD process, which can include multiple different functional and voltage regions, and the region for forming the MPS diode (i.e. the MPS diode region) of the present application can be located in a high voltage region (e.g. in the same region as DMOS devices), which can be defined by a front trench isolation structure, for example, and can include an NBL layer 11 (N-type buried layer) and an N-type doped region 12 (as a drift region) arranged in sequence. In some examples, the N-type doped region 12 described above can further include a first N-type doped region 12a and a second N-type doped region 12b formed in sequence, the first N-type doped region 12a can be in-situ phosphorus doping, which is located above the NBL layer 11, and the second N-type doped region 12b has a thickness greater than that of the first N-type doped region 12a, and a shallow trench isolation structure 13 is arranged in the second N-type doped region 12b.
[0048] The patterned mask layer 21 covers the surface of the substrate 10 and exposes part of the surface of the substrate 10 in the region for the MPS diode, in other words, the patterned mask layer 21 is provided with a plurality of spaced openings in the region for the MPS diode to expose the corresponding part of the surface of the substrate 10, wherein the region exposed by the patterned mask layer 21 in the region for the MPS diode is used for subsequent formation of an ohmic contact, and the region covered by the patterned mask layer 21 in the region for the MPS diode is used for subsequent formation of a Schottky contact. It can be understood that the surface of the substrate 10 is covered with the oxide layer 14 formed by the previous oxidation process.
[0049] Next, referring to Figure 3B , step S02 is performed, P-type ion implantation is performed to form a plurality of P-type heavily doped regions 22 in the N-type doped region 12 to form the MPS diode in the substrate 10.
[0050] After the P-type ion implantation is performed in the N-type doped region 12 using the patterned mask layer 21 to form a plurality of P-type heavily doped regions 22, an annealing process can not be performed immediately, but the annealing process for activating the P-type heavily doped regions 22 can be combined with a subsequent annealing process for forming a metal silicide to save one annealing process and thus save costs. Therefore, the surface of the formed MPS diode includes alternating P-type heavily doped regions 22 and N-type doped regions 12.
[0051] It should be noted that in the present application, the process steps for forming the MPS diode can be independent of the steps for forming other structures on the surface of the substrate 10, for example, after forming P-type heavily doped regions and metal silicides in other regions, the steps for forming the MPS diode and metal silicide (fuse) of the present application are performed.
[0052] Next, referring toFigure 3C After step S03, the patterned photoresist layer and the oxide layer 14 on the surface of the substrate 10 are removed.
[0053] In some examples, a wet process (including diluted hydrofluoric acid) can be used to sequentially remove the patterned photoresist layer and the oxide layer 14 on the surface of the substrate 10 to expose the silicon on the surface of the substrate 10. In another example, a dry etching process can be used to remove the patterned photoresist layer to expose the oxide layer 14 on the surface of the substrate 10, and then a wet process (such as diluted hydrofluoric acid) can be used to remove the oxide layer 14 on the surface of the substrate 10 to expose the silicon on the surface of the substrate 10.
[0054] Next, please refer to Figure 3D After step S04, a decoupled plasma nitridation process is performed to form a nitride layer 23 on the surface of the substrate 10.
[0055] In some examples, the decoupled plasma nitridation process has a power of 1000W-2250W and a processing time of 10s-120s to perform nitriding treatment on the surface of the MPS diode, i.e., to form a nitride layer 23 on the surface of the MPS diode (the P-type heavily doped region 22 and the N-type doped region 12 on the surface). It can be understood that, compared with the method of implanting nitrogen ions on the surface of the MPS diode, the decoupled plasma nitridation process of the present application can avoid damage during ion implantation, reduce interface defects, and have advantages of reducing Schottky contact (Schottky diode) leakage, etc.
[0056] Next, step S05 is performed to form a metal silicide layer 26 on the surface of the substrate 10, and the metal silicide is used as a fuse on the MPS diode.
[0057] Please refer to Figure 3E The metal layer 24 and the barrier layer 25 are sequentially formed to conformally cover the surface of the substrate 10. The metal layer 24 is used to react with silicon in the substrate 10 to form a metal silicide, which can include one or any of cobalt, nickel, or titanium, and the barrier layer 25 is used to protect the metal layer 24 or the metal silicide during annealing, which can have a material matching that of the metal layer 24 or the metal silicide. In some examples of the present application, the metal layer 24 can include metallic cobalt, and the barrier layer 25 can include titanium nitride. The metal layer 24 and the barrier layer 25 can be sequentially formed by a PVD process. The thickness of the metallic cobalt can be 30-300 angstroms, and the thickness of the titanium nitride can be 10-100 angstroms.
[0058] Please refer to Figure 3FThe first anneal is performed to react a portion of the metal layer 24 with silicon in the substrate 10 to form a first silicide, and a wet process is performed to remove the barrier layer 25 and unreacted metal layer 24. The first anneal is used to react a portion of the metal layer 24 with silicon in the substrate 10 to form a first silicide to fix the portion of the metal layer 24 near the surface of the substrate 10. In some examples, the metal layer 24 can include cobalt, the first anneal can be a rapid thermal anneal process, the anneal time can be 10 seconds to 60 seconds, the anneal temperature can be 400 degrees Celsius to 600 degrees Celsius, and the first silicide can be high resistance cobalt silicide, i.e., CoSi. When performing the wet process, a solution including SPM (a mixed solution including dilute sulfuric acid and hydrogen peroxide) can be used to remove the barrier layer 25 and unreacted metal layer 24, and a DHF (dilute hydrofluoric acid) solution can be used to remove surface oxides, and DI water can be used for rinsing.
[0059] Please refer to Figure 3G A second anneal is performed to react a portion of the first silicide with the nitride layer 23 to form a second silicide, and to leave a portion of the first silicide, and the first silicide and the second silicide are used as the metal silicide layer 26, and the second anneal has a temperature greater than the first anneal. In this application, the metal layer 24 can include cobalt, and the nitride layer 23 formed by the decoupled plasma nitridation process is disposed on the surface of the MPS diode, which can increase the diffusion barrier height of Si into CoSi during the reaction of Co and Si, so as to increase the temperature for forming low resistance and agglomeration (e.g., similar to increasing the phase transition temperature of the first silicide to the second silicide by 50 degrees Celsius to 100 degrees Celsius), in other words, even if the anneal temperature of the second anneal is increased, only a portion of the first silicide is converted to the second silicide, and the remaining portion is still retained as the first silicide, and the high resistance first silicide and the low resistance second silicide are used as the fuse of the MPS diode, and are used to form an electrical fuse structure, so as to avoid or reduce the agglomeration of the metal silicide (fuse) during the anneal process, so as to improve the performance and yield of the electrical fuse structure. In addition, compared with the anneal temperature of the second anneal in the related art (the anneal temperature is not enough to completely activate the P-type heavily doped region 22), the anneal temperature of the second anneal in this application can be slightly increased, and the P-type heavily doped region 22 is also activated by the second anneal.
[0060] In some examples, the metal layer 24 includes cobalt, the second anneal includes a rapid thermal anneal process, the anneal temperature of the second anneal is 850 degrees Celsius to 950 degrees Celsius, and the anneal time is 5 seconds to 120 seconds. In other examples, the metal layer 24 includes cobalt, the second anneal includes a laser anneal process, the anneal temperature of the second anneal process is 1000 degrees Celsius to 1200 degrees Celsius, and the anneal time is 200 microseconds to 1000 microseconds.
[0061] Embodiments of the present application also provide a semiconductor structure for a BCD process.
[0062] Figure 3G A schematic diagram of a semiconductor structure for BCD process is provided in embodiments of the present application.
[0063] As shown in Figure 3G , the semiconductor structure for BCD process provided in embodiments of the present application includes a substrate 10, an MPS diode, a nitride layer 23 and a metal silicide layer 26. The MPS diode is disposed in the substrate 10, and the MPS diode includes an N-type doped region 12 and a plurality of P-type heavily doped regions 22 disposed in the N-type doped region 12. The metal silicide layer 26 is disposed on the N-type doped region 12 and the P-type heavily doped regions 22, and serves as a fuse disposed on the MPS diode. The nitride layer 23 is disposed between the MPS diode and the metal silicide layer 26.
[0064] Please continue to refer to Figure 3G , the substrate 10 is used for BCD process, which can include a plurality of different functional and voltage regions, and the MPS diode (i.e. the region where the MPS diode is located) of the present application can be located in a high-voltage region (for example, in the same region as the DMOS device), which can be defined by a front trench isolation structure, for example. The MPS diode can include an NBL layer 11, an N-type doped region 12 and a plurality of P-type heavily doped regions 22, the NBL layer 11 and the N-type doped region 12 are sequentially disposed in the substrate 10, and the N-type doped region 12 can further include a first N-type doped region 12a and a second N-type doped region 12b sequentially formed, the first N-type doped region 12a can be in-situ phosphorus doping, which is located above the NBL layer 11, and the thickness of the second N-type doped region 12b is greater than that of the first N-type doped region 12a, and a plurality of P-type heavily doped regions 22 are spaced apart in the second N-type doped region 12b. The nitride layer 23 is disposed in the surface of the substrate 10 of the MPS diode, i.e. disposed on the surface of the P-type heavily doped regions 22 and the N-type doped region 12, and the metal silicide layer 26 covers the surface of the substrate 10 of the MPS diode, i.e. the nitride layer 23 is located at the bottom of the metal silicide layer 26 connected to the surface of the substrate 10. The metal silicide layer 26, as a fuse connected to the MPS diode, can include a high-resistance first silicide and a low-resistance second silicide.
[0065] In summary, the present application provides a semiconductor structure for BCD process and a manufacturing method thereof. The manufacturing method comprises providing a substrate, forming a patterned mask layer on the surface of the substrate, the opening of the patterned mask layer exposes the N-type doped region on the surface of the substrate; performing P-type ion implantation to form several P-type heavily doped regions on the N-type doped region to form an MPS diode in the substrate; removing the patterned photoresist layer and the oxide layer on the surface of the substrate; performing decoupled plasma nitridation process to form a nitride layer on the surface of the substrate; forming a metal silicide layer on the surface of the substrate, and using the metal silicide as a fuse on the MPS diode. In the present application, the nitride layer formed by the decoupled plasma nitridation process is arranged on the surface of the MPS diode, which can increase the diffusion barrier height of Si into CoSi during the reaction of Co and Si, so as to increase the temperature for forming low resistance and agglomeration, which is equivalent to increasing the phase transition temperature from high resistance silicide to low resistance silicide, thereby avoiding or reducing the agglomeration of the metal silicide as a fuse during the annealing process, and improving the performance and yield of the electrical fuse structure. In addition, the present application can perform P-type ion implantation to form multiple P-type heavily doped regions on the N-type doped region, and can not immediately perform the annealing process, but combine the annealing process for activating the P-type heavily doped region with the subsequent annealing process for forming the metal silicide, so as to save one annealing process, thereby saving the cost.
[0066] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any modification or change made by a person skilled in the art according to the above disclosure is within the protection scope of the claims.
Claims
1. A method of fabricating a semiconductor structure for a BCD process, characterized by, The method comprises: providing a substrate, forming a patterned mask layer on a surface of the substrate, openings of the patterned mask layer exposing N-type doped regions on the surface of the substrate; performing P-type ion implantation to form a plurality of P-type heavily doped regions in the N-type doped regions to form an MPS diode in the substrate; removing the patterned photoresist layer and an oxide layer on the surface of the substrate; performing a decoupled plasma nitridation process to form a nitride layer on the surface of the substrate; forming a metal silicide layer on the surface of the substrate, and using the metal silicide as a fuse on the MPS diode.
2. The production method according to claim 1, characterized by The step of forming the metal silicide layer further comprises: forming a metal layer and a barrier layer sequentially to conformally cover the surface of the substrate; performing a first annealing to react part of the metal layer with silicon in the substrate to form a first silicide; performing a wet process to remove the barrier layer and unreacted metal layer; performing a second annealing to react part of the first silicide with the nitride layer to form a second silicide, and to reserve part of the first silicide, using the first silicide and the second silicide as the metal silicide layer, the second annealing having a temperature greater than that of the first annealing.
3. The production method according to claim 2, characterized by The metal barrier layer comprises a titanium nitride layer.
4. The production method according to claim 2, characterized by The metal layer comprises one or more of cobalt, nickel or titanium.
5. The production method according to claim 2, wherein The P-type heavily doped regions are also activated by the second annealing.
6. The production method according to claim 2, wherein The metal layer comprises cobalt, the second annealing comprises a rapid thermal annealing process, the annealing temperature of the second annealing is 850-950℃, and the annealing time is 5-120 seconds.
7. The production method according to claim 2, wherein The metal layer comprises cobalt, the second annealing comprises a laser annealing process, the annealing temperature of the second annealing process is 1000-1200℃, and the annealing time is 200 microseconds-1000 microseconds.
8. The production method according to claim 1, wherein The decoupled plasma nitridation process has a power of 1000-2250W and a processing time of 10-120 seconds.
9. A semiconductor structure for a BCD process, characterized by The method comprises: a substrate; an MPS diode provided in the substrate, the MPS diode comprising N-type doped regions and a plurality of P-type heavily doped regions provided in the N-type doped regions a metal silicide layer provided on the N-type doped regions and the P-type heavily doped regions and used as a fuse provided on the MPS diode; a nitride layer provided between the MPS diode and the metal silicide layer.
10. The semiconductor structure of claim 9, wherein, The metal silicide layer comprises a first silicide with high resistance and a second silicide with low resistance.