Bipolar power amplifier and preparation method thereof

Abstract

The invention relates to a power amplifier, in particular to a bipolar power amplifier and a preparation method thereof. Comprising a P-type substrate, and a plurality of N + type buried layers are arranged on the upper surface of the P-type substrate; the upper surface of the P-type substrate is provided with a plurality of first P + expansion regions and an N-type epitaxial layer located on the surface of the P-type substrate and the upper surface of the N + type buried layer; a second P + expansion region and a first N + expansion region are arranged on the upper surface of the N-type epitaxial layer; a second N + expansion region is arranged on the upper surface of the second P + expansion region; silicon dioxide layers are arranged on the upper surfaces of the first P + expansion region, the second P + expansion region, the N-type epitaxial layer, the first N + expansion region and the second N + expansion region; a plurality of wiring terminals are arranged on the surface of the silicon dioxide layer, and the lower end faces of the wiring terminals penetrate through the silicon dioxide layer and are connected with the second P + expansion area, the second N + expansion area and the first N + expansion area respectively. The high-frequency efficiency of the power amplifier can be improved from 65% to 80%, and the output power is increased by 30%.

Description

TECHNICAL FIELD

[0001] The present application relates to a power amplifier, in particular to a bipolar power amplifier and a preparation method thereof. BACKGROUND

[0002] As a core device of radio frequency and microwave systems, power amplifiers are widely used in communication, radar, satellite navigation and other fields, and their performance directly affects the output power, efficiency and signal quality of the system. Bipolar power amplifiers have been long concerned by the industry due to their advantages of excellent high-frequency characteristics, mature process and controllable cost.

[0003] However, as high-frequency communication systems evolve towards higher bandwidth, greater power density and better thermal stability, traditional bipolar process power amplifiers face the following key bottlenecks in performance: high-frequency efficiency and output power are limited due to process parameter fluctuations. SUMMARY

[0004] The purpose of the present application is to solve the technical problem of the existing power amplifier that the high-frequency efficiency and output power are limited due to process parameter fluctuations, and to provide a bipolar power amplifier and a preparation method thereof.

[0005] To solve the above technical problems, the technical solutions provided by the present application are as follows:

[0006] A bipolar power amplifier comprises a P-type substrate, and a plurality of N+ buried layers are arranged on the upper surface of the P-type substrate.

[0007] The upper surface of the P-type substrate is provided with a plurality of first P+ extension regions, and an N-type epitaxial layer is arranged on the surface of the P-type substrate and the upper surface of the N+ buried layer.

[0008] The upper surface of the N-type epitaxial layer is provided with a second P+ extension region and a first N+ extension region; a second N+ extension region is arranged on the upper surface of the second P+ extension region.

[0009] The upper surfaces of the first P+ extension region, the second P+ extension region, the N-type epitaxial layer, the first N+ extension region and the second N+ extension region are provided with a silicon dioxide layer.

[0010] The surface of the silicon dioxide layer is provided with a plurality of terminal ends, and the lower end surfaces of the plurality of terminal ends penetrate the silicon dioxide layer and are respectively connected with the second P+ extension region, the second N+ extension region and the first N+ extension region.

[0011] Further, the thickness of the N-type epitaxial layer is 8.8-9.2 μm, and the resistance block value is 2500-3000 Ω / □.

[0012] Further, an isolation wall is arranged on the upper surface of the N-type epitaxial layer, and the spacing between the isolation wall and the N+ buried layer is 26 μm.

[0013] Further, the thickness of the N+ type buried layer is 4 μm, and the resistance Rc is less than 0.5 Ω.

[0014] A preparation method of a bipolar power amplifier, comprising the following steps:

[0015] S1, cutting a P type substrate with a corresponding size according to the size of the power amplifier, and cleaning and polishing the outer surface of the P type substrate;

[0016] S2, photoetching a buried layer pattern on the upper surface of the P type substrate, and diffusing impurities into the buried layer pattern to form an N+ type buried layer;

[0017] S3, growing an N- type epitaxial layer with a thickness of 8.8-9.2 μm and a resistance block value of 2500-3000 Ω / □ on the upper surface of the P type substrate and the N+ type buried layer;

[0018] Simultaneously diffusing impurities between the upper surface of the P type substrate and the N- type epitaxial layer to form a first P+ extension region;

[0019] S4, photoetching an isolation pattern on the upper surface of the N- type epitaxial layer, and diffusing impurities into the isolation pattern to form an isolation wall;

[0020] S5, diffusing impurities on the upper surface of the N- type epitaxial layer to form a second P+ extension region and a first N+ extension region respectively, and diffusing impurities on the upper surface of the second P+ extension region to form a second N+ extension region;

[0021] S6, coating a silicon dioxide layer on the upper surfaces of the first P+ extension region, the second P+ extension region, the N- type epitaxial layer, the first N+ extension region and the second N+ extension region, and etching lead holes connected with the second P+ extension region, the first N+ extension region and the second N+ extension region respectively on the silicon dioxide layer;

[0022] S7, evaporating an aluminum layer on the upper surface of the silicon dioxide layer and in the lead holes, and removing the excess aluminum layer by photoetching and etching;

[0023] Heating at a temperature of 480 ℃ for 20 minutes under a nitrogen atmosphere to complete the aluminum-silicon alloying of the aluminum layer and the P type substrate, and to complete the preparation of the bipolar power amplifier.

[0024] Further, the specific method for diffusing impurities into the buried layer pattern on the P type substrate to form the N+ type buried layer in step S2 is as follows:

[0025] Deep phosphorus implantation process is used to implant phosphorus elements into the buried layer pattern on the P type substrate, wherein the implantation energy is 180 keV, and the implantation dose is 3e15 cm -2 ;

[0026] When the diffusion depth of phosphorus element on the surface of the P-type substrate reaches 4um, the P-type substrate is annealed in a nitrogen atmosphere for 30 minutes, and the annealing temperature is 1000 DEG C.

[0027] After the annealing is completed, the N+ type buried layer with the resistance Rc < 0.5 omega is formed on the upper surface of the P-type substrate.

[0028] Further, the specific method for diffusing impurities on the upper surface of the N-type epitaxial layer to form the second P+ extension region in step S5 is as follows:

[0029] The second P+ extension region pattern is photoetched on the upper surface of the N-type epitaxial layer, and impurities are pre-diffused into the second P+ extension region pattern at a diffusion temperature of 940 DEG C, so as to form the second P+ extension region with the resistance block value of 54-58 omega / square.

[0030] Then, impurities are re-diffused into the second P+ extension region pattern again at a diffusion temperature of 1118-1122 DEG C, and the diffusion time is 70 minutes, and the phosphine gas concentration is 600ppm, so as to form the second P+ extension region with the resistance block value of 190-210 omega / square.

[0031] Further, the specific method for diffusing impurities on the upper surface of the second P+ extension region to form the second N+ extension region in step S5 is as follows:

[0032] The second N+ extension region pattern is photoetched on the upper surface of the second P+ extension region, and impurities are diffused into the second N+ extension region pattern at a diffusion temperature of 1080 DEG C, and the diffusion time is 15 minutes, and the diffusion depth is 0.6um.

[0033] The doping concentration is 5e20 cm-3, and the doping concentration ratio beta is 90-110. -3

[0034] Compared with the prior art, the beneficial effects of the present application are as follows:

[0035] 1. The bipolar power amplifier and the preparation method thereof provided by the present application, the N+ type buried layer (Rc < 0.5 omega, junction depth 4um) is formed by the deep phosphorus implantation process, which forms a low-resistance buried layer, helps to increase the output power by 30% and improve the high-frequency efficiency from 65% to 80%; the distance from the N+ type buried layer to the isolation wall is increased from 20um to 26um, which can reduce the parasitic capacitance by about 30%, reduce the leakage current from 2.36uA to 0.5uA, expand the high-frequency bandwidth from 4GHz to 6GHz, reduce the signal delay by 20%, and significantly improve the high-frequency response speed.

[0036] ​2. The bipolar power amplifier and the preparation method thereof provided by the application can reduce local electric field concentration and heat accumulation, improve breakdown voltage, reduce thermal stress, enhance the working stability of the power amplifier under high-temperature and high-pressure environment, reduce parameter drift rate, and prolong service life.

[0037] 3. The bipolar power amplifier and the preparation method thereof provided by the application adopt a two-step diffusion process, i.e. pre-diffusion + re-diffusion, the resistance block value of the second P+ extension region is optimized from the existing 210-230Ω / □ to 190-210Ω / □, the process fluctuation range is reduced by 20%; the static current is reduced by about 7% (from 8.26mA to 7.71mA), the peak current fluctuation range is reduced from 286-314mA to 180-285mA, and the yield is improved by 30%. The second N+ extension region doping concentration is improved to 5e20cm -3 , the beta value is optimized from 70-90 to 90-110, the discreteness is reduced by 40%; the current driving capability is enhanced, the amplification consistency is improved, the dependence on external compensation circuit is reduced, and the design complexity and cost are reduced. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 It is a circuit structure schematic diagram of an existing ER3020 type wideband power amplifier;

[0039] Figure 2 It is a test circuit diagram of an existing ER3020 type wideband power amplifier;

[0040] Figure 3 It is a test schematic diagram of an existing ER3020 type wideband power amplifier;

[0041] Figure 4 It is a structure schematic diagram of the embodiment of the application.

[0042] The reference signs are explained as follows: 1-P type substrate, 2-N+ type buried layer, 3-first P+ extension region, 4-N- type epitaxial layer, 5-second P+ extension region, 6-first N+ extension region, 7-second N+ extension region, 8-silicon dioxide layer, and 9-terminal. DETAILED DESCRIPTION

[0043] The technical solutions in the application will be described in detail below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments. Based on the embodiments of the application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the application.

[0044] This embodiment takes an ER3020 type wideband power amplifier adopting a bipolar process as an example for detailed description. Figure 1The diagram shows the circuit structure of the ER3020 broadband power amplifier. The ER3020 broadband power amplifier uses a standard 3μm to 5μm bipolar process and has three stages: a differential input stage, an intermediate gain stage, and a push-pull output stage. It contains a total of 10 NPN transistors and 15 base diffusion resistors.

[0045] Table 1 shows the core steps of the manufacturing process for the ER3020 broadband power amplifier using bipolar technology and the key parameters affecting these steps.

[0046] Table 1: Core Steps and Key Parameters Affecting These Steps

[0047]

[0048] The influencing factors of key current parameters of the ER3020 broadband power amplifier are shown in Table 2.

[0049] Table 2: Current Parameters and Influencing Factors of ER3020 Broadband Power Amplifier

[0050]

[0051]

[0052] As shown in Table 2: I cc The total current consumption is only affected by the base resistance block value. The larger the base resistance block value, the more significant the total current consumption may be, reflecting the direct effect of the base resistance on the overall power consumption.

[0053] I PEAK (Peak output current), I IDLE (static current), I off (cutoff current), I ceo (Emitter-collector cutoff current): Both are affected by the sheet value of the base resistance and the β value. The sheet value of the base resistance affects the magnitude of the base resistance, while the β value reflects the current gain capability. The two work together to affect the current characteristics of the device. For example, increasing the sheet value of the base resistance may limit the current, while increasing the β value will enhance the current drive capability. Together, they determine the peak, quiescent, and cutoff current parameters.

[0054] To verify the relationship between the current parameters and influencing factors of the ER3020 broadband power amplifier, a simulation test circuit for the ER3020 broadband power amplifier was constructed. The simulation test circuit is as follows: Figure 2 and Figure 3 As shown, by inputting different combinations of β values ​​and base region resistance block values, I... PEAK and I IDLE Simulation tests were conducted, and the specific results are shown in Table 3.

[0055] Table 3: I under different combinations of β value and base region resistance block value PEAK and I IDLE Simulation test results

[0056]

[0057] Analysis of the simulation data in Table 4 shows that:

[0058] (1) Base region resistance block value and I PEAK I IDLE Negative correlation, and with a relatively small impact;

[0059] (2) Base region resistance block value and I cc Negative correlation can be achieved by adjusting the base region resistance, which can be used to adjust I. cc ;

[0060] (3) β value and I PEAK I IDLE A positive correlation exists, and the β value has a significant impact on its magnitude. The I value can be adjusted by changing the β value. PEAK I IDLE Value. If β increases, then I... PEAK I IDLE Increase, conversely, I PEAK I IDLE Decrease.

[0061] The structure of the existing ER3020 broadband power amplifier was examined, and the potential problems caused by the structure of the ER3020 broadband power amplifier were summarized in Table 4.

[0062] Table 4: Test Items and Potential Problems for ER3020 Broadband Power Amplifier

[0063]

[0064] As shown in Table 4, a distance of 20μm between the N+ type buried layer and the isolation wall leads to problems such as increased parasitic capacitance, increased leakage current, decreased breakdown voltage, deteriorated thermal stability, increased process difficulty and defect rate, and enhanced noise interference. The ER3020 broadband power amplifier does not use deep phosphorus process, resulting in high collector series resistance, limited output power, large-signal nonlinear distortion, deterioration of high-frequency response performance, increased thermal stability and reliability risks, and collector resistance is more sensitive to metallization process fluctuations, resulting in a decrease in yield.

[0065] Based on the above analysis, the manufacturing process of the existing ER3020 broadband power amplifier will be optimized and adjusted as follows:

[0066] like Figure 4As shown, a bipolar power amplifier includes a P-type substrate 1, and a plurality of N+ type buried layers 2 are provided on the upper surface of the P-type substrate 1; the thickness of the N+ type buried layer 2 is 4μm and the resistance Rc < 0.5Ω.

[0067] The upper surface of the P-type substrate 1 is provided with a plurality of first P+ expansion regions 3, and an N-type epitaxial layer 4 located on the surface of the P-type substrate 1 and the upper surface of the N+ type buried layer 2; the thickness of the N-type epitaxial layer 4 is 8.8-9.2μm and the sheet resistance value is 2500-3000Ω / □; an isolation wall is provided on the upper surface of the N-type epitaxial layer 4, and the distance between the isolation wall and the N+ type buried layer 2 is 26μm.

[0068] The upper surface of the N-type epitaxial layer 4 is provided with a second P+ expansion region 5 and a first N+ expansion region 6; the upper surface of the second P+ expansion region 5 is provided with a second N+ expansion region 7.

[0069] A silicon dioxide layer 8 is provided on the upper surface of the first P+ expansion region 3, the second P+ expansion region 5, the N-type epitaxial layer 4, the first N+ expansion region 6, and the second N+ expansion region 7.

[0070] The surface of the silicon dioxide layer 8 is provided with a plurality of terminals 9. The lower end face of the plurality of terminals 9 penetrates the silicon dioxide layer 8 and is connected to the second P+ expansion region 5, the second N+ expansion region 7, and the first N+ expansion region 6 respectively.

[0071] The specific fabrication method of the above-mentioned bipolar power amplifier is as follows:

[0072] S1. Cut a P-type substrate 1 of the appropriate size according to the size of the power amplifier, and clean and polish the outer surface of the P-type substrate 1.

[0073] S2. A buried layer pattern is photolithographically patterned on the upper surface of the P-type substrate 1. Phosphorus is implanted into the buried layer pattern on the P-type substrate 1 using a deep phosphorus implantation process, wherein the implantation energy is 180 keV and the implantation dose is 3e15cm. -2 ;

[0074] When the diffusion depth of phosphorus on the surface of P-type substrate 1 reaches 4 μm, P-type substrate 1 is annealed for 30 min in a nitrogen atmosphere at a temperature of 1000℃.

[0075] After annealing, an N+ buried layer 2 with a resistance Rc < 0.5Ω is formed on the upper surface of the P-type substrate 1;

[0076] S3. An N-type epitaxial layer 4 with a thickness of 8.8-9.2 μm and a sheet resistance of 2500-3000 Ω / □ is grown on the upper surface of the P-type substrate 1 and the N+ type buried layer 2.

[0077] Simultaneously, impurities are diffused between the upper surface of the P-type substrate 1 and the N-type epitaxial layer 4 to form the first P+ expansion region 3;

[0078] S4. Photolithographically etch an isolation pattern on the upper surface of the N-type epitaxial layer 4 and diffuse impurities into the isolation pattern to form an isolation wall with a spacing of 26μm between it and the N+ type buried layer 2.

[0079] S5. Diffusion of impurities on the upper surface of the N-type epitaxial layer 4 to form a second P+ expansion region 5 and a first N+ expansion region 6, respectively; diffusion of impurities on the upper surface of the second P+ expansion region 5 to form a second N+ expansion region 7.

[0080] The specific method for diffusing impurities on the upper surface of the N-type epitaxial layer 4 to form the second P+ expansion region 5 is as follows:

[0081] A second P+ expansion region 5 pattern is photolithographically etched on the upper surface of the N-type epitaxial layer 4, and impurities are pre-diffused into the second P+ expansion region 5 pattern at a diffusion temperature of 940℃ to form a second P+ expansion region 5 with a sheet resistance value of 54-58Ω / □.

[0082] Then, impurities are diffused again into the second P+ expansion region 5 pattern at a diffusion temperature of 1118-1122℃ for 70 minutes, with a phosphine gas concentration of 600ppm; thus forming the second P+ expansion region 5 with a sheet resistance of 190-210Ω / □.

[0083] The specific method for diffusing impurities on the upper surface of the second P+ expansion region 5 to form the second N+ expansion region 7 is as follows:

[0084] A pattern of a second N+ expansion region 7 was photolithographically formed on the upper surface of the second P+ expansion region 5, and impurities were diffused into the pattern of the second N+ expansion region 7 at a diffusion temperature of 1080℃ for 15 min and a diffusion depth of 0.6 μm.

[0085] The doping concentration is 5e20cm. -3 The doping concentration ratio β is 90-110.

[0086] S6. Coat the upper surfaces of the first P+ expansion region 3, the second P+ expansion region 5, the N-type epitaxial layer 4, the first N+ expansion region 6, and the second N+ expansion region 7 with a silicon dioxide layer 8; and etch lead holes on the silicon dioxide layer 8 that are connected to the second P+ expansion region 5, the first N+ expansion region 6, and the second N+ expansion region 7 respectively.

[0087] S7. An aluminum layer is deposited on the upper surface of the silicon dioxide layer 8 and inside the lead hole, and the excess aluminum layer is removed by photolithography and etching.

[0088] Under a nitrogen atmosphere, the aluminum layer and the P-type substrate 1 were heated at 480℃ for 20 minutes to complete the aluminum-silicon alloying, thereby realizing the fabrication of a bipolar power amplifier.

[0089] In the bipolar power amplifier of this embodiment, the second P+ expansion region 5 is the base region of the bipolar power amplifier, the first N+ expansion region 6 is the collector region of the bipolar power amplifier, and the second N+ expansion region 7 is the emitter region of the bipolar power amplifier.

[0090] In this embodiment, the sheet resistance value of the base region is adjusted and optimized from the existing 210-230Ω / □ to 190-210Ω / □, reducing process fluctuations in the base region resistance and stabilizing the quiescent current (I). IDLE ) and peak current (I PEAK ).

[0091] Increase the emitter doping concentration to 5e20cm -3 The β value was adjusted and optimized from 70-90 to 90-110; the current drive capability was enhanced, and batch-to-batch differences were reduced, which can improve the consistency of the amplification factor by 40% and the quiescent current (I IDLE The current decreased from 8.26 mA to 7.71 mA.

[0092] By introducing a deep phosphorus implantation process, an N+ type buried layer 2 is formed. The resistance Rc of the N+ type buried layer 2 is less than 0.5Ω, which can improve the high-frequency output efficiency from 65% to 80% and extend the bandwidth to 6GHz.

[0093] Increasing the distance between the N+ type buried layer 2 and the isolation wall from 20μm to 26μm helps reduce parasitic capacitance and leakage current, and reduces high-frequency signal delay by 20%.

[0094] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present invention should be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A bipolar power amplifier, characterized in that, It includes a P-type substrate (1), and the upper surface of the P-type substrate (1) is provided with multiple N+ type buried layers (2); The upper surface of the P-type substrate (1) is provided with a plurality of first P+ expansion regions (3), and an N-type epitaxial layer (4) located on the surface of the P-type substrate (1) and the upper surface of the N+ type buried layer (2); The upper surface of the N-type epitaxial layer (4) is provided with a second P+ expansion region (5) and a first N+ expansion region (6); the upper surface of the second P+ expansion region (5) is provided with a second N+ expansion region (7); A silicon dioxide layer (8) is provided on the upper surface of the first P+ expansion region (3), the second P+ expansion region (5), the N-type epitaxial layer (4), the first N+ expansion region (6) and the second N+ expansion region (7); The surface of the silicon dioxide layer (8) is provided with a plurality of terminals (9), the lower end face of the plurality of terminals (9) penetrates the silicon dioxide layer (8) and is connected to the second P+ expansion region (5), the second N+ expansion region (7) and the first N+ expansion region (6) respectively.

2. The bipolar power amplifier according to claim 1, characterized in that, The thickness of the N-type epitaxial layer (4) is 8.8-9.2 μm and the sheet resistance value is 2500-3000 Ω / □.

3. The bipolar power amplifier according to claim 1, characterized in that, An isolation wall is provided on the upper surface of the N-type epitaxial layer (4), and the distance between the isolation wall and the N+ type buried layer (2) is 26 μm.

4. The bipolar power amplifier according to claim 1, characterized in that, The thickness of the N+ type buried layer (2) is 4 μm, and the resistance Rc < 0.5 Ω.

5. A method for fabricating a bipolar power amplifier based on any one of claims 1-4, characterized in that, Includes the following steps: S1. Cut a P-type substrate (1) of the appropriate size according to the size of the power amplifier, and clean and polish the outer surface of the P-type substrate (1); S2. Photolithographically pattern a buried layer pattern on the upper surface of the P-type substrate (1) and diffuse impurities into the buried layer pattern to form an N+ type buried layer (2); S3. An N-type epitaxial layer (4) with a thickness of 8.8-9.2 μm and a sheet resistance of 2500-3000 Ω / □ is grown on the upper surface of the P-type substrate (1) and the N+ type buried layer (2); Simultaneously, impurities are diffused between the upper surface of the P-type substrate (1) and the N-type epitaxial layer (4) to form the first P+ expansion region (3); S4. Photolithographically etch an isolation pattern on the upper surface of the N-type epitaxial layer (4) and diffuse impurities into the isolation pattern to form an isolation wall with a spacing of 26 μm between it and the N+ type buried layer (2). S5. Diffusion of impurities on the upper surface of the N-type epitaxial layer (4) to form a second P+ expansion region (5) and a first N+ expansion region (6), respectively; diffusion of impurities on the upper surface of the second P+ expansion region (5) to form a second N+ expansion region (7); S6. A silicon dioxide layer (8) is coated on the upper surface of the first P+ expansion region (3), the second P+ expansion region (5), the N-type epitaxial layer (4), the first N+ expansion region (6), and the second N+ expansion region (7); and lead holes connected to the second P+ expansion region (5), the first N+ expansion region (6), and the second N+ expansion region (7) are etched on the silicon dioxide layer (8); S7. An aluminum layer is deposited on the upper surface of the silicon dioxide layer (8) and inside the lead hole, and the excess aluminum layer is removed by photolithography and etching. Under a nitrogen atmosphere, the aluminum layer and the P-type substrate (1) are heated at 480°C for 20 minutes to complete the aluminum-silicon alloying, thereby realizing the fabrication of a bipolar power amplifier.

6. The method for fabricating a bipolar power amplifier according to claim 5, characterized in that, In step S2, the specific method for diffusing impurities into the buried layer pattern on the P-type substrate (1) to form an N+ type buried layer (2) is as follows: Phosphorus was implanted into the buried layer pattern on a P-type substrate (1) using a deep phosphorus implantation process, wherein the implantation energy was 180 keV and the implantation dose was 3e15cm. -2 ; When the diffusion depth of phosphorus on the surface of the P-type substrate (1) reaches 4 μm, the P-type substrate (1) is annealed for 30 min in a nitrogen atmosphere at a temperature of 1000 °C. After annealing, an N+ buried layer (2) with a resistance Rc < 0.5Ω is formed on the upper surface of the P-type substrate (1).

7. The method for fabricating a bipolar power amplifier according to claim 5, characterized in that, In step S5, the specific method for diffusing impurities on the upper surface of the N-type epitaxial layer (4) to form the second P+ expansion region (5) is as follows: A second P+ expansion region (5) pattern is photolithographically etched on the upper surface of the N-type epitaxial layer (4), and impurities are pre-diffused into the second P+ expansion region (5) pattern at a diffusion temperature of 940℃ to form a second P+ expansion region (5) with a sheet resistance value of 54-58Ω / □. Then, impurities are diffused again into the second P+ expansion region (5) pattern at a diffusion temperature of 1118-1122℃ for 70 minutes, with a phosphine gas concentration of 600ppm; thus forming a second P+ expansion region (5) with a sheet resistance of 190-210Ω / □.

8. The method for fabricating a bipolar power amplifier according to claim 5, characterized in that, In step S5, the specific method for diffusing impurities on the upper surface of the second P+ expansion region (5) to form the second N+ expansion region (7) is as follows: A second N+ expansion region (7) pattern is photolithographically etched on the upper surface of the second P+ expansion region (5), and impurities are diffused into the second N+ expansion region (7) pattern at a diffusion temperature of 1080℃ for 15 min and a diffusion depth of 0.6 μm. The doping concentration is 5e20cm. -3 The doping concentration ratio β is 90-110.

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