Ring amplifier and analog-to-digital converter
By using cascaded inverters and short-circuit inverters in the ring amplifier to replace the resistive load and using low-threshold transistors, the stability and speed issues of the ring amplifier in high-speed scenarios are solved, achieving higher data processing speed and stability.
Patent Information
- Application Number
- CN202511042079.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-28
- Publication Date
- 2025-11-25
AI Technical Summary
Existing ring amplifiers are sensitive to changes in process technology, power supply voltage, and temperature in high-speed scenarios, which limits their speed and creates dead-zone voltage that affects data processing speed.
By using a cascaded inverter and a short-circuit inverter connection method to replace the traditional resistive load, and by utilizing low-threshold transistors and a head-to-tail connection design, dead-zone voltage is avoided, thereby improving stability and bandwidth.
It significantly improves the data processing speed and stability of the ring amplifier, reduces its sensitivity to changes in process technology, power supply voltage and temperature, and increases bandwidth and phase margin.
Smart Images
Figure CN121012450A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of analog-to-digital conversion technology, specifically to a ring amplifier and an analog-to-digital converter. Background Technology
[0002] Pipelined SAR ADCs (Analog-to-Digital Converters) are widely used in practical circuits due to their low power consumption, high speed, and low bit error rate. Their core principle is to achieve high-speed and high-precision analog-to-digital conversion through multiple cascaded pipeline structures and successive approximation register (SAR) technology. A high-performance amplifier is needed to amplify the quantization residual between each stage. Ring amplifiers, with their high speed, low power consumption, and simple circuitry, are very suitable as interstage amplifiers for pipelined SAR ADCs. While ring amplifiers can use resistors to generate a dead-time voltage at the gate of the output stage, this also creates a small second pole, which significantly affects the speed of the ring amplifier. Furthermore, ring amplifiers are very sensitive to changes in process technology, power supply voltage, and PVT (temperature), especially in high-speed applications.
[0003] In related technologies, a relatively large time margin is usually allowed or gain calibration techniques are added to address the speed and PVT sensitivity issues of ring amplifiers. However, this leads to a longer quantization cycle for analog-to-digital conversion and a lower sampling frequency for the ADC (Analog-to-Digital Converter). Therefore, high-performance interstage amplifiers have become one of the factors restricting the development of pipelined SAR ADCs. Summary of the Invention
[0004] In view of this, the present invention provides a ring amplifier and an analog-to-digital converter to solve or at least partially solve the above-mentioned technical problems.
[0005] In a first aspect, the present invention provides a ring amplifier, the ring amplifier comprising a cascaded inverter and two short-circuited inverters, each stage of the cascaded inverter comprising two single-stage inverters;
[0006] Both the short-circuit inverter and the single-stage inverter include two complementary MOS transistors;
[0007] The gates of the two MOS transistors of the short-circuit inverter and the drains of the two MOS transistors of the short-circuit inverter are shorted together.
[0008] The first-stage inverter in the cascaded inverter is connected to the control voltage and input voltage of the ring amplifier, wherein the control voltage is the output voltage of the common-mode feedback circuit of the ring amplifier;
[0009] The drain of the output stage inverter in the cascaded inverter serves as the differential output terminal of the ring amplifier.
[0010] The drains of the two MOS transistors in the short-circuit inverter are connected to the gates of the two MOS transistors in the output stage inverter, and the gates of the two MOS transistors in the short-circuit inverter are connected to the drains of the two MOS transistors in the preceding stage inverter of the output stage inverter.
[0011] The ring amplifier provided in this invention includes a cascaded inverter and two short-circuit inverters. By replacing the resistors in related technologies with short-circuit inverters, dead-zone voltage is effectively avoided. Connecting the short-circuit inverters between the output stage inverter and the preceding stage inverter stabilizes the gate voltage of the MOS transistor in the output stage inverter. Therefore, the ring amplifier can output a stable differential signal.
[0012] In some alternative implementations, the ring amplifier further includes a first MOS transistor; wherein the source of the first MOS transistor is connected to the power supply terminal, the gate is connected to the control voltage, and the drain is connected to the source of the NMOS transistor of the first stage inverter.
[0013] In some alternative implementations, the ring amplifier further includes a second MOS transistor; wherein the source of the second MOS transistor is grounded, the gate is connected to the control voltage, and the drain is connected to the source of the PMOS transistor of the first-stage inverter.
[0014] In some alternative implementations, the gates of the two MOS transistors of one of the single-stage inverters of the first-stage inverter are connected to the positive terminal of the input voltage;
[0015] The gates of the two MOS transistors in another single-stage inverter are connected to the negative terminal of the input voltage.
[0016] In some alternative implementations, the two complementary MOS transistors include an NMOS transistor and a PMOS transistor.
[0017] In some optional implementations, the connection relationship between the two MOS transistors of the single-stage inverters other than the first-stage inverter in the cascaded inverter is as follows:
[0018] The source of the NMOS transistor is connected to the power supply terminal;
[0019] The gate of the NMOS transistor is connected to the gate of the PMOS transistor, and is also connected to the drain of the MOS transistor in the previous stage inverter.
[0020] The drain of the NMOS transistor is connected to the drain of the PMOS transistor, and is also connected to the gate of the MOS transistor in the next stage inverter.
[0021] The ring amplifier in this embodiment of the invention adopts a head-to-tail connection method, connecting cascaded inverters and short-circuit inverters according to a set rule, and replacing the resistive load in related technologies with short-circuit inverters, effectively alleviating the problem of the second pole caused by resistance, thereby significantly improving the data processing speed of the ring amplifier.
[0022] In some alternative implementations, both complementary MOS transistors are low-threshold transistors.
[0023] The ring amplifier in this embodiment of the invention uses a low-threshold transistor, which enables the MOS transistor of the output stage inverter to operate in the strong inversion region, effectively avoiding a dynamic stage that generates dead-zone voltage. At the same time, it significantly reduces the output load of the preceding stage inverter, shifts the second pole of the ring amplifier to the right, effectively improves the bandwidth and phase margin of the ring amplifier, thereby significantly shortening the amplification time of the ring amplifier and improving the processing speed and stability of the ring amplifier.
[0024] In some alternative implementations, the differential output terminal outputs a pair of signals with opposite phases and symmetrical amplitudes.
[0025] In a second aspect, the present invention provides an analog-to-digital converter, the analog-to-digital converter comprising the ring amplifier of the first aspect above or any corresponding embodiment thereof.
[0026] In some alternative implementations, the analog-to-digital converter further includes a comparator;
[0027] The differential output of the ring amplifier is connected to the input of the comparator. Attached Figure Description
[0028] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0029] Figure 1 This is a schematic diagram of the structure of a ring amplifier according to an embodiment of the present invention;
[0030] Figure 2 A schematic diagram illustrating the working principle of a specific example of the ring amplifier of the present invention is shown. Detailed Implementation
[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0033] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0034] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0035] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0036] This invention provides a ring amplifier and an analog-to-digital converter. The embodiments of this invention are described below with reference to the accompanying drawings.
[0037] According to an embodiment of the present invention, in one aspect, a ring amplifier is provided. Figure 1 A schematic diagram of the ring amplifier of the present invention is shown.
[0038] The ring amplifier includes two short-circuit inverters DF and a cascaded inverter. Each stage of the cascaded inverter includes two single-stage inverters (shown in the figure as the first-stage inverter F1, the previous stage inverter FQ1 of the output stage, and the output stage inverter FC).
[0039] Both the short-circuit inverter and the single-stage inverter include two complementary MOS transistors.
[0040] In some alternative implementations, the two complementary MOS transistors include an NMOS transistor and a PMOS transistor.
[0041] The gates of the two MOS transistors of the short-circuit inverter are shorted to the drains of the two MOS transistors of the short-circuit inverter.
[0042] The first-stage inverter F1 in the cascaded inverter is connected to the control voltage (VCMFB) and the input voltages VIN (positive voltage) and VIP (positive voltage) of the ring amplifier. The control voltage is the output voltage (VCMFB) of the common-mode feedback circuit of the ring amplifier. The drain of the output stage inverter in the cascaded inverter serves as the differential output terminals OUTP (positive output) and OUTN (negative output) of the ring amplifier.
[0043] The drains of the two MOS transistors in the short-circuit inverter are connected to the gates of the two MOS transistors in the output stage inverter, and the gates of the two MOS transistors in the short-circuit inverter are connected to the drains of the two MOS transistors in the preceding stage inverter of the output stage inverter.
[0044] It should be noted that, Figure 1 The connection relationships of the MOSFETs are not shown in the diagram; please refer to [link / reference needed]. Figure 2 The embodiments shown are not described in detail here.
[0045] The ring amplifier provided in this invention includes a cascaded inverter and two short-circuit inverters. By replacing the resistors in related technologies with short-circuit inverters, dead-zone voltage is effectively avoided. Connecting the short-circuit inverters between the output stage inverter and the preceding stage inverter stabilizes the gate voltage of the MOS transistor in the output stage inverter. Therefore, the ring amplifier can output a stable differential signal.
[0046] Figure 2 A schematic diagram illustrating the working principle of a specific example of the ring amplifier of the present invention is shown. (Reference) Figure 2 Taking a ring amplifier as an example, which includes three stages of inverters, the ring amplifier consists of two first-stage inverters, two second-stage inverters, two short-circuit inverters, and two third-stage inverters.
[0047] Among them, M1 to M18 all represent MOS. M1, M3, M5, M7, M9, M11, M13, M15, and M17 can be N-channel MOS transistors, abbreviated as NMOS. M2, M4, M6, M8, M10, M12, M14, M16, and M18 can be P-channel MOS transistors, abbreviated as PMOS.
[0048] M3 and M4 form a first-stage inverter, and M5 and M6 form a first-stage inverter.
[0049] M7 and M8 form a set of second-stage inverters, and M9 and M10 form a set of second-stage inverters.
[0050] M11 and M12 form a short-circuit inverter, while M13 and M14 form a short-circuit stage inverter.
[0051] M15 and M16 form a set of third-stage inverters, and M17 and M18 form a set of third-stage inverters.
[0052] The third-stage inverter here is... Figure 1 The output stage inverter in the illustrated embodiment. The second stage inverter is... Figure 1 The preceding stage inverter of the output stage inverter in the illustrated embodiment.
[0053] In some optional embodiments, the ring amplifier further includes a first MOS transistor M1. The source of the first MOS transistor M1 is connected to the power supply terminal, the gate is connected to the control voltage, and the drain is connected to the source of the NMOS transistor in the first-stage inverter.
[0054] In some optional embodiments, the ring amplifier further includes a second MOS transistor M2. The source of the second MOS transistor M2 is grounded, its gate is connected to the control voltage, and its drain is connected to the source of the PMOS transistor in the first-stage inverter.
[0055] In some alternative implementations, the gates of the two MOS transistors of one of the single-stage inverters of the first-stage inverter are connected to the positive terminal of the input voltage, and the gates of the two MOS transistors of the other single-stage inverter are connected to the negative terminal of the input voltage.
[0056] In some optional embodiments, the connection relationship between the two MOS transistors in the single-stage inverters other than the first-stage inverter in the cascaded inverter is as follows: the source of the NMOS transistor is connected to the power supply terminal. The gate of the NMOS transistor is connected to the gate of the PMOS transistor and to the drain of the MOS transistor in the previous stage inverter. The drain of the NMOS transistor is connected to the drain of the PMOS transistor and to the gate of the MOS transistor in the next stage inverter.
[0057] Instead of using resistors to generate dead-zone voltage, the loop amplifier uses inverters connected end-to-end. This alleviates the problem of a small second pole to some extent and improves the amplifier's bandwidth. Simultaneously, compensation is established for the stage transconductance (gm) and output resistance (ro). This amplifier exhibits stable gain, gain-bandwidth product (GBW), phase margin (PM), and transient response, improving the stability of the loop amplifier.
[0058] After the second-stage inverter, a short-circuited inverter serves as a load to stabilize the gate voltage of the third-stage PMOS and NMOS.
[0059] The ring amplifier in this embodiment of the invention adopts a head-to-tail connection method, connecting cascaded inverters and short-circuit inverters according to a set rule, and replacing the resistive load in related technologies with short-circuit inverters, effectively alleviating the problem of the second pole caused by resistance, thereby significantly improving the data processing speed of the ring amplifier.
[0060] In some alternative implementations, both complementary MOS transistors are low-threshold transistors.
[0061] Specifically, under the advanced process of MOSFETs, the ring amplifier in this embodiment of the invention uses low-threshold transistors, which makes the MOSFETs of the output stage inverters operate in the strong inversion region, effectively avoiding a dynamic stage that generates dead-zone voltage. At the same time, it significantly reduces the output load of the preceding stage inverter of the output stage inverter, shifts the second pole of the ring amplifier to the right, effectively improves the bandwidth and phase margin of the ring amplifier, thereby significantly shortening the amplification time of the ring amplifier and improving the processing speed and stability of the ring amplifier.
[0062] In some alternative implementations, the differential output terminal outputs a pair of signals with opposite phases and symmetrical amplitudes.
[0063] For example: Figure 2 In this circuit, OUTP (Output Positive) and OUTN (Output Negative) represent the differential output terminals, used to transmit a pair of signals with opposite phases and symmetrical amplitudes.
[0064] The short-circuit inverter load is 1 / g m Assume the second-level load is r o1 The third level load is r o2 Therefore, the external load of the second-stage inverter is
[0065] The total load r of the last two stages of the amplifier o for
[0066] The total gain is Gm *r o ,
[0067] When the W / L (width-to-length ratio) of the second-stage inverter is the same as that of the short-circuit inverter, G m It can be g m N times, so the overall gain of the last two stages is When A INV When the gain approaches N, it becomes close to a constant, thus improving the overall stability of the ring amplifier. Furthermore, setting the W / L of the first-stage inverter to be the same as that of the second-stage inverter can further stabilize the overall gain; however, attention must be paid to the setting of the common-mode feedback circuit's output voltage (VCMFB) in this case.
[0068] In inverters, the W / L (width-to-length ratio) refers to the ratio of the transistor's width (W) to its length (L), and is used to adjust circuit performance. In inverter design, W / L directly affects its drive capability, propagation delay, and power consumption.
[0069] In a second aspect, the present invention provides an analog-to-digital converter, the analog-to-digital converter comprising the ring amplifier of the first aspect above or any corresponding embodiment thereof.
[0070] In some alternative implementations, the analog-to-digital converter further includes a comparator, with the differential output of the ring amplifier connected to the input of the comparator.
[0071] In some alternative implementations, in a SAR ADC (Successive Approximation Analog-to-Digital Converter), OUTP and OUTN are connected to the inputs of the comparator, and the quantized value of the input signal is successively approximated using a binary division method. Further implementation details of the analog-to-digital converter can be found in the implementation details of the ring amplifier in the above embodiments, and will not be repeated here.
[0072] In the specific implementation of the above embodiments, the technical features can be combined in any non-contradictory way. For the sake of brevity, not all possible combinations of the above technical features are described. However, as long as the combination of these technical features is not contradictory, it should be considered to be within the scope of this specification.
[0073] The specific embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.
Claims
1. A ring amplifier, characterized in that, The ring amplifier includes a cascaded inverter and two short-circuit inverters, and each stage of the cascaded inverter includes two single-stage inverters. Both the short-circuit inverter and the single-stage inverter include two complementary MOS transistors; The gates of the two MOS transistors of the short-circuit inverter and the drains of the two MOS transistors of the short-circuit inverter are shorted together. The first-stage inverter in the cascaded inverter is connected to the control voltage and input voltage of the ring amplifier, wherein the control voltage is the output voltage of the common-mode feedback circuit of the ring amplifier; The drain of the output stage inverter in the cascaded inverter serves as the differential output terminal of the ring amplifier. The drains of the two MOS transistors in the short-circuit inverter are connected to the gates of the two MOS transistors in the output stage inverter, and the gates of the two MOS transistors in the short-circuit inverter are connected to the drains of the two MOS transistors in the preceding stage inverter of the output stage inverter.
2. The ring amplifier according to claim 1, characterized in that, The ring amplifier also includes a first MOS transistor; In this configuration, the source of the first MOS transistor is connected to the power supply terminal, the gate is connected to the control voltage, and the drain is connected to the source of the NMOS transistor in the first-stage inverter.
3. The ring amplifier according to claim 2, characterized in that, The ring amplifier also includes a second MOS transistor; In this configuration, the source of the second MOS transistor is grounded, its gate is connected to the control voltage, and its drain is connected to the source of the PMOS transistor in the first-stage inverter.
4. The ring amplifier according to claim 1, characterized in that, In the first-stage inverter, the gates of the two MOS transistors in one of the single-stage inverters are connected to the positive terminal of the input voltage; The gates of the two MOS transistors in another single-stage inverter are connected to the negative terminal of the input voltage.
5. The ring amplifier according to claim 1, characterized in that, The two complementary MOS transistors include an NMOS transistor and a PMOS transistor.
6. The ring amplifier according to claim 5, characterized in that, The connection relationship between the two MOS transistors in the single-stage inverters other than the first-stage inverter in the cascaded inverter is as follows: The source of the NMOS transistor is connected to the power supply terminal; The gate of the NMOS transistor is connected to the gate of the PMOS transistor, and is also connected to the drain of the MOS transistor in the previous stage inverter. The drain of the NMOS transistor is connected to the drain of the PMOS transistor, and is also connected to the gate of the MOS transistor in the next stage inverter.
7. The ring amplifier according to any one of claims 1 to 6, characterized in that, Both complementary MOS transistors are low-threshold transistors.
8. The ring amplifier according to any one of claims 1 to 6, characterized in that, The differential output terminal outputs a pair of signals with opposite phases and symmetrical amplitudes.
9. An analog-to-digital converter, characterized in that, The analog-to-digital converter includes the ring amplifier according to any one of claims 1 to 8.
10. The analog-to-digital converter according to claim 9, characterized in that, The analog-to-digital converter also includes a comparator; The differential output of the ring amplifier is connected to the input of the comparator.