Semiconductor structure and method for preparing semiconductor structure

Abstract

The invention provides a semiconductor structure and a method for preparing the semiconductor structure. The method comprises the following steps: depositing a trap-rich layer on the surface of a substrate; an ultrasonic treatment is applied to the trap-rich layer to reduce the grain size in the trap-rich layer to a range of 30 nm to 150 nm.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for preparing a semiconductor structure. BACKGROUND

[0002] Radio Frequency Silicon-On-Insulator (RF-SOI) technology has become a core radio frequency substrate technology in the fields of 5G / 6G communication, Internet of Things (IoT), and intelligent vehicles, etc. due to its low loss, high linearity, and high integration characteristics. A typical RF-SOI structure includes a substrate formed of a single crystal silicon wafer, and a buried oxide (BOX) layer covering the substrate.

[0003] At the interface between the BOX layer and the substrate, charge carriers are formed due to the attraction of free electrons in the substrate by the fixed positive charges in the BOX layer (for example, positive charges in silicon dioxide), thereby forming a low-resistivity conductive layer, which is also referred to as a PSC layer. The PSC layer reduces the effective resistivity of the substrate, resulting in additional loss of radio frequency signals during transmission due to the enhanced conductivity of the substrate. In addition, the PSC layer causes an increase in parasitic capacitance coupling between adjacent circuits, leading to signal interference. Furthermore, fluctuations in the charge carrier concentration of the PSC layer introduce nonlinear distortion, affecting signal fidelity in high-power or high-frequency applications.

[0004] In order to eliminate the negative effects caused by the PSC layer, a trap-rich layer is usually introduced between the substrate and the BOX layer. The trap-rich layer is usually composed of polysilicon, which forms traps for trapping charge carriers using the grain boundaries and dislocations in the polysilicon to suppress the formation of the PSC layer. However, the grain size of the trap-rich layer is usually large, resulting in a low grain boundary density and a low trap density, which cannot effectively trap charge carriers. SUMMARY

[0005] The present disclosure provides a semiconductor structure and a method for preparing a semiconductor structure, which can reduce the grain size of the trap-rich layer, increase the grain boundary density of the trap-rich layer, and improve the ability of the trap-rich layer to trap charges.

[0006] The technical solution of the present disclosure is implemented as follows: In a first aspect, the present disclosure provides a method for preparing a semiconductor structure, the method comprising: depositing a trap-rich layer on the surface of the substrate; Ultrasonic treatment is applied to the trap-rich layer to reduce the grain size in the trap-rich layer to the range of 30 nm to 150 nm.

[0007] In a second aspect, this disclosure provides a semiconductor structure prepared by the method for preparing a semiconductor structure described in the first aspect. The semiconductor structure includes a substrate and a trap-rich layer deposited on the surface of the substrate, wherein the grain size in the trap-rich layer is 30 nm to 150 nm.

[0008] This disclosure provides a semiconductor structure and a method for fabricating the semiconductor structure. By applying ultrasonic treatment to a trap-rich layer deposited on the surface of a substrate, the vibration energy of the ultrasonic waves promotes the migration of grain boundaries and dislocation reorganization in the trap-rich layer. The vibration of the ultrasonic waves also interferes with the thermal migration activity of the grain boundaries in the trap-rich layer, hindering grain growth. This reduces the grain size in the trap-rich layer, increases the grain boundary density of the trap-rich layer, and enhances the ability of the trap-rich layer to trap charges. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of an SOI structure provided in this disclosure.

[0010] Figure 2 This is a schematic diagram of a method for preparing a semiconductor structure provided in this disclosure.

[0011] Figure 3 A grain image of a portion of the trap-rich layer provided in this disclosure.

[0012] Figure 4 This is an image of a grain in Comparative Example 2 provided in this disclosure.

[0013] Figure 5 Another grain image provided in Comparative Example 2 of this disclosure.

[0014] Figure 6 The image shows a grain in Comparative Example 3 provided in this disclosure.

[0015] Figure 7 The image shows the damage detected in Comparative Example 3 provided in this disclosure.

[0016] Figure 8 Image of the grains in Embodiment 1 provided in this disclosure.

[0017] Figure 9 Image of the grains in Embodiment 2 provided in this disclosure.

[0018] Figure 10 The image shows a grain in Embodiment 3 of this disclosure.

[0019] Figure 11Image of the grains in Embodiment 4 provided in this disclosure.

[0020] Figure 12 The image shows the damage detected in Embodiment 4 of this disclosure.

[0021] Figure 13 Image of the grains in Embodiment 5 provided in this disclosure.

[0022] Figure 14 The image shows the damage detected in Embodiment 5 of this disclosure.

[0023] Figure 15 This is a comparative schematic diagram of grain size provided in this disclosure.

[0024] Figure 16 Image of the grains in Embodiment Six provided in this disclosure.

[0025] Figure 17 Image of the grains in Embodiment 7 provided in this disclosure.

[0026] Figure 18 Image of the grains in Embodiment 8 provided in this disclosure.

[0027] Figure 19 Image of the grains in Embodiment Nine provided in this disclosure.

[0028] Figure 20 This is a comparative schematic diagram of another grain size provided in this disclosure.

[0029] Figure 21 The image shows a grain in Embodiment 10 of this disclosure.

[0030] Figure 22 Image of the grains in Example 11 of this disclosure.

[0031] Figure 23 Image of the grains in Example Twelve of this disclosure.

[0032] Figure 24 This is a grain image from Embodiment Thirteen of this disclosure.

[0033] Figure 25 The image shows the damage detected in Embodiment Thirteen of this disclosure.

[0034] Figure 26 This is a comparative schematic diagram of another grain size provided in this disclosure.

[0035] Figure 27 The image shows the grains of Example 14 provided in this disclosure.

[0036] Figure 28This is a comparative schematic diagram of another grain size provided in this disclosure.

[0037] Figure 29 The image shows a grain of Example 15 provided in this disclosure.

[0038] Figure 30 This is a comparative schematic diagram of another grain size provided in this disclosure.

[0039] Figure 31 The image shows a grain of Example Sixteen provided in this disclosure.

[0040] Figure 32 This is a comparative schematic diagram of another grain size provided in this disclosure.

[0041] Figure 33 The image shows a grain of Example 17 provided in this disclosure.

[0042] Figure 34 This is a comparative schematic diagram of another grain size provided in this disclosure.

[0043] Figure 35 This is a comparative schematic diagram of another grain size provided in this disclosure.

[0044] Figure 36 This is a comparative schematic diagram showing the grain size before and after heat treatment provided in this disclosure.

[0045] Figure 37 This is a schematic diagram comparing the curvature of the trap-rich layer before and after heat treatment, as provided in this disclosure.

[0046] Figure 38 This is a schematic diagram comparing the warpage of the trap-rich layer before and after heat treatment, as provided in this disclosure. Detailed Implementation

[0047] The technical solutions in this disclosure will now be clearly and completely described in conjunction with the accompanying drawings.

[0048] See Figure 1 This is a schematic diagram of an exemplary SOI structure provided in this disclosure. Figure 1 In the SOI structure 1, there are a substrate 11, a trap-rich layer 12 deposited on the substrate 11, and a buried oxide (BOX) layer 13 covering the trap-rich layer 12.

[0049] exist Figure 1In this process, substrate 11 can be a high-resistivity silicon substrate made of single-crystal silicon, typically with a resistivity greater than 2000 ohm·cm. The preparation of substrate 11 may include cutting single-crystal silicon wafers from single-crystal silicon ingots grown by Czochralski (CZ) or Float Zone (FZ) methods, and then applying grinding, etching, and polishing processes to the single-crystal silicon wafers to form polished wafers, which can be used as... Figure 1 The substrate 11 shown is optional. Alternatively, the epitaxial wafer formed by further epitaxial processing of the polished wafer can also be used as... Figure 1 The substrate 11 shown is optional. In addition to single-crystal silicon, the substrate 11 can also be formed of other materials, such as sapphire, silicon carbide, etc., which will not be described in detail in this disclosure.

[0050] exist Figure 1 In this context, the material of the trap-rich layer 12 may include a polycrystalline semiconductor material, which means a material comprising small crystals with random crystal orientation. For example, polycrystalline semiconductor materials include polycrystalline silicon (Poly-Si), polycrystalline silicon germanide (SiGe), polycrystalline silicon carbide (SiC), and polycrystalline germanium (Ge).

[0051] For the above-exemplary polycrystalline semiconductor materials, a trap-rich layer 12 can be formed on the surface of the substrate 11 by vapor deposition. This vapor deposition method includes chemical or physical vapor deposition, such as metal-organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), chemical vapor deposition (CVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), remote plasma chemical vapor deposition (RPCVD), or plasma-enhanced chemical vapor deposition (PECVD), etc.

[0052] exist Figure 1In this process, the material of the BOX layer 13 may include semiconductor oxides, semiconductor nitrides, or semiconductor oxide oxynitrides, such as silicon dioxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON). These materials can also be deposited on the trap-rich layer 12 using vapor deposition to form one or more insulating layers, which form... Figure 1 BOX layer 13 in the middle.

[0053] against Figure 1 The structure shown, taking polycrystalline silicon as the material for the trap-rich layer 12 and silicon dioxide as the material for the BOX layer 13, demonstrates that the polycrystalline silicon grains in the trap-rich layer 12 form numerous grain boundaries. Dangling bonds, dislocations, and vacancies at these grain boundaries act as traps for capturing charge carriers (e.g., electrons or holes). Once trapped, charge carriers cannot migrate freely, thus suppressing the formation of the parasitic surface conduction (PSC) layer. Based on the above explanation of charge carrier capture in the trap-rich layer, it can be seen that as the grain density in the trap-rich layer 12 increases, the density of these trapping defect states also increases, thereby enhancing the charge carrier capture capability of the trap-rich layer 12. Furthermore, there is a negative correlation between grain density and grain size; that is, smaller grain sizes result in a higher number of grains per unit area, leading to a corresponding increase in grain density.

[0054] Based on the above correlations between grain size, grain density, and the ability to trap charge carriers, it can be seen that there is a negative correlation between grain size and the ability of the trap-rich layer 12 to trap charge carriers; that is, the smaller the grain size, the higher the ability of the trap-rich layer 12 to trap charge carriers. Therefore, the grain size can be reduced by grain refinement, thereby improving the ability of the trap-rich layer 12 to trap charge carriers. In related schemes, grain refinement is usually performed by high-temperature annealing after the trap-rich layer 12 is deposited on the surface of the substrate 11. This method requires precise control of process parameters such as annealing temperature, duration, and gas flow; even small fluctuations in process parameters can lead to significant changes in grain size. In addition, high-temperature annealing consumes the overall thermal budget of the process. To address the shortcomings of the above-mentioned related schemes, this disclosure employs ultrasonic processing for grain refinement, aiming to achieve precise control over grain size refinement under low-temperature process conditions.

[0055] Based on this, in this disclosure, such as Figure 2 As shown, it illustrates a method for preparing a semiconductor structure, which may include steps S201 and S202.

[0056] S201: Deposit a trap-rich layer on the surface of the substrate.

[0057] In step S201, the substrate can be exemplary implemented as described above. Figure 1 The substrate 11 in the SOI structure shown. The material of the trap-rich layer can be exemplary implemented as polycrystalline silicon (Poly-Si). In some examples, the thickness of the substrate can range from about 773 micrometers to about 775 micrometers, and the thickness of the trap-rich layer can range from about 1.6 micrometers to about 3.5 micrometers, that is, the trap-rich layer is significantly thinner than the substrate. Of course, the thickness of the substrate and the thickness of the trap-rich layer are not fixed within the numerical ranges in the above examples, and can vary depending on the actual situation, but regardless of the variation in thickness, the trap-rich layer is still significantly thinner than the substrate.

[0058] In some examples, polysilicon (Poly-Si) can be deposited onto the substrate surface in a single growth process using APCVD, LPCVD, or RPCVD to form a trap-rich layer. In specific implementations, the temperature range for depositing polysilicon on the substrate surface is 450°C to 1200°C, and the thickness of the deposited polysilicon (i.e., the thickness of the trap-rich layer) ranges from 1.8 μm to 3 μm. Taking APCVD as an example, at a deposition temperature range of 850°C to 1150°C, the grain size in some regions of the trap-rich layer is as follows: Figure 3 As shown. And through the... Figure 3 The grain sizes of the trap-rich layer shown are statistically analyzed, and the grain size ranges from 450 nm to 800 nm.

[0059] S202: Apply ultrasonic treatment to the trap-rich layer to reduce the grain size in the trap-rich layer to the range of 30nm to 150nm.

[0060] In this disclosure, the high-frequency mechanical vibration of ultrasound generates periodic stress within a trap-rich material (e.g., polycrystalline silicon). This periodic stress activates and drives dislocations pre-existing at the grain boundaries of polycrystalline silicon to move along their slip surfaces. On one hand, the vibrational energy provided by the ultrasound and the resulting dislocation movement promote grain boundary migration and dislocation recombination. The energy accumulated during dislocation recombination leads to the formation of new small-sized grains or the segmentation of existing grains during grain boundary migration, thereby achieving grain size refinement. Furthermore, the relatively uniform action of ultrasonic vibration in all directions induces uniform grain growth in all directions during the formation of new small-sized grains or the segmentation of existing grains, resulting in equiaxed crystals. On the other hand, grain coarsening (i.e., size increase) depends on the directional migration of atoms across grain boundaries through thermal activation. Although the high-frequency vibration of ultrasound increases the atomic kinetic energy of the grains, the rapid periodicity and non-directionality of this kinetic energy will hinder the directional atomic jumping process dominated by thermal energy. This interference with the thermally activated migration of grain boundaries effectively suppresses the tendency of polycrystalline silicon grains to coarsen in the high-temperature environment they may experience in the future.

[0061] In this disclosure, a trap-rich layer is deposited on the substrate surface, forming a monolithic structure between the trap-rich layer and the substrate. Based on this, ultrasonic treatment can be applied to the monolithic structure formed by the trap-rich layer and the substrate, thereby applying ultrasonic treatment to the trap-rich layer within the monolithic structure.

[0062] for Figure 2 The technical solution shown applies ultrasonic treatment to the trap-rich layer deposited on the surface of the substrate. The vibration energy of the ultrasonic wave promotes the migration of grain boundaries and dislocation reorganization in the trap-rich layer. The vibration of the ultrasonic wave also interferes with the thermal migration activity of the grain boundaries in the trap-rich layer, hindering grain growth. This reduces the grain size in the trap-rich layer, increases the grain boundary density of the trap-rich layer, and enhances the ability of the trap-rich layer to trap charges.

[0063] In combination with the above Figure 2 It should be noted that during the ultrasonic treatment of the trap-rich layer, the mechanical vibration of the ultrasound may cause physical damage to the thin and brittle semiconductor material, such as cracking or breakage of the trap-rich layer and the substrate. Furthermore, the ultrasonic vibration can generate shear stress at the interface between the trap-rich layer and the substrate, which may cause the trap-rich layer to peel off from the substrate.

[0064] The risks involved in these implementation processes are primarily influenced by three operating parameters: ultrasonic power, frequency, and processing time. Specifically, firstly, the ultrasonic power directly determines the intensity and energy input rate of the mechanical vibration applied to the trap-rich layer and substrate. If the power is too high, it means that the stress amplitude experienced by the trap-rich layer and substrate is enormous, which could very likely exceed the strength limit of the trap-rich layer and substrate in a very short time, leading to catastrophic mechanical damage (such as cracking of the trap-rich layer, substrate fracture, or peeling of the trap-rich layer from the substrate). Even if the frequency and processing time of the ultrasonic waves are set appropriately, uncontrolled power can still cause immediate and irreversible damage to the trap-rich layer and substrate.

[0065] Secondly, the frequency of ultrasound determines the vibration period and wavelength, which directly affects the interaction of ultrasonic energy with microstructures (such as lattices, dislocations, and grain boundaries) at different scales within the trap-rich layer and substrate. Different frequencies are suitable for driving physical processes at different scales; for example, higher frequency ultrasound is generally more suitable for manipulating nanoscale structures. Frequency also affects the amplitude of vibration at a fixed power; lower frequencies are usually accompanied by larger amplitudes, which may increase the risk of mechanical damage and also affect the uniformity of energy distribution in the material.

[0066] The duration of ultrasonic treatment then determines the total dose of ultrasonic energy received by the trap-rich layer and the substrate, as well as the total duration of the treatment process. After power and frequency settings, the duration controls the degree of microstructure evolution. However, excessively long treatment times may lead to "over-processing," such as excessive grain refinement (if applicable) or anomalous growth, and may induce material fatigue and micro-damage accumulation in the trap-rich layer and the substrate, increasing overall heat accumulation and the risk of introducing potential defects.

[0067] Based on the above analysis and explanation of the three working parameters of ultrasound—power, frequency, and processing time—this disclosure determines the range of working parameters that can both refine grain size and reduce risk through the following embodiments and comparative examples.

[0068] In the following examples and comparative cases, the initial conditions were the same: the material of the trap-rich layer was polycrystalline silicon, and the substrate material was a single-crystal silicon wafer. The trap-rich layer was deposited on the surface of the substrate using APCVD at a deposition temperature range of 850°C to 1150°C, thus obtaining a substrate with a trap-rich layer. Furthermore, the grain size of the trap-rich layer was obtained by detecting the trap-rich layer using a scanning electron microscope (SEM), and the output SEM image size was 5µm × 5µm. After obtaining the SEM image of the trap-rich layer, the numerical range of the grain size of the trap-rich layer was calculated based on the image size and the area of ​​the trap-rich layer.

[0069] Comparative Example 1 After obtaining a substrate with a trap-rich layer via APCVD, the trap-rich layer is not subjected to ultrasonic treatment; instead, it is directly inspected using SEM. The resulting grain images are as follows: Figure 3 As shown, the range of grain size is 450 nm to 800 nm, the median grain size is 630 nm, and the first and third quartiles of the grain size are 520 nm and 720 nm, respectively.

[0070] Comparative Example 2 After obtaining a substrate with a trap-rich layer via APCVD, the trap-rich layer was subjected to ultrasonic treatment. During the ultrasonic treatment, the ultrasonic power was 1500 W, the frequency was 10 kHz, and the treatment durations were 0.5 hours and 2 hours, respectively. The grain images obtained after the ultrasonic treatment for 0.5 hours and 2 hours are shown below. Figure 4 and Figure 5 As shown. Visually, it will... Figure 4 and Figure 5 respectively with Figure 3 Comparison reveals that, with lower ultrasonic power and frequency, increasing the ultrasonic treatment time resulted in poorer grain refinement. Figure 4 and Figure 5 The grain size shown in the figure is consistent with Figure 3 The grain sizes shown in the figures do not show significant differences.

[0071] Comparative Example 3 After obtaining a substrate with a trap-rich layer via APCVD, the trap-rich layer was subjected to ultrasonic treatment. During the ultrasonic treatment, the ultrasonic power was 4000 W, the frequency was 30 kHz, and the treatment time was 0.5 hours. The resulting grain image after the ultrasonic treatment is shown below. Figure 6 As shown. Figure 6 and Figure 3 Comparison reveals that the grain refinement effect is significant, with a marked reduction in grain size. However, damage detection at the interface between the ultrasonically treated substrate and the trap-rich layer yields the following results: Figure 7 As shown. From Figure 7 As can be seen, when the power and frequency of ultrasound are high, although it can refine the grains, it increases the probability of physical damage to the trap-rich layer and the substrate.

[0072] As can be seen from Comparative Examples 1 to 3 above, in order to refine grain size while reducing the risk of physical damage and delamination, the power and frequency of the ultrasonic waves need to be controlled within an appropriate range. For example, the power of the ultrasonic waves can be greater than 1500W and less than 4000W, and the frequency can be greater than 10kHz and less than 30kHz. Based on the above ranges, this disclosure analyzes the effects of ultrasonic power, frequency, and processing time on grain refinement through Examples 1 to 13 below.

[0073] Example 1 After obtaining a substrate with a trap-rich layer via APCVD, the trap-rich layer was subjected to ultrasonic treatment. During the ultrasonic treatment, the ultrasonic power was 1800 W, the frequency was 18 kHz, and the treatment time was 1 hour. The trap-rich layer after ultrasonic treatment was detected using SEM, and the resulting grain images are shown below. Figure 8 As shown, the range of grain size is approximately 340 nm to 630 nm, with a median grain size of approximately 500 nm. The first and third quartiles of the grain size are approximately 430 nm and 540 nm, respectively.

[0074] Example 2 After obtaining a substrate with a trap-rich layer via APCVD, the trap-rich layer was subjected to ultrasonic treatment. During the ultrasonic treatment, the ultrasonic power was 2000 W, the frequency was 18 kHz, and the treatment time was 1 hour. The trap-rich layer after ultrasonic treatment was detected using SEM, and the resulting grain images are shown below. Figure 9 As shown, the range of grain size is approximately 310 nm to 520 nm, with a median grain size of approximately 440 nm. The first and third quartiles of the grain size are approximately 400 nm and 490 nm, respectively.

[0075] Example 3 After obtaining a substrate with a trap-rich layer via APCVD, the trap-rich layer was subjected to ultrasonic treatment. During the ultrasonic treatment, the ultrasonic power was 2500 W, the frequency was 18 kHz, and the treatment time was 1 hour. The trap-rich layer after ultrasonic treatment was detected using SEM, and the resulting grain images are shown below. Figure 10 As shown, the range of grain size is approximately 105 nm to 420 nm, with a median grain size of approximately 300 nm. The first and third quartiles of the grain size are approximately 230 nm and 350 nm, respectively.

[0076] Example 4 After obtaining a substrate with a trap-rich layer via APCVD, the trap-rich layer was subjected to ultrasonic treatment. During the ultrasonic treatment, the ultrasonic power was 3000 W, the frequency was 18 kHz, and the treatment time was 1 hour. The trap-rich layer after ultrasonic treatment was detected using SEM, and the resulting grain images are shown below. Figure 11 As shown, the grain size range is approximately 60 nm to 270 nm, with a median grain size of approximately 140 nm. The first and third quartiles of the grain size are approximately 80 nm and 225 nm, respectively. Furthermore, in this fifth embodiment, damage detection was performed at the interface between the substrate and the trap-rich layer after ultrasonic treatment. The detection results are as follows... Figure 12 As shown, from Figure 12 As can be seen, when the ultrasonic power is 3000W, no significant damage has yet occurred at the interface between the substrate and the trap-rich layer.

[0077] Example 5 After obtaining a substrate with a trap-rich layer via APCVD, the trap-rich layer was subjected to ultrasonic treatment. During the ultrasonic treatment, the ultrasonic power was 3500 W, the frequency was 18 kHz, and the treatment time was 1 hour. The trap-rich layer after ultrasonic treatment was detected using SEM, and the resulting grain images are shown below. Figure 13 As shown, the grain size range is approximately 50 nm to 220 nm, with a median grain size of approximately 110 nm. The first and third quartiles of the grain size are approximately 70 nm and 140 nm, respectively. Furthermore, in this sixth embodiment, damage detection was performed at the interface between the substrate and the trap-rich layer after ultrasonic treatment. The detection results are as follows... Figure 14 As shown, from Figure 14 As can be seen, when the ultrasonic power is 3500W, there is already obvious damage at the interface between the substrate and the trap-rich layer that can be detected by visual inspection.

[0078] The grain size statistical results of Examples 1 to 5 above were used... Figure 15 The box plots shown are compared. Figure 15 In the diagram, the horizontal axis represents the power of the ultrasonic wave, measured in watts (W), and the vertical axis represents the grain size, measured in nanometers (nm). From... Figure 15 As can be seen, when the frequency and processing time of the ultrasound are the same, the higher the power of the ultrasound, the better the grain size refinement effect. However, considering the risk of physical damage caused by higher power, the power range of the ultrasound used to apply the ultrasound treatment to the trap-rich layer in this disclosure is 1800w to 3000w.

[0079] Example 6 After obtaining a substrate with a trap-rich layer via APCVD, the trap-rich layer was subjected to ultrasonic treatment. During the ultrasonic treatment, the ultrasonic power was 2000 W, the frequency was 15 kHz, and the treatment time was 1 hour. The trap-rich layer after ultrasonic treatment was detected using SEM, and the resulting grain images are shown below. Figure 16 As shown, the range of grain size is approximately 330 nm to 750 nm, with a median grain size of approximately 510 nm. The first and third quartiles of the grain size are approximately 450 nm and 620 nm, respectively.

[0080] Example 7 After obtaining a substrate with a trap-rich layer via APCVD, the trap-rich layer was subjected to ultrasonic treatment. During the ultrasonic treatment, the ultrasonic power was 2000 W, the frequency was 20 kHz, and the treatment time was 1 hour. The trap-rich layer after ultrasonic treatment was detected using SEM, and the resulting grain images are shown below. Figure 17 As shown, the range of grain size is approximately 190 nm to 460 nm, with a median grain size of approximately 380 nm. The first and third quartiles of the grain size are approximately 310 nm and 410 nm, respectively.

[0081] Example 8 After obtaining a substrate with a trap-rich layer via APCVD, the trap-rich layer was subjected to ultrasonic treatment. During the ultrasonic treatment, the ultrasonic power was 2000 W, the frequency was 22 kHz, and the treatment time was 1 hour. The trap-rich layer after ultrasonic treatment was detected using SEM, and the resulting grain images are shown below. Figure 18 As shown, the range of grain size is approximately 80 nm to 400 nm, with a median grain size of approximately 310 nm. The first and third quartiles of the grain size are approximately 230 nm and 350 nm, respectively.

[0082] Example 9 After obtaining a substrate with a trap-rich layer via APCVD, the trap-rich layer was subjected to ultrasonic treatment. During the ultrasonic treatment, the ultrasonic power was 2000 W, the frequency was 25 kHz, and the treatment time was 1 hour. The trap-rich layer after ultrasonic treatment was detected using SEM, and the resulting grain images are shown below. Figure 19 As shown, the range of grain size is approximately 50 nm to 220 nm, with a median grain size of approximately 110 nm. The first and third quartiles of the grain size are approximately 50 nm and 140 nm, respectively.

[0083] The grain size statistical results of Examples 2 and 6 to 9 above were used... Figure 20 Compare the box plots shown. By... Figure 20 It can be seen that, with the same ultrasonic power and processing time, the higher the ultrasonic frequency (unit: kilohertz kHz), the better the grain size (unit: nanometer). However, considering the risk of physical damage caused by higher frequencies (such as 30 kHz used in the aforementioned Comparative Example 3), the ultrasonic frequency range used in this disclosure for applying ultrasonic treatment to the trap-rich layer is 15 kHz to 25 kHz.

[0084] Example 10 After obtaining a substrate with a trap-rich layer via APCVD, the trap-rich layer was subjected to ultrasonic treatment. During the ultrasonic treatment, the ultrasonic power was 2000 W, the frequency was 18 kHz, and the treatment time was 0.5 hours. The trap-rich layer after ultrasonic treatment was detected using SEM, and the resulting grain images are shown below. Figure 21 As shown, the range of grain size is approximately 400 nm to 620 nm, with a median grain size of approximately 510 nm. The first and third quartiles of the grain size are approximately 450 nm and 540 nm, respectively.

[0085] Example 11 After obtaining a substrate with a trap-rich layer via APCVD, the trap-rich layer was subjected to ultrasonic treatment. During the ultrasonic treatment, the ultrasonic power was 2000 W, the frequency was 18 kHz, and the treatment time was 1.5 hours. The trap-rich layer after ultrasonic treatment was detected using SEM, and the resulting grain images are shown below. Figure 22 As shown, the range of grain size is approximately 170 nm to 430 nm, with a median grain size of approximately 260 nm. The first and third quartiles of the grain size are approximately 220 nm and 320 nm, respectively.

[0086] Example 12 After obtaining a substrate with a trap-rich layer via APCVD, the trap-rich layer was subjected to ultrasonic treatment. During the ultrasonic treatment, the ultrasonic power was 2000 W, the frequency was 18 kHz, and the treatment time was 2 hours. The trap-rich layer after ultrasonic treatment was detected using SEM, and the resulting grain images are shown below. Figure 23As shown, the range of grain size is approximately 70 nm to 250 nm, with a median grain size of approximately 120 nm. The first and third quartiles of the grain size are approximately 90 nm and 160 nm, respectively.

[0087] Example 13 After obtaining a substrate with a trap-rich layer via APCVD, the trap-rich layer was subjected to ultrasonic treatment. During the ultrasonic treatment, the ultrasonic power was 2000 W, the frequency was 18 kHz, and the treatment time was 2.5 hours. The trap-rich layer after ultrasonic treatment was detected using SEM, and the resulting grain images are shown below. Figure 24 As shown. Furthermore, in this fourteenth embodiment, damage detection was performed at the interface between the substrate and the trap-rich layer after ultrasonic treatment, and the detection results are as follows. Figure 25 As shown, from Figure 25 As can be seen, when the ultrasonic treatment time is 2.5 hours, there is already obvious damage at the interface between the substrate and the trap-rich layer that can be detected by visual inspection.

[0088] The grain size statistical results of Examples 2 and 10 to 12 above were used... Figure 26 Compare the box plots shown. By... Figure 26 It can be seen that, under the same power and frequency of ultrasound, the higher the processing time (time, unit: hours h), the better the grain size (Nm) refinement effect. However, considering the risk of physical damage caused by a higher processing time (such as 2.5 hours used in Example 13), in this disclosure, the processing time of ultrasound used to apply ultrasound to the trap-rich layer is in the range of 0.5 hours to 2 hours.

[0089] The analysis of Examples 1 to 12 above reveals the influence of any single parameter among the three operating parameters—ultrasonic power, frequency, and processing time—on the grain refinement effect. In conjunction with the twelve examples above, this disclosure further analyzes the interaction (e.g., synergistic and antagonistic effects) among these three parameters through the following examples.

[0090] Example 14 After obtaining a substrate with a trap-rich layer via APCVD, the trap-rich layer was subjected to ultrasonic treatment. During the ultrasonic treatment, the ultrasonic power was 3000 W, the frequency was 25 kHz, and the treatment time was 1 hour. The trap-rich layer after ultrasonic treatment was detected using SEM, and the resulting grain images are shown below. Figure 27As shown, the grain size range is approximately 60 nm to 270 nm, with a median grain size of approximately 150 nm. The first and third quartiles of the grain size are approximately 80 nm and 240 nm, respectively. The grain size statistics of Example Fourteen and Example One are compared using... Figure 28 The comparison of the box plots shown shows that increasing both the power and frequency of the ultrasonic waves can significantly improve the grain size (nm) refinement.

[0091] Example 15 After obtaining a substrate with a trap-rich layer via APCVD, the trap-rich layer was subjected to ultrasonic treatment. During the ultrasonic treatment, the ultrasonic power was 1800 W, the frequency was 25 kHz, and the treatment time was 1 hour. The trap-rich layer after ultrasonic treatment was detected using SEM, and the resulting grain images are shown below. Figure 29 As shown, the grain size range is approximately 40 nm to 200 nm, with a median grain size of approximately 130 nm. The first and third quartiles of the grain size are approximately 100 nm and 160 nm, respectively. The grain size statistics of Examples 15 and 4 are compared using the following method... Figure 30 The box plots shown demonstrate that, compared to low-power-high-frequency ultrasonic treatment, high-power-low-frequency ultrasonic treatment achieves better grain refinement. This comparison reflects that frequency parameters have a greater impact on grain size refinement than power parameters.

[0092] Example 16 After obtaining a substrate with a trap-rich layer via APCVD, the trap-rich layer was subjected to ultrasonic treatment. During the ultrasonic treatment, the ultrasonic power was 3000 W, the frequency was 18 kHz, and the treatment time was 2 hours. The trap-rich layer after ultrasonic treatment was detected using SEM, and the resulting grain images are shown below. Figure 31 As shown, the grain size range was statistically determined to be approximately 30 nm to 205 nm, with a median grain size of approximately 90 nm. The first and third quartiles of the grain size were approximately 65 nm and 125 nm, respectively. The grain size statistical results from Examples Sixteen, Four, and Twelve were compared using... Figure 32Comparing the box plots shown, the results indicate that simultaneously increasing the ultrasonic power and processing time improves the grain refinement effect. Furthermore, comparing the high-power, low-time ultrasonic treatment shown in Example 4 with the low-power, high-time ultrasonic treatment shown in Example 12, it is evident that increasing the power allows for smaller grain sizes; however, the average grain size and size range are still better with higher processing times.

[0093] Example 17 After obtaining a substrate with a trap-rich layer via APCVD, the trap-rich layer was subjected to ultrasonic treatment. During the ultrasonic treatment, the ultrasonic power was 3000 W, the frequency was 25 kHz, and the treatment time was 2 hours. The trap-rich layer after ultrasonic treatment was detected using SEM, and the resulting grain images are shown below. Figure 33 As shown, the grain size range is approximately 25 nm to 125 nm, with a median grain size of approximately 60 nm. The first and third quartiles of the grain size are approximately 45 nm and 85 nm, respectively. The grain size statistics of Examples 17 and 4 are compared using the following method... Figure 34 The box plots shown are compared, and the results show that increasing both the frequency and processing time of the ultrasound can improve the grain refinement effect.

[0094] As can be seen from Examples 1 to 16 above, in this disclosure, the preferred range of ultrasonic power is 3000-3500W, the preferred range of frequency is 25-30kHz, and the preferred range of processing time is 2-2.5h. After applying ultrasonic treatment to the trap-rich layer according to the above preferred parameter values, the grain size in the trap-rich layer ranges from 30 nm to 150 nm. The statistical results of its grain size are compared with the grain size statistical results of Comparative Example 1. Figure 35 Compare the box plots shown.

[0095] Based on the aforementioned technical solution of this disclosure, in order to repair the damage generated on the substrate surface and optimize the curvature and warpage of the substrate with the deposited trap-rich layer after ultrasonic treatment, in some examples, after applying ultrasonic treatment to the trap-rich layer, the method further includes: heat treatment of the substrate with the deposited trap-rich layer.

[0096] In the above example, during the actual implementation process, the temperature range of the heat treatment is 800 degrees Celsius to 1200 degrees Celsius, and the duration of the heat treatment ranges from 1 to 20 minutes.

[0097] It should be noted that the heat treatment process can optimize the curvature and warpage of the deposited trap-rich layer, repair minor damage on the substrate surface, and improve the flatness of the substrate with the deposited trap-rich layer. Specifically, within the aforementioned time range, a time shorter than the minimum of 1 minute will not reduce warpage, while a time longer than the maximum of 20 minutes will increase grain size.

[0098] Furthermore, under thermal conditions, the atoms of the grains undergo directional migration across grain boundaries via thermal activation, resulting in grain coarsening, meaning the grain size increases significantly with heat treatment. However, after ultrasonic treatment of the trap-rich layer, the rapidly changing periodic and non-directional kinetic energy generated by the high-frequency vibrations of the ultrasound waves hinders or interferes with the directional thermal activation migration process of the grain atoms, effectively suppressing the tendency for grain coarsening during heat treatment.

[0099] In this disclosure, taking the example of a grain size ranging from 30 nanometers to 150 nanometers in a trap-rich layer deposited on the substrate surface after ultrasonic treatment, the substrate that has undergone ultrasonic treatment is subjected to heat treatment. Figure 36 The comparison of grain size in the trap-rich layer before and after heat treatment is shown. Figure 36 As shown, after heat treatment (After), the grain size in the trap-rich layer deposited on the substrate surface ranges from 62 nm to 175 nm, with a median grain size of approximately 110 nm. The first and third quartiles of the grain size are approximately 90 nm and 140 nm, respectively. Before heat treatment (Before), the grain size in the trap-rich layer deposited on the substrate surface ranges from 20 nm to 148 nm, with a median grain size of approximately 80 nm. The first and third quartiles of the grain size are approximately 55 nm and 120 nm, respectively. Figure 36 It can be seen that although the grains coarsened, the grain size growth was limited and there was no significant increase in grain size as is usually seen.

[0100] In addition, such as Figure 37 As shown, before heat treatment, the bow of the trap-rich layer ranges from approximately 26 to 45 micrometers, with a median bow of approximately 33 micrometers. The first and third quartiles of the bow are approximately 28 and 41 micrometers, respectively. After heat treatment, the bow of the trap-rich layer ranges from approximately 8 to 25 micrometers, with a median bow of approximately 15 micrometers. The first and third quartiles of the bow are approximately 9 and 21 micrometers, respectively.

[0101] like Figure 38As shown, before heat treatment, the warp of the trap-rich layer ranges from approximately 58 μm to 88 μm, with a median warp of approximately 80 μm. The first and third quartiles of the warp are approximately 60 μm and 86 μm, respectively. After heat treatment, the warp of the trap-rich layer ranges from approximately 20 μm to 60 μm, with a median warp of approximately 34 μm. The first and third quartiles of the warp are approximately 25 μm and 58 μm, respectively.

[0102] from Figure 37 as well as Figure 38 It can be seen that the heat treatment process can optimize the curvature and warpage of the deposited trap-rich layer and improve the flatness of the substrate with the deposited trap-rich layer.

[0103] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily as long as they do not conflict.

[0104] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that, The method includes: Deposit a trap-rich layer on the surface of the substrate; The trap-rich layer is subjected to ultrasonic treatment to reduce the grain size in the trap-rich layer to the range of 30 nm to 150 nm.

2. The method according to claim 1, characterized in that, During the ultrasonic treatment of the trap-rich layer, the power of the ultrasonic waves ranges from 1800W to 3000W.

3. The method according to claim 1, characterized in that, During the ultrasonic treatment of the trap-rich layer, the frequency range of the ultrasonic waves is from 15 kHz to 30 kHz.

4. The method according to claim 1, characterized in that, The duration of the ultrasonic treatment ranges from 0.5 hours to 2 hours.

5. The method according to claim 1, characterized in that, After ultrasonic treatment is applied to the trap-rich layer, the grain size in the trap-rich layer ranges from 30 nanometers to 150 nanometers.

6. The method according to claim 1, characterized in that, The method further includes: After applying ultrasonic treatment to the trap-rich layer, the substrate on which the trap-rich layer is deposited is subjected to heat treatment.

7. The method according to claim 6, characterized in that, The temperature range for the heat treatment is 800 degrees Celsius to 1200 degrees Celsius.

8. The method according to claim 6, characterized in that, The duration of the heat treatment ranges from 30 seconds to 300 seconds.

9. The method according to claim 6, characterized in that, After heat treatment of the substrate on which the trap-rich layer is deposited, the grain size of the trap-rich layer deposited on the surface of the substrate ranges from 62 nanometers to 180 nanometers, and the curvature of the trap-rich layer ranges from 8 micrometers to 25 micrometers, and / or the warpage of the trap-rich layer ranges from 20 micrometers to 60 micrometers.

10. The method according to any one of claims 1 to 9, characterized in that, The substrate comprises a monocrystalline silicon wafer, and the trap-rich layer comprises polycrystalline silicon.

11. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the method of preparing a semiconductor structure according to any one of claims 1 to 10, the semiconductor structure comprising a substrate and a trap-rich layer deposited on the surface of the substrate, wherein the grain size in the trap-rich layer is 30 nm to 150 nm.

12. The semiconductor structure according to claim 11, characterized in that, The grain size of the trap-rich layer is 62 nm to 180 nm, and the curvature of the trap-rich layer is in the range of 8 μm to 25 μm, and / or the warpage of the trap-rich layer is in the range of 20 μm to 60 μm.

13. The semiconductor structure according to claim 11 or 12, characterized in that, The substrate comprises a monocrystalline silicon wafer, and the trap-rich layer comprises polycrystalline silicon.

Images