Semiconductor integrated circuit design support method

Abstract

A semiconductor integrated circuit design support method comprises the following steps: a conversion step of converting a hardware description text into a graph object; a reasoning step: inputting the graph object into a trained neural network through a GAT method, and reasoning a reasoning physical measurement index of the semiconductor integrated circuit; and an extraction step of extracting a significant portion of the hardware description text from the reasoning physical metric index, the graph object including nodes and edges, the nodes including a first node including description position information representing a position of a corresponding description in the hardware description text, and the first node including a second node representing a position of the corresponding description in the hardware description text. The neural network comprises an attention coefficient serving as a weight and representing the influence degree of an edge on the reasoning physical measurement index, and in the extraction step, a first edge is determined according to the attention coefficient, and a part in the hardware description text is extracted as a significant part according to description position information of a first node corresponding to the first edge.

Description

Technical Field

[0001] This disclosure relates to methods for supporting semiconductor integrated circuit design. Background Technology

[0002] A design method for semiconductor integrated circuits has been previously discussed. The process of generating information required for the design and manufacture of semiconductor integrated circuits includes many stages, from the initial stage to the final stage. The initial stage involves determining the working specifications, represented by hardware description text described using a hardware description language, while the final stage involves the layout of the various components and wiring of the semiconductor integrated circuit (for example, see Patent Document 1). Patent Document 1 describes a concept for inferring quality metrics of a semiconductor integrated circuit manufactured according to the design during the initial stage of design. Accordingly, by providing feedback on quality metrics to improve the design, it is possible to shorten the design time without performing all stages of the design process.

[0003] (Existing technical literature)

[0004] (Patent Documents)

[0005] Patent Document 1: U.S. Patent Application Publication No. 2021 / 0287120

[0006] (Non-patent literature)

[0007] Non-patent literature 1: Petar Velickovic, et al., “Graph Attention Networks”, ICLR, 2018 Summary of the Invention

[0008] The problem that the invention aims to solve

[0009] However, Patent Document 1 does not disclose a feedback method for a specific design. Therefore, even if quality metrics can be deduced, it is impossible to estimate, for example, which description in the hardware description text described by the hardware description language should be fed back.

[0010] Therefore, the present disclosure aims to provide a semiconductor integrated circuit design support method that can accurately infer the physical metrics of a semiconductor integrated circuit based on the hardware description text describing the semiconductor integrated circuit, and can determine the description location of the hardware description text that has a significant impact on the physical metrics.

[0011] Methods for solving problems

[0012] To achieve the above objectives, one aspect of the semiconductor integrated circuit design support method disclosed herein includes the following steps: a conversion step, converting hardware description text describing the semiconductor integrated circuit using a hardware description language into a graph object in CDFG (Control Data Flow Graph) format; and an inference step, inputting the graph object into a graph object using GAT (Graph Attention). The method describes a trained neural network represented by a graph attention network (GAN) and infers an inference physical metric of the semiconductor integrated circuit. The method includes an extraction step whereby a salient portion of a hardware description text is extracted based on the inference physical metric. The graph object includes multiple nodes and one or more edges that transform descriptions within the hardware description text. The multiple nodes include one or more first nodes embedded with description location information representing positions within the hardware description text. Each of the one or more first nodes is associated with a description within the hardware description text indicated by the description location information. The neural network includes attention coefficients as weights, representing the degree of influence of each of the one or more edges on the inference physical metric. In the extraction step, one or more first edges are determined based on the attention coefficients, and a portion of the hardware description text is extracted as the salient portion based on the description location information of the first nodes corresponding to the one or more first edges.

[0013] Invention Effects

[0014] This disclosure provides a semiconductor integrated circuit design support method that can accurately infer the physical metrics of a semiconductor integrated circuit based on the hardware description text describing the semiconductor integrated circuit, and can determine the description location of the hardware description text that has a significant impact on the physical metrics. Attached Figure Description

[0015] Figure 1 This is a block diagram illustrating the functional configuration of the semiconductor integrated circuit design support device according to the embodiment.

[0016] Figure 2 This is a block diagram showing an outline of the functional configuration of the preparation unit involved in the embodiment.

[0017] Figure 3 This is a block diagram showing an outline of the functional configuration of the estimation unit involved in the embodiment.

[0018] Figure 4 This is a diagram illustrating an example of hardware description text.

[0019] Figure 5 This is a diagram illustrating an example of a training diagram object involved in the implementation method.

[0020] Figure 6 This is a diagram illustrating an example of the hardware configuration of a computer that implements the functions of a semiconductor integrated circuit design support device via software, as described in the embodiment.

[0021] Figure 7 This is a flowchart illustrating the process of the semiconductor integrated circuit design support method involved in the implementation.

[0022] Figure 8 This is a flowchart illustrating the preparation steps of the semiconductor integrated circuit design support method involved in the implementation.

[0023] Figure 9 This is a flowchart illustrating the derivation steps of the semiconductor integrated circuit design support method involved in the implementation. Detailed Implementation

[0024] Hereinafter, embodiments of the present disclosure will be specifically described with reference to the accompanying drawings. Furthermore, the embodiments described below are all specific examples of the present disclosure. The numerical values, shapes, materials, standards, constituent elements, the arrangement and connection methods of constituent elements, steps, and the order of steps shown in the following embodiments are all examples and are not intended to limit the present disclosure. Moreover, constituent elements not described in the independent technical solutions illustrating the highest-level concept of the present disclosure will be described as arbitrary constituent elements. Furthermore, the figures are not strictly illustrative. In the figures, substantially identical components are given the same symbols, and there are instances where repeated descriptions are omitted or simplified.

[0025] (Implementation Method)

[0026] The semiconductor integrated circuit design support method and semiconductor integrated circuit design support apparatus involved in the implementation method will be described.

[0027] [1. Semiconductor Integrated Circuit Design Support Device]

[0028] use Figures 1 to 3 The configuration of the semiconductor integrated circuit design support device involved in this embodiment will be described. Figure 1 This is a block diagram showing an outline of the functional configuration of the semiconductor integrated circuit design support device 10 according to this embodiment. Figure 2 This is a block diagram showing an outline of the functional configuration of the preparation unit 20 according to this embodiment. Figure 3This is a block diagram showing an outline of the functional configuration of the estimation unit 60 according to this embodiment.

[0029] The semiconductor integrated circuit design support device 10 is an apparatus that performs the following processing: estimating the physical metrics of a semiconductor integrated circuit designed based on a hardware description text (HMR), and supporting feedback on the HMR by extracting significant portions of the HMR that have a major impact on the physical metrics. The HMR is a description of the semiconductor integrated circuit using a hardware description language. It describes the configuration, operation, and other specifications of the semiconductor integrated circuit. There are no specific limitations on the hardware description language used to describe the HMR. For example, the HMR can be described using RTL (Register Transfer Level), behavioral level, or Unified Modeling Language (UML).

[0030] Here, physical metrics refer to indicators based on the physical concepts of semiconductor integrated circuits. Examples of physical metrics include, for instance, wiring congestion, which indicates the number of wirings present per unit area in the layout data of a semiconductor integrated circuit, and power density, which indicates the power consumed per unit area in the layout data of a semiconductor integrated circuit.

[0031] like Figure 1 As shown, the semiconductor integrated circuit design support device 10 includes a preparation unit 20 and an estimation unit 60.

[0032] Preparation unit 20 is a processing unit that prepares a trained neural network represented using the GAT (Graph Attention Networks) method. For example... Figure 2 As shown, the preparation unit 20 includes a description text storage unit 22, an RTL storage unit 24, a parser 26, a conversion unit 28, an input information storage unit 30, a training unit 32, a logic synthesis unit 34, a layout unit 36, a derivation unit 38, and a related decision unit 40.

[0033] The description text storage unit 22 is an example of a training description text storage unit that stores training hardware description text used for training neural networks. The training hardware description text describes a training semiconductor integrated circuit. The description text storage unit 22 stores more than one training hardware description text. Here, utilizing... Figure 4 Provide a description of the hardware description text. Figure 4 This is a diagram illustrating an example of hardware description text. (Example:) Figure 4As shown, the hardware description text is code written in a hardware description language. Figure 4 The line number Ln of the hardware description text is also shown in the text.

[0034] RTL storage unit 24 stores hardware description text that corresponds to the RTL-described training hardware description text stored in description text storage unit 22. Alternatively, the training hardware description text stored in description text storage unit 22 may also be RTL-described hardware description text, just like the hardware description text stored in RTL storage unit 24. In other words, description text storage unit 22 may also store the same training hardware description text as that stored in RTL storage unit 24. In this case, description text storage unit 22 may also function as RTL storage unit 24.

[0035] Parser 26 is a processing unit that performs syntax parsing on the training hardware description text stored in description text storage unit 22.

[0036] The conversion unit 28 is a processing unit that converts training hardware description text into training graph objects in CDFG (Control Data Flow Graph) format, and is an example of a training conversion unit. In this embodiment, the training hardware description text, which has been parsed by the parser 26, is converted into training graph objects. Here, utilizing... Figure 5 The objects used in the training diagrams are described. Figure 5 This is a diagram illustrating an example of a training diagram object involved in this embodiment. Figure 5 It shows the relationship with Figure 4 The image shows an example of a training graph object corresponding to the hardware description text. Figure 5 The ellipses represent nodes, and the arrows represent edges. The training graph object includes multiple nodes and one or more edges that have been transformed from the descriptions in the training hardware description text. Each of the one or more edges connects one node to another. Each of the multiple nodes corresponds to a hardware instance that implements the function represented by the hardware description text, and each of the one or more edges corresponds to a connection such as wiring connected to the hardware instance. The hardware instance includes, for example, logic gates and registers. Furthermore, when the hardware description text is described using a unified modeling language, the hardware instance includes units such as a CPU (Central Processing Unit).

[0037] Multiple nodes include one or more first nodes embedded with location description information, which represents the position in the training hardware description text corresponding to the node. Each of the one or more first nodes is associated with a description in the training hardware description text indicated by the location description information. In this embodiment, the first node is embedded with a line number Ln of the training hardware description text, which serves as the location description information. Figure 5 In the example shown, nodes N11 to N23 correspond to the first nodes, and the numbers following the @ symbol in each node correspond to the row number Ln. Furthermore, more than one first node includes a second node corresponding to the operator. Additionally, the first nodes include nodes such as N22, which perform sequential operations. Figure 5 In the example shown, nodes N12 and N14 correspond to the second nodes. In this embodiment, each of the more than one first edge has an amount of information transmitted as a feature quantity by the connection corresponding to that first edge. Furthermore, the hardware description text is described in RTL, and the connection corresponding to each of the more than one first edge is a wiring connected to the hardware instance. The wiring has a bus structure, and the amount of information transmitted by the connection corresponding to that first edge includes the bus width of the bus structure.

[0038] Alternatively, each of the first nodes may have a degree of computational complexity in a hardware instance, which corresponds to the hardware instance described in the hardware description text shown in the location information. Here, computational complexity is used, for example, as computational quantity (computational level), which represents the performance of a certain algorithm. As computational quantity, there are concepts such as time computational quantity (processing time) and space computational quantity (memory usage). As a representation of time computational quantity, Big O notation is a representative method. As Big O notation, the processing time in ascending order is as follows: O(1): constant time, O(logN): logarithmic time, O(N): linear time, O(NlogN): quasi-linear / linear logarithmic time, O(N^2): square time, O(N^3), polynomial time, O(k^N): exponential time, and O(N!): factorial time. Furthermore, each of the first nodes may have a number of inputs to that first node, which are used as feature quantities. Furthermore, it is also possible that each of the more than one first side has an amount of information transmitted as a feature by the connection portion corresponding to that first side. It is also possible that each of the more than one first node has a number of nodes through which the input to that first node passes, which is a plurality of nodes. For example, the nodes through which the input to node N21 passes (that is, the serially connected nodes through which the input to node N21 passes) include nodes N30 and N12 (or nodes N11 and N12).

[0039] By embedding metrics associated with the physical properties of semiconductor integrated circuits as features into the neural network, training based on more information becomes possible. Therefore, the accuracy of the neural network's inference can be improved.

[0040] Furthermore, each of the multiple first nodes can possess a disadvantage in computation, such as computational cost and computational complexity, as a feature quantity corresponding to the node corresponding to the operator. Alternatively, each of the multiple first nodes can possess an advantage in computation, such as computational efficiency and power efficiency, as a feature quantity corresponding to the node corresponding to the operator. Accordingly, by embedding metrics associated with the physical metrics of semiconductor integrated circuits into the neural network as feature quantities, training based on more information becomes possible. Therefore, the accuracy of neural network inference can be improved. Furthermore, by possessing the disadvantages of computation as feature quantities, the disadvantages of computation can be used as an indicator of the importance of the design task. Furthermore, by possessing the advantages of computation as feature quantities, the advantages of computation can be used as an indicator of the importance of the trade-offs between the disadvantages of computation.

[0041] The input information storage unit 30 stores the input information input to the training unit 32. The input information storage unit 30 may store, for example, library information, which includes information such as the constraints of the training semiconductor integrated circuit and the structural information of the constituent elements included in the training semiconductor integrated circuit. For example, if the training hardware description text is described using a unified modeling language, the library information may also include the structural information of each unit included as a constituent element, and integrated circuit information. Furthermore, the input information storage unit 30 is not a necessary constituent element.

[0042] The training unit 32 is a processing unit that takes the training graph object converted by the conversion unit 28 as input and the expected value of the physical metric derived by the derivation unit 38 as training data to train the neural network. The training unit 32 trains the neural network represented by the GAT (Graph Attention Networks) method. The GAT method refers to a method that uses weights for features to represent the contribution of each edge in the graph object to inference (see Non-Patent Literature 1, etc.). These weights are called attention coefficients. The attention coefficient e is given for the edge connecting node i and node j (i.e., the edge connecting node i and node j). ij , as defined below.

[0043] [Mathematical Expression 1]

[0044]

[0045] Here,

[0046] [Mathematical Expression 2]

[0047] as well as

[0048] Let F and F' represent the feature quantities of node i and node j, respectively. Furthermore, F and F' represent the number of feature quantities in each node, and W represents the weight matrix.

[0049] Regarding the attention coefficient e ij Normalized attention coefficient α ij , as defined below.

[0050] [Mathematical Expression 3]

[0051]

[0052] Here, N i This represents the set of indices of nodes adjacent to node i in the training graph object.

[0053] When the normalized attention coefficient α between node i and node j is used ij When this happens, the mapping coefficient m representing the importance of node i will be... i The following definition defines node i and its adjacent node N as follows: i Normalized attention coefficient α ij The average value.

[0054] [Mathematical Expression 4]

[0055]

[0056] In preparation section 20, by training a neural network, a neural network capable of predicting attention coefficients that indicate the importance of each edge can be obtained. Therefore, by mapping coefficient m... i This allows for the prediction of the importance of each node. As mentioned above, since the description location information of the training hardware description text is embedded in each node, it is possible to establish a correlation between the description location of the hardware description text and its importance. In other words, it is possible to predict the importance of nodes embedded in nodes with high importance (i.e., mapping coefficient m). i The description location information of the large node indicates the description location prediction of the hardware description text, which is the part to be modified when improving the hardware description text (in other words, the feedback object part).

[0057] In addition, the training unit 32 can input not only training graph objects, but also other input information such as constraints and library information from the input information storage unit 30.

[0058] The logic synthesis unit 34 is a processing unit that creates a gate-level netlist based on the training hardware description text. In this embodiment, the logic synthesis unit 34 creates a gate-level netlist by performing logic synthesis on the hardware description text of the RTL description stored in the RTL storage unit 24.

[0059] The layout unit 36 ​​is a processing unit that creates layout data for a semiconductor integrated circuit based on a gate-level netlist created by the logic synthesis unit 34. The layout data shows the layout of each logic gate, each wiring, etc., included in the semiconductor integrated circuit.

[0060] The correlation determination unit 40 is a processing unit that determines the correlation between each description in the training hardware description text and each logic gate included in the gate-level netlist created by the logic synthesis unit 34. For example, the correlation determination unit 40 determines the correlation by using the following case: the identifier strings assigned to each logic gate included in the gate-level netlist originate from strings indicating variables described in the training hardware description text (and the hardware description text described in RTL). Specifically, for each string included in each description of the training hardware description text and each identifier string of each logic gate included in the gate-level netlist, a Locality Sensitive Hash (LSH) function is used to convert them into features, and the correlation of each feature is calculated. Based on this, the expected value of the correlation between each description in the training hardware description text and each logic gate included in the gate-level netlist can be calculated.

[0061] The derivation unit 38 is a processing unit that derives expected values ​​of physical metrics based on the layout data of the training semiconductor integrated circuit. As expected values ​​of physical metrics, the derivation unit 38 derives, for example, the wiring congestion level and power density per unit area. In this embodiment, the derivation unit 38 calculates heatmap expected values ​​showing the importance of each description in the training hardware description text based on the expected values ​​of physical metrics and the expected values ​​of relevance obtained by the relevance determination unit 40.

[0062] Figure 1 The estimation unit 60 shown is a processing unit that uses a trained neural network prepared by the preparation unit 20 to estimate a portion of the hardware description text as a significant part that has a large impact on the semiconductor integrated circuit. For example... Figure 3 As shown, the estimation unit 60 includes a description text storage unit 62, a parser 66, a conversion unit 68, a neural network 72, an extraction unit 78, and a heatmap storage unit 70.

[0063] The description text storage unit 62 stores hardware description text that describes the semiconductor integrated circuit that is the design target. The hardware description text stored in the description text storage unit 62 is the same as that in the description text storage unit 22 of the preparation unit 20. Figure 4The code shown is written in a hardware description language. Hardware description text can be described in RTL, behavioral level, or unified modeling language, for example.

[0064] Parser 66 is a processing unit that performs syntax parsing on the hardware description text stored in the description text storage unit 62. Parser 66 has the same configuration as parser 26 in preparation unit 20. Alternatively, parser 26 can also serve as parser 66.

[0065] The conversion unit 68 is a processing unit that converts hardware description text into a graph object in CDFG format, and has the same configuration as the conversion unit 28 of the preparation unit 20. Alternatively, the conversion unit 28 can also function as the conversion unit 68. The graph object has the same structure as the training graph object converted by the conversion unit 28 of the preparation unit 20. The graph object has multiple nodes and one or more edges that have converted the descriptions in the hardware description text. Each of the multiple nodes corresponds to a hardware instance that implements the function represented by the hardware description text, and each of the one or more edges corresponds to a connection such as a signal line connected to the hardware instance. In this embodiment, each of the one or more edges has a amount of information transmitted as a feature quantity by the connection corresponding to that edge. Furthermore, the hardware description text is described in RTL, and the connection corresponding to each of the one or more edges is a wiring connected to the hardware instance. The wiring has a bus structure, and the amount of information transmitted by the connection corresponding to that edge includes the bus width of the bus structure. For example, for... Figure 5 The amount of information transmitted by the edge connecting nodes N30 and N12, and the edge connecting nodes N11 and N12 in the graph shown can be 8 bits. In this case, the amount of information transmitted by the edge connecting nodes N12 and N21 can also be 16 bits.

[0066] Multiple nodes include one or more first nodes embedded with location description information representing a position in the hardware description text. Each of the first nodes is associated with a description in the hardware description text indicated by the location description information. The first nodes include second nodes corresponding to operators. The location description information of the second nodes includes a first line number, which is the line number in the hardware description text describing the operator. The second node has the first line number as a feature. Alternatively, the second node may also have a second line number as a feature, which is the line number in the hardware description text defining variables referenced by the operator. Accordingly, the line numbers in the hardware description text describing variables referenced by the operator can be easily extracted.

[0067] Neural network 72 is a trained neural network represented using the GAT method. Neural network 72 is a neural network trained in preparation unit 20. Neural network 72 is input to a graph object that has been transformed in conversion unit 68, and infers the inference physical metrics of the semiconductor integrated circuit. As described above, the trained neural network 72 in preparation unit 20 includes attention coefficients as weights, which represent the degree of influence of each of the more than one edge on the inference physical metrics.

[0068] Inference physical metrics may include, for example, results derived from inferences about wiring congestion levels, and inferred as congestion predictions for multiple nodes. These wiring congestion levels indicate the number of wirings present in a unit area of ​​semiconductor integrated circuit layout data derived from hardware description text. Accordingly, wiring congestion levels can be improved by modifying salient portions of the hardware description text based on wiring congestion levels.

[0069] Furthermore, the inferred physical metrics can also include results derived from inferences about power density, and inferred as predicted power density values ​​for each of the multiple nodes. This power density represents the power consumed per unit area in the layout data of a semiconductor integrated circuit, which is derived from a hardware description text. Accordingly, by modifying significant portions of the hardware description text based on the power density, power density can be improved.

[0070] Furthermore, the physical metrics include the results of inference on the signal transmission times of multiple signal paths included in the layout data of the semiconductor integrated circuit, and are inferred as the predicted signal transmission time values ​​of each of the multiple signal paths, which includes multiple nodes. The layout data of the semiconductor integrated circuit is derived from the hardware description text. Based on this, the critical path can be inferred, which is the signal path whose signal arrives at the latest timing among the signal arrival timings from multiple nodes to one node.

[0071] Extraction unit 78 is a processing unit that extracts salient parts of hardware description text based on inference physical metrics inferred by neural network 72. Extraction unit 78 determines one or more first edges among one or more edges included in a graph object based on attention coefficients, and extracts a portion of the hardware description text as salient parts based on information indicating the description positions of the first nodes corresponding to the one or more first edges.

[0072] The heatmap storage unit 70 stores heatmaps of prominent portions of the hardware description text extracted by the extraction unit 78. For example, a heatmap may show hardware description text with high importance, represented by different colors for prominent portions of the text according to their importance, or by assigning markers to highly important descriptions.

[0073] [2. Hardware Configuration]

[0074] Next, using Figure 6 The hardware configuration of the semiconductor integrated circuit design support device 10 according to this embodiment will be described. Figure 6 This is a diagram illustrating an example of the hardware configuration of a computer 1000 that implements the functions of a semiconductor integrated circuit design support device 10 via software, as described in this embodiment.

[0075] like Figure 6 As shown, the computer 1000 includes an input device 1001, an output device 1002, a CPU 1003, an internal storage device 1004, RAM 1005, a reading device 1007, a transceiver device 1008, and a bus 1009. The input device 1001, output device 1002, CPU 1003, internal storage device 1004, RAM 1005, reading device 1007, and transceiver device 1008 are connected via the bus 1009.

[0076] The input device 1001 is a user interface device such as an input button, touchpad, or touchscreen display, used to receive user operations. Alternatively, the input device 1001 may also be configured to receive not only touch operations but also voice operations, remote operations such as those from a remote control, etc.

[0077] The output device 1002 is a device that outputs signals from the computer 1000. In addition to signal output terminals, it can also be a display, speaker, or other device that serves as a user interface.

[0078] The built-in storage device 1004 is a flash memory or the like. Furthermore, in addition to the data stored in each storage unit of the semiconductor integrated circuit design support device 10, the built-in storage device 1004 can also pre-store at least one of the programs used to implement the functions of the semiconductor integrated circuit design support device 10 and the applications constructed using the functions of the semiconductor integrated circuit design support device 10.

[0079] RAM1005 is Random Access Memory, used to store data and other information needed when executing programs or applications.

[0080] The reading device 1007 reads information from a recording medium such as a USB (Universal Serial Bus) memory. The reading device 1007 reads a program or application from a recording medium containing such a program or application, and stores it in the built-in storage device 1004.

[0081] The transceiver 1008 is a communication circuit used for communication via wireless or wired means. For example, the transceiver 1008 communicates with a server device connected to a network, downloads such programs or applications from the server device, and stores them in the built-in storage device 1004.

[0082] CPU 1003 is a central processing unit that copies programs, applications, etc. stored in the built-in storage device 1004 to RAM 1005, and sequentially reads and executes the instructions included in the copied programs, applications, etc. from RAM 1005.

[0083] [3. Semiconductor Integrated Circuit Design Support Methods]

[0084] use Figures 7 to 9 The semiconductor integrated circuit design support method involved in this embodiment will be described. Figure 7 This is a flowchart illustrating the process of the semiconductor integrated circuit design support method according to this embodiment. Figure 8 This is a flowchart illustrating the preparation steps of the semiconductor integrated circuit design support method according to this embodiment. Figure 9 This is a flowchart illustrating the derivation steps of the semiconductor integrated circuit design support method involved in this embodiment.

[0085] The semiconductor integrated circuit design support method involved in this embodiment provides support by estimating the physical metrics of the semiconductor integrated circuit designed based on the hardware description text, and by extracting the significant parts of the hardware description text that have a large impact on the physical metrics, thereby supporting feedback to the hardware description text.

[0086] like Figure 7 As shown, the first step is to prepare the trained neural network (preparation step S10). Figure 8 As shown, in preparation step S10, the expected value of the physical metric of the training semiconductor integrated circuit designed based on the training hardware description text is derived. The training hardware description text is described in a hardware description language (physical metric expected value derivation step S110).

[0087] like Figure 9As shown, in the step S110 of deriving the expected value of the physical metric, a hardware description text is created using an RTL corresponding to the training hardware description text (RTL creation step S112).

[0088] Next, a gate-level netlist is created by performing logic synthesis based on the hardware description text described in RTL (logic synthesis step S114).

[0089] Next, layout data is created based on the gate-level netlist (layout step S116). Furthermore, based on the training hardware description text and the gate-level netlist, the correlation between each description in the training hardware description text and each logic gate included in the gate-level netlist created by the logic synthesis unit 34 is determined (correlation determination step S118).

[0090] Next, based on the layout data of the training semiconductor integrated circuit produced in layout step S116, expected values ​​of physical metrics are derived (derivation step S120). In the derivation step S120 of this embodiment, based on the expected values ​​of physical metrics and the expected values ​​of relevance obtained by the relevance determination unit 40, expected values ​​of a heatmap showing the importance of each description in the training hardware description text are obtained. As described above, expected values ​​of physical metrics and expected values ​​of heatmaps can be derived. Furthermore, in Figure 8 In the flowchart shown, although the physical metric expectation value derivation step S110 is executed at the beginning of the preparation step S10, the order in which the physical metric expectation value derivation step S110 is executed is not limited to this. The physical metric expectation value derivation step S110 can also be executed before the training step S160.

[0091] Next, as Figure 8 As shown, parser 26 is used to perform syntax parsing of the training hardware description text (training syntax parsing step S130).

[0092] Next, the training hardware description text is converted into a training graph object in CDFG format (training conversion step S140).

[0093] Next, the training graph object is input into a neural network represented using the GAT method (training data input step S150). The training graph object includes multiple nodes and one or more edges that have been transformed from descriptions in the training hardware description text. The multiple nodes include one or more first nodes that have embedded description location information representing the position in the training hardware description text. Each of the one or more first nodes is associated with a description in the training hardware description text shown by the description location information. The neural network represented using the GAT method includes attention coefficients as weights, which represent the degree of influence of one or more edges of the training graph object on the inference physical metric. In the training data input step S150, the training graph object may also be input into the neural network along with library information, which includes information such as the constraints of the training semiconductor integrated circuit and the structural information of the constituent elements included in the training semiconductor integrated circuit.

[0094] Next, the training graph object is used as input, and the expected value of the physical metric is used as training data to train the neural network (training step S160). Then, if there are other training graph objects, the process returns to the expected value derivation step S110 and repeats the above steps. In this way, a trained neural network can be prepared. Furthermore, in Figure 7 In the flowchart shown, although preparation step S10 is executed at the beginning, the order in which preparation steps S10 are executed is not limited to this. Preparation step S10 can also be executed before reasoning step S50.

[0095] Next, as Figure 7 As shown, the hardware description text is parsed (syntax parsing step S20).

[0096] Next, the hardware description text is converted into a CDFG format diagram object (conversion step S30).

[0097] Next, the graph object transformed in transformation step S30 is input into a neural network represented using the GAT method (data input step S40). In data input step S40, the graph object may also be input into the neural network along with library information, which includes information such as the constraints of the semiconductor integrated circuit and the structural information of the constituent elements included in the semiconductor integrated circuit.

[0098] Next, the trained neural network is used to infer the physical metrics of the semiconductor integrated circuit (inference step S50).

[0099] Next, based on the inference physical metrics, the salient portions of the hardware description text are extracted (extraction step S60). In extraction step S60, one or more first edges from one or more edges are determined based on the attention coefficient, which represents the degree of influence on the inference physical metrics. Furthermore, based on the description location information of the first nodes corresponding to the one or more first edges, a portion of the hardware description text is extracted as the salient portion. In this embodiment, a heatmap is created that shows the hardware description text with high importance descriptions.

[0100] As described above, in the semiconductor integrated circuit design support method of this embodiment, it is possible to estimate the significant parts of the hardware description text that have a large impact on physical metrics. If there are parts in the inference physical metrics that should be modified, the inference physical metrics can be improved by modifying the significant parts.

[0101] [4. Effects, etc.]

[0102] The semiconductor integrated circuit design support method involved in this embodiment and its effects are explained.

[0103] The semiconductor integrated circuit design support method of Method 1 involved in this embodiment includes the following steps: a conversion step S30, converting the hardware description text describing the semiconductor integrated circuit using a hardware description language into a graph object in CDFG format; an inference step S50, inputting the graph object into a trained neural network represented by the GAT method, and inferring the inference physical metrics of the semiconductor integrated circuit; and an extraction step S60, extracting the salient parts of the hardware description text based on the inference physical metrics. The graph object includes multiple nodes and one or more edges that have been converted for each description in the hardware description text. The multiple nodes include one or more first nodes with embedded description location information, which indicates the position in the hardware description text. Each of the one or more first nodes is associated with a description in the hardware description text indicated by the description location information. The neural network includes attention coefficients as weights, which indicate the degree of influence of each of the one or more edges on the inference physical metrics. In the extraction step, one or more first edges are determined based on the attention coefficients, and a portion of the hardware description text is extracted as a salient part based on the description location information of the first nodes corresponding to the one or more first edges.

[0104] Accordingly, by inference using a trained neural network represented by the GAT method, the physical metrics of semiconductor integrated circuits can be estimated with high accuracy. Furthermore, in this embodiment, salient portions of the hardware description text can be extracted based on the description location information embedded in the nodes connected to edges with large attention coefficients in the graph object. This allows for the identification of description locations in the hardware description text that significantly impact the physical metrics. Thus, since the physical metrics of semiconductor integrated circuits can be estimated from the hardware description text, and the salient portions of the hardware description text that significantly impact the physical metrics can be identified, the physical metrics of semiconductor integrated circuits can be improved by modifying the hardware description text at the initial stage of semiconductor integrated circuit design.

[0105] The semiconductor integrated circuit design support method of Method 2 involved in this embodiment is based on the semiconductor integrated circuit design support method described in Method 1. One or more first nodes include second nodes corresponding to operators. The description location information of the second node includes a first line number, which is the line number in the hardware description text describing the operator. The second node has a first line number as a feature quantity.

[0106] Therefore, since the significant parts of the hardware description text can be extracted based on the line numbers of the hardware description text, the parts of the hardware description text that need to be modified can be easily identified.

[0107] The semiconductor integrated circuit design support method of Method 3 involved in this embodiment is based on the semiconductor integrated circuit design support method described in Method 2. One or more first sides include a second side connected to a second node, and the second side has a first row number as a feature quantity.

[0108] Therefore, since the attention coefficients, which serve as weights on the second side, can be associated with the line numbers of the hardware description text, the salient parts of the hardware description text can be easily extracted.

[0109] The semiconductor integrated circuit design support method of method 4 involved in this embodiment is based on the semiconductor integrated circuit design support method described in method 2 or 3. The second node has a second row number as a feature quantity. The second row number is the row number in the hardware description text where variables are defined. The variables are variables referenced by operators.

[0110] Therefore, it is easy to extract the line numbers in the hardware description text that describes variables referenced by operators.

[0111] The semiconductor integrated circuit design support method of method 5 in this embodiment is based on any one of the semiconductor integrated circuit design support methods of methods 1 to 4. Each of the multiple nodes corresponds to a hardware instance that implements the function represented by hardware description text, and each of the more than one edge corresponds to a connection part connected to the hardware instance.

[0112] The semiconductor integrated circuit design support method of Method 6 involved in this embodiment is based on the semiconductor integrated circuit design support method described in Method 5. Each of the more than one first node has a degree of computational complexity in a hardware instance as a feature quantity. The hardware instance is a hardware instance corresponding to the description in the hardware description text shown in the description location information.

[0113] By embedding the complexity of computations—which are physical metrics associated with semiconductor integrated circuits—as features into the neural network, training based on more information becomes possible. Therefore, the accuracy of the neural network's inference can be improved.

[0114] The semiconductor integrated circuit design support method of mode 7 in this embodiment is based on any one of the semiconductor integrated circuit design support methods of modes 1 to 6, wherein one or more first nodes each have a number of inputs to the first node as a feature quantity.

[0115] By embedding the number of inputs to nodes—a metric associated with physical indicators of semiconductor integrated circuits—as a feature into the neural network, training based on more information becomes possible. Therefore, the accuracy of the neural network's inference can be improved.

[0116] The semiconductor integrated circuit design support method of Method 8 in this embodiment is based on the semiconductor integrated circuit design support method of Method 5, wherein one or more first sides each have an amount of information transmitted by the connection portion corresponding to the first side as a feature quantity.

[0117] By embedding the amount of information transmitted by the interconnects—which is a metric associated with the physical properties of semiconductor integrated circuits—as a feature into the neural network, training based on more information becomes possible. Therefore, the accuracy of the neural network's inference can be improved.

[0118] The semiconductor integrated circuit design support method of Method 9 involved in this embodiment is based on the semiconductor integrated circuit design support method described in Method 8. The hardware description text is described in RTL. The connection part corresponding to one or more first sides is a wiring connected to the hardware instance. The wiring has a bus structure and the information includes the bus width of the bus structure.

[0119] By embedding the bus width, a metric associated with the physical properties of semiconductor integrated circuits, as a feature into the neural network, training based on more information becomes possible. Therefore, the accuracy of the neural network's inference can be improved.

[0120] The semiconductor integrated circuit design support method of Method 10 involved in this embodiment is based on any one of the semiconductor integrated circuit design support methods of Methods 1 to 8, and the hardware description text is described in RTL.

[0121] The semiconductor integrated circuit design support method of method 11 involved in this embodiment is based on any one of the semiconductor integrated circuit design support methods of methods 1 to 8, and the hardware description text is described at the behavior level.

[0122] The semiconductor integrated circuit design support method of method 12 involved in this embodiment is based on any one of the semiconductor integrated circuit design support methods of methods 1 to 8, and the hardware description text is described in a unified modeling language.

[0123] The semiconductor integrated circuit design support method of mode 13 involved in this embodiment is based on any one of the semiconductor integrated circuit design support methods of modes 1 to 10, wherein one or more first nodes each have the number of nodes through which the input to the first node passes as a feature quantity.

[0124] By embedding the number of nodes—which is a metric associated with physical indicators of semiconductor integrated circuits—as a feature into the neural network, training based on more information becomes possible. Therefore, the accuracy of the neural network's inference can be improved.

[0125] The semiconductor integrated circuit design support method of method 14 involved in this embodiment is based on any one of the semiconductor integrated circuit design support methods of methods 1 to 13. The inferred physical metric includes the result obtained by inferring the degree of wiring congestion and is inferred as the congestion prediction value of each of the multiple nodes. The degree of wiring congestion indicates the number of wirings present in a unit area in the layout data of the semiconductor integrated circuit, which is derived from the hardware description text.

[0126] Accordingly, by modifying the salient parts of the hardware description text according to the degree of cabling congestion, it is possible to improve the cabling congestion level.

[0127] The semiconductor integrated circuit design support method of method 15 involved in this embodiment is based on any one of the semiconductor integrated circuit design support methods of methods 1 to 14. The inferred physical metric includes the result obtained by inferring power density and is inferred as the power density prediction value of each of the multiple nodes. The power density shows the power consumed per unit area in the layout data of the semiconductor integrated circuit, which is derived from the hardware description text.

[0128] Accordingly, power density can be improved by modifying the salient parts of the hardware description text based on power density.

[0129] The semiconductor integrated circuit design support method of method 16 involved in this embodiment is based on any one of the semiconductor integrated circuit design support methods of methods 1 to 15. The physical metric includes the result obtained by inferring the signal transmission time in multiple signal paths included in the layout data of the semiconductor integrated circuit, and is inferred as the predicted value of the signal transmission time of each of the multiple signal paths including multiple nodes. The layout data of the semiconductor integrated circuit is derived from the hardware description text.

[0130] Based on this, the critical path can be deduced, which is the signal path from multiple nodes to one node where the signal arrives at the latest timing.

[0131] The semiconductor integrated circuit design support method of embodiment 17 is based on any one of the semiconductor integrated circuit design support methods of embodiments 1 to 16. The semiconductor integrated circuit design support method includes a preparation step S10 for preparing a trained neural network. The preparation step S10 includes: a training conversion step S140, which converts a training hardware description text describing a training semiconductor integrated circuit into a training graph object in CDFG format; a logic synthesis step S114, which creates a gate-level netlist based on the training hardware description text; a placement step S116, which creates placement data based on the gate-level netlist; an export step S120, which exports physical metric expected values ​​from the placement data; and a training step S160, which trains the neural network by taking the training graph object as input and the physical metric expected values ​​as training data.

[0132] Therefore, since neural networks can be trained based on high-precision training data, neural networks capable of high-precision inference can be obtained.

[0133] (variant examples, etc.)

[0134] While the semiconductor integrated circuit design support methods and the like described above are based on various embodiments, this disclosure is not limited to these embodiments. Various modifications conceivable to those skilled in the art, implemented in each embodiment, or other configurations combining some of the constituent elements of each embodiment, are also included within the scope of this disclosure without departing from its spirit.

[0135] Furthermore, the methods described below are also included within the scope of one or more methods disclosed herein.

[0136] (1) A portion of the constituent elements of the semiconductor integrated circuit design support device 10 described above may also be a computer system consisting of a microprocessor, ROM, RAM, hard disk drive, display device, keyboard, mouse, etc. A computer program is stored in the RAM or hard disk drive. The microprocessor performs its functions according to the computer program. This computer program, in order to achieve the specified function, is composed of multiple command codes that issue instructions to the computer.

[0137] (2) A portion of the constituent elements of the semiconductor integrated circuit design support device 10 described above is constituted by a system LSI (Large Scale Integration). A system LSI is a multi-functional LSI in which multiple components are integrated and manufactured on a single chip; specifically, it is a computer system comprising a microprocessor, ROM, RAM, etc. The RAM stores a computer program. The microprocessor operates according to the computer program, thereby enabling the system LSI to perform its functions.

[0138] (3) A portion of the constituent elements of the semiconductor integrated circuit design support device 10 described above may be composed of an IC card or a single module that can be mounted and detached from various devices. The IC card or module is a computer system composed of a microprocessor, ROM, RAM, etc. The IC card or module may include the aforementioned multi-functional LSI. The IC card or module performs its functions by operating according to a computer program via a microprocessor. The IC card or module may also be tamper-proof.

[0139] (4) Furthermore, a component of the aforementioned semiconductor integrated circuit design support device 10 can also be implemented as a computer-readable recording medium on which the computer program or the digital signal is recorded. Examples of computer-readable recording media include floppy disks, hard disks, CD-ROMs, MOs, DVDs, DVD-ROMs, DVD-RAMs, BDs (Blu-ray Discs), semiconductor memories, etc. It can also be implemented as the digital signal recorded on these recording media.

[0140] Furthermore, as part of the constituent elements of the aforementioned semiconductor integrated circuit design support device 10, the computer program or the digital signal can be transmitted via electronic communication lines, wireless or wired communication lines, networks such as the Internet, data playback, etc.

[0141] (5) This disclosure can also be used as the methods shown above. Furthermore, it can be implemented by a computer program that executes these methods, or by digital signals constituted by said computer program. Further, this disclosure can also be implemented as a non-transitory computer-readable recording medium such as a CD-ROM that records the computer program.

[0142] (6) Furthermore, this disclosure may be a computer system having a microprocessor and a memory, wherein the memory stores the aforementioned computer program, and the microprocessor operates according to the computer program.

[0143] (7) Furthermore, the program or the digital signal can be transmitted by recording it onto the recording medium or by transmitting it via the network, thereby enabling execution by a separate computer system.

[0144] (8) The above-described embodiments and the above-described variations can also be combined separately.

[0145] Industrial availability

[0146] This disclosure provides a semiconductor integrated circuit design support method that enables the precise determination of the parts of the hardware description text that should be modified at the initial stage of design, and can be used in the design of semiconductor integrated circuits.

[0147] Symbol Explanation

[0148] 10 Semiconductor Integrated Circuit Design Support Devices

[0149] 20. Preparation Department

[0150] 22, 62 Describe the text storage section

[0151] 24 RTL Storage Section

[0152] 26, 66 parsers

[0153] 28, 68 conversion section

[0154] 30 Input Information Storage Unit

[0155] Training Department 32

[0156] 34. Logic Integration Department

[0157] 36 Layout Department

[0158] 38 Export Section

[0159] 40 Relevant Decision-Making Department

[0160] 60 Estimation Department

[0161] 70 Heatmap Storage Department

[0162] 72 Neural Networks

[0163] 78 Extraction Section

[0164] 1000 computers

[0165] 1001 Input Device

[0166] 1002 Output Device

[0167] 1003 CPU

[0168] 1004 built-in storage device

[0169] 1005 RAM

[0170] 1007 Reading Device

[0171] 1008 transceiver

[0172] 1009 bus

[0173] Nodes N11, N12, N13, N14, N15, N16, N17, N18, N19, N20, N21, N22, N23, and N30

Claims

1. A semiconductor integrated circuit design support method, The semiconductor integrated circuit design support method includes the following steps: The conversion step converts the hardware description text of the semiconductor integrated circuit described by the hardware description language into a graph object in CDFG format, where CDFG stands for Control Data Flow Graph. The inference step involves inputting the graph object into a trained neural network represented using the GAT method, and inferring the inference physical metric of the semiconductor integrated circuit, where GAT refers to Graph Attention Networks; and The extraction step involves extracting the salient portions of the hardware description text based on the inference physical metrics. The graph object includes multiple nodes that have transformed the descriptions in the hardware description text and one or more edges. The plurality of nodes includes one or more first nodes embedded with location description information, which indicates the location within the hardware description text. Each of the one or more first nodes is associated with a description in the hardware description text shown in the description location information. The neural network includes attention coefficients as weights, each representing the degree of influence of one or more edges on the inference physical metric. In the extraction step, one or more first edges are determined based on the attention coefficient, and a portion of the hardware description text is extracted as the salient part based on the description location information of the first nodes corresponding to the one or more first edges.

2. The semiconductor integrated circuit design support method as described in claim 1, The one or more first nodes include second nodes corresponding to the operators. The description location information of the second node includes a first line number, which is the line number in the hardware description text that describes the operator. The second node has the first row number as a feature quantity.

3. The semiconductor integrated circuit design support method as described in claim 2, The more than one first edge includes a second edge connected to the second node. The second side has the first row number as a feature quantity.

4. The semiconductor integrated circuit design support method as described in claim 2 or 3, The second node has a second line number as a feature quantity, which is the line number in the hardware description text where variables are defined, and the variables are referenced by the operator.

5. The semiconductor integrated circuit design support method as described in any one of claims 1 to 3, Each of the plurality of nodes corresponds to a hardware instance that implements the function represented by the hardware description text. Each of the one or more edges corresponds to a connection portion connected to the hardware instance.

6. The semiconductor integrated circuit design support method as described in claim 5, Each of the one or more first nodes has a degree of computational complexity in the hardware instance as a feature quantity, and the hardware instance is the hardware instance corresponding to the description in the hardware description text shown in the description location information.

7. The semiconductor integrated circuit design support method as described in any one of claims 1 to 3, Each of the one or more first nodes has a number of inputs to that first node as a feature quantity.

8. The semiconductor integrated circuit design support method as described in claim 5, Each of the more than one first side has an amount of information transmitted by the connection portion corresponding to that first side as a characteristic quantity.

9. The semiconductor integrated circuit design support method as described in claim 8, The hardware description text is written in RTL, which stands for Register Transfer Level. The connection portion corresponding to each of the one or more first sides is a wiring connection to the hardware instance. The wiring has a bus structure. The amount of information includes the bus width of the bus structure.

10. The semiconductor integrated circuit design support method as described in any one of claims 1 to 3, The hardware description text is described in RTL, which stands for Register Transfer Level.

11. The semiconductor integrated circuit design support method as described in any one of claims 1 to 3, The hardware description text is described at the behavior level.

12. The semiconductor integrated circuit design support method as described in any one of claims 1 to 3, The hardware description text is described using the Unified Modeling Language.

13. The semiconductor integrated circuit design support method as described in claim 10, Each of the one or more first nodes has a number of nodes through which the input to that first node is traversed, which is a feature quantity.

14. The semiconductor integrated circuit design support method as described in any one of claims 1 to 3, The inference physical metric includes the result of inference on the degree of wiring congestion, and is inferred as the congestion prediction value of each of the plurality of nodes. The degree of wiring congestion indicates the number of wirings present in a unit area in the layout data of the semiconductor integrated circuit, which is derived from the hardware description text.

15. The semiconductor integrated circuit design support method as described in any one of claims 1 to 3, The inference physical metric includes the result of inference of power density, and is inferred as the power density prediction value of each of the plurality of nodes, the power density indicating the power consumed per unit area in the layout data of the semiconductor integrated circuit, which is derived from the hardware description text.

16. The semiconductor integrated circuit design support method as described in any one of claims 1 to 3, The inference physical metric includes the result of inferring the signal transmission time in multiple signal paths included in the layout data of the semiconductor integrated circuit, and is inferred as the predicted signal transmission time value of each of the multiple signal paths including the multiple nodes, the layout data of the semiconductor integrated circuit being derived from the hardware description text.

17. The semiconductor integrated circuit design support method as described in any one of claims 1 to 3, The semiconductor integrated circuit design support method includes a preparation step for preparing the trained neural network. The preparation steps include: The training conversion step converts the training hardware description text, which describes the training semiconductor integrated circuit, into a training graph object in CDFG format. The logic synthesis step involves creating a gate-level netlist based on the training hardware description text. The layout step involves creating layout data based on the gate-level netlist. The export step involves deriving the expected values ​​of physical metrics from the layout data. as well as The training step involves using the training graph object as input and the expected value of the physical metric as training data to train the neural network.

Images