DSSC device dynamic current sharing performance test system and method based on multi-device parallel connection

Abstract

The invention relates to the technical field of power flow control, and particularly provides a DSSC device dynamic current sharing performance test system and method based on multi-device parallel connection, and the system comprises a valve layer control board, a unit controller, and a plurality of drive boards. The valve layer control panel is used for issuing a test control pulse command to the unit controller; the unit controller is used for generating a driving PWM pulse signal corresponding to the test control pulse command and issuing the driving PWM pulse signal to a driving board; the driving board is used for converting the received driving PWM pulse signal into an electric PWM signal for driving a power device, and sending the electric PWM signal to the power device in the half-bridge unit controlled by the driving board; wherein a control object of one driving board is a power device in one half-bridge unit. According to the technical scheme provided by the invention, the dynamic current sharing property of a plurality of power devices which are connected in parallel can be verified by a simple and efficient method under the condition that the sub-module outputs a large current.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power flow control, in particular to a DSSC device dynamic current sharing test system and method based on multi-device parallel connection. BACKGROUND

[0002] Power flow control technology is directly related to the safe and efficient operation of the power grid. Among the 13 global blackouts since the 21st century, 12 were related to power flow out of control. The construction investment for improving power flow distribution and increasing power flow transmission capacity is increasing. Traditional power flow control mainly relies on power output adjustment and load transfer. The speed of power flow control is slow and the effect is poor. At present, with the large-scale development of new energy and the increase of volatile loads, the difficulty of power flow control is further increased, which limits the power supply capacity of the power grid, increases the risk of power flow exceeding and out of control. Therefore, it is urgent to develop fast and accurate power flow control technology to improve the efficiency and benefit of the power grid and ensure the safety of the power grid.

[0003] As a new type of distributed power flow controller in power flow control technology, the direct series distributed static synchronous series compensator (DSSC) has been successfully demonstrated in power transmission systems. However, the device voltage level is low, the capacity of a single sub-module is small, and it is easily disturbed by lightning during operation, which makes it difficult to meet the needs of higher voltage level power transmission systems, and the reliability of the device needs to be further improved.

[0004] In view of the problems of higher voltage level of power transmission system, larger capacity of sub-module and easy disturbance by lightning current, the DSSC adopts the latest multi-high-voltage power device parallel topology scheme. However, the traditional double-pulse test method mainly uses inductance as energy load, and adjusts the input voltage and pulse width to estimate the collector current size of the power device. Only the dynamic characteristics of a single power device in the DSSC can be verified. Therefore, a DSSC device dynamic current sharing test system based on multi-device parallel connection is needed. SUMMARY

[0005] In order to overcome the above defects, the present application provides a DSSC device dynamic current sharing test system and method based on multi-device parallel connection.

[0006] In the first aspect, a DSSC device dynamic current sharing test system based on multi-device parallel connection is provided, which comprises a valve layer control board, a unit controller and a plurality of drive boards.

[0007] The valve layer control board is used to issue test control pulse commands to the unit controller.

[0008] The unit controller is configured to generate a driving PWM pulse signal corresponding to the test control pulse command and send the driving PWM pulse signal to a driving board;

[0009] The driving board is configured to convert the received driving PWM pulse signal into an electrical PWM signal for driving a power device and send the electrical PWM signal to the power device in a half-bridge unit controlled by the driving board.

[0010] The control object of one driving board is the power device in one half-bridge unit.

[0011] Preferably, the system comprises a DSSC based on parallel connection of multiple devices, which is composed of a left half-bridge module and a right half-bridge module in parallel.

[0012] Further, the DSSC based on parallel connection of multiple devices has a DC bus connected with a DC bus capacitor and a high-voltage adjustable DC source.

[0013] Further, the left half-bridge module or the right half-bridge module is composed of multiple half-bridge units in parallel.

[0014] Further, the half-bridge unit is composed of multiple half-bridge structures in parallel, and the AC output ends of the half-bridge structures are short-circuited through a laminated busbar to form the AC output end of the half-bridge unit.

[0015] Further, the AC output ends of the half-bridge units of the left half-bridge module or the right half-bridge module are short-circuited after being filtered by a conjugate inductor to form the AC output end of the left half-bridge module or the right half-bridge module.

[0016] Further, the AC output ends of the left half-bridge module and the right half-bridge module are short-circuited through a copper bar, and the negative pole of an adjustable resistance box and a DC bus capacitor is connected in sequence through a soft wire in the middle of the copper bar.

[0017] In a second aspect, a dynamic current sharing test method for a DSSC based on parallel connection of multiple devices is provided, which comprises:

[0018] Setting an adjustable high-voltage power supply output voltage;

[0019] Starting a current sharing test process;

[0020] Testing the dynamic current sharing of the DSSC based on parallel connection of multiple devices based on current data of the collector side of the upper tube power device unit in the DSSC based on parallel connection of multiple devices and the series bus side between the adjustable resistance and the negative pole of the DC bus capacitor.

[0021] Preferably, the adjustable high-voltage power supply output voltage is set in a range of 500V-4000V.

[0022] Preferably, the current sharing test procedure comprises:

[0023] starting the adjustable high-voltage power supply;

[0024] after the capacitor is charged, issuing a pulse instruction through the host computer;

[0025] generating and issuing an electric PWM signal for driving the power device through the valve layer control panel, the unit controller and the plurality of drive boards;

[0026] collecting current data between the collector side of the upper tube power device unit in the measured DSSC based on parallel connection of multiple devices, the adjustable resistor and the negative pole of the DC bus capacitor;

[0027] turning off the adjustable high-voltage power supply.

[0028] Further, the preset resistance value of the adjustable resistor box is 1Ω.

[0029] Preferably, the current data between the collector side of the upper tube power device unit in the measured DSSC based on parallel connection of multiple devices and the series bus side between the adjustable resistor and the negative pole of the DC bus capacitor test the dynamic current sharing of the measured DSSC based on parallel connection of multiple devices, comprising:

[0030] if the sum of the current of the collector side of all upper tube power device units in the measured DSSC based on parallel connection of multiple devices is consistent with the current of the series bus side between the adjustable resistor and the negative pole of the DC bus capacitor, and the current waveform and current peak of the collector side of each upper tube power device unit in the measured DSSC based on parallel connection of multiple devices differ within ±5%, then the measured DSSC based on parallel connection of multiple devices passes the dynamic current sharing test, otherwise, the measured DSSC based on parallel connection of multiple devices fails the dynamic current sharing test.

[0031] In a third aspect, a computer device is provided, comprising: one or more processors;

[0032] the processor is configured to execute one or more programs;

[0033] when the one or more programs are executed by the one or more processors, the dynamic current sharing test method for the DSSC device based on parallel connection of multiple devices is implemented.

[0034] In a fourth aspect, a computer readable storage medium is provided, having a computer program stored thereon, and when the computer program is executed, the dynamic current sharing test method for the DSSC device based on parallel connection of multiple devices is implemented.

[0035] The one or more technical solutions of the present application have at least one or more of the following advantages:

[0036] The application provides a DSSC device dynamic current sharing test system and method based on parallel connection of multiple devices, comprising a valve layer control board, a unit controller and multiple drive boards; the valve layer control board is used to issue a test control pulse command to the unit controller; the unit controller is used to generate a drive PWM pulse signal corresponding to the test control pulse command and issue it to the drive board; the drive board is used to convert the received drive PWM pulse signal into an electrical PWM signal for driving a power device and issue the electrical PWM signal to the power device in a half-bridge unit controlled by the drive board; wherein the control object of one drive board is the power device in one half-bridge unit. The technical scheme provided by the application can verify the dynamic current sharing of multiple power devices in parallel connection under the condition of large current output of a sub-module in a simplified and efficient manner. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 FIG. 1 is a main structure schematic diagram of the DSSC device dynamic current sharing test system based on parallel connection of multiple devices according to the embodiment of the application;

[0038] Figure 2 FIG. 2 is a peripheral accessory structure schematic diagram of the DSSC device dynamic current sharing test system based on parallel connection of multiple devices according to the embodiment of the application;

[0039] Figure 3 FIG. 3 is a specific structure block diagram of the DSSC device dynamic current sharing test system based on parallel connection of multiple devices according to the embodiment of the application. DETAILED DESCRIPTION

[0040] The specific implementation of the application will be further described in detail below with reference to the accompanying drawings.

[0041] To make the purpose, technical scheme and advantages of the embodiments of the application clearer, the technical scheme in the embodiments of the application will be described clearly and completely below with reference to the drawings of the embodiments of the application. Obviously, the described embodiments are some of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the application.

[0042] As disclosed in the background, the power flow control technology is directly related to the safe and efficient operation of the power grid, and 12 of the 13 global blackouts in the 21st century are related to power flow out of control; the construction investment for improving power flow distribution and increasing power flow transmission capacity is increasing. Traditional power flow control mainly relies on power output adjustment, load transfer and other means, and the power flow control is slow and the effect is poor. At present, with the large-scale development of new energy and the increase of fluctuating loads, the difficulty of power flow control is further increased, which limits the power supply capacity of the power grid, increases the risk of power flow exceeding and out of control, therefore, it is urgent to develop fast and accurate power flow control technology to improve the efficiency and benefit of the power grid and ensure the safety of the power grid.

[0043] As a new type of distributed power flow controller in power flow control technology, DSSC has been successfully demonstrated in power transmission systems, but the device voltage level is low, the capacity of a single sub-module is small, and it is easy to be disturbed by lightning during operation, which cannot meet the demand of higher voltage level of power transmission system, and the reliability of the device needs to be further improved.

[0044] In view of the problems of higher voltage level of power transmission system, larger capacity of sub-module and easy to be disturbed by lightning current, DSSC adopts the latest parallel topology scheme of multiple high-voltage power devices, however, the traditional double pulse test method mainly uses inductance as energy load, and adjusts the input voltage and pulse width to estimate the collector current size of the power device, which can only verify the dynamic characteristics of a single power device in DSSC, therefore, a DSSC device dynamic current sharing test system based on multiple device parallel is needed.

[0045] In order to improve the above problems, the present application provides a DSSC device dynamic current sharing test system and method based on multiple device parallel, which comprises: a valve layer control board, a unit controller and a plurality of drive boards; the valve layer control board is used to issue a test control pulse command to the unit controller; the unit controller is used to generate a drive PWM pulse signal corresponding to the test control pulse command and issue it to the drive board; the drive board is used to convert the received drive PWM pulse signal into an electrical PWM signal for driving the power device, and issue the electrical PWM signal to the power device in the half-bridge unit controlled by the drive board; wherein the control object of one drive board is the power device in one half-bridge unit. The technical scheme provided by the present application can verify the dynamic current sharing of multiple power devices in parallel under the condition of large current output of the sub-module in a simplified and efficient way, specifically:

[0046] (1) The application uses a resistor as a test load. Compared with a traditional load inductor, the resistor error can be controlled within 0.1% to 1%, and the manufacturing cost is low and easy to obtain. The inductance value changes greatly in the design and manufacturing process, and the error is generally more than 5%, which seriously affects the dynamic current sharing of the measured power device. In addition, the manufacturing cost of the inductor is high, and the cost-sensitive test scheme needs to be considered carefully.

[0047] (2) The control dimension of the application is small, and only the operation of the direct current voltage is needed to obtain the collector current value of the measured power device, which reduces the control complexity of the power device.

[0048] (3) The application can simultaneously test the dynamic current sharing of single or multiple power devices in parallel, reducing the operation complexity and labor intensity, and greatly improving the work efficiency.

[0049] (4) The platform of the application is simplified, and under the condition of testing multiple power devices in parallel, no parallel inductor is needed on each parallel power device, and only a resistor is used to connect to the negative electrode of the capacitor through a half-bridge circuit.

[0050] (5) The theoretical principle of the application is simple, and the current is calculated by voltage, pulse width time and inductance value, and only the Ohm's law is needed to confirm the size of the measured current value.

[0051] (6) The hardware driving architecture of the application is layered and modularized. In the face of the demand for multiple power devices in parallel, the driving module can be configured according to actual needs, and compared with the integrated driving module, the distributed driving has better anti-interference performance and improves the reliability of the driving pulse.

[0052] The above scheme will be described in detail below.

[0053] Embodiment 1

[0054] Referring to the accompanying Figure 1 , Figure 1 is the main structure diagram of the DSSC device dynamic current sharing test system based on multiple device parallelism of an embodiment of the application. As Figure 1 shown, the DSSC device dynamic current sharing test system based on multiple device parallelism in the embodiment of the application mainly includes a valve layer control board, a unit controller and a plurality of driving boards;

[0055] The valve layer control board is used to issue a test control pulse command to the unit controller;

[0056] The unit controller is used to generate a driving PWM pulse signal corresponding to the test control pulse command and issue it to the driving board;

[0057] The drive board is used for converting the received drive PWM pulse signal into an electric PWM signal for driving the power device and delivering the electric PWM signal to the power device in the half-bridge unit controlled by the drive board.

[0058] The power device in the half-bridge unit controlled by one drive board can be an IGBT.

[0059] In the embodiment, the system comprises a DSSC based on parallel connection of multiple devices to be measured, which is composed of a left half-bridge module and a right half-bridge module in parallel.

[0060] In one embodiment, as shown in Figure 2 The DC bus of the DSSC based on parallel connection of multiple devices to be measured is connected with a DC bus capacitor and a high-voltage adjustable DC source.

[0061] In one embodiment, the left half-bridge module or the right half-bridge module is composed of multiple half-bridge units in parallel.

[0062] In one embodiment, the half-bridge unit is composed of multiple half-bridge structures in parallel, and the AC output ends of the half-bridge structures are short-circuited through a laminated busbar to form the AC output end of the half-bridge unit.

[0063] In one embodiment, the AC output ends of the half-bridge units of the left half-bridge module or the right half-bridge module are short-circuited after being filtered by a conjugate inductor to form the AC output end of the left half-bridge module or the right half-bridge module.

[0064] In one embodiment, the AC output ends of the left half-bridge module and the right half-bridge module are short-circuited through a copper bar, and a soft wire is sequentially connected with an adjustable resistor box R and a negative electrode of a DC bus capacitor in the middle of the copper bar.

[0065] In one specific embodiment, as shown in Figure 3 In the embodiment, the application needs to add a monitoring device to observe the results, a Rogowski coil is arranged on the series bus between the adjustable resistor and the negative electrode of the capacitor, and the total current value and the waveform are observed through an oscilloscope; on the power device side, a Rogowski coil is arranged on the collector side of each power device, and the collector current and the waveform are observed through an oscilloscope. Finally, by comparing the differences between the collector currents of the power devices under different total currents, the current sharing of the multiple power devices in the turn-on and turn-off processes is directly verified.

[0066] Embodiment 2

[0067] Based on the same inventive concept, the application further provides a DSSC device dynamic current sharing test method based on parallel connection of multiple devices, which comprises the following steps:

[0068] setting the output voltage of the adjustable high-voltage power supply;

[0069] starting the current sharing test procedure;

[0070] testing the dynamic current sharing of the DSSC based on multiple devices in parallel based on the current data of the collector side of the upper tube power device unit in the DSSC based on multiple devices in parallel, and the series bus side between the adjustable resistor and the negative electrode of the DC bus capacitor.

[0071] Preferably, the adjustable high-voltage power supply output voltage is set in the range of 500V-4000V.

[0072] Preferably, the current sharing test procedure comprises:

[0073] starting the adjustable high-voltage power supply;

[0074] After the capacitor is charged, the host computer issues a pulse command;

[0075] generating and issuing the electric PWM signal for driving the power device through the valve layer control board, the unit controller and the plurality of drive boards;

[0076] collecting the current data of the collector side of the upper tube power device unit in the DSSC based on multiple devices in parallel, and the series bus side between the adjustable resistor and the negative electrode of the DC bus capacitor;

[0077] turning off the adjustable high-voltage power supply.

[0078] Further, the adjustable resistor box can be configured in the range of 10Ω-0.01Ω, and the preset resistance value of the adjustable resistor box is 1Ω.

[0079] Preferably, the testing of the dynamic current sharing of the DSSC based on multiple devices in parallel based on the current data of the collector side of the upper tube power device unit in the DSSC based on multiple devices in parallel, and the series bus side between the adjustable resistor and the negative electrode of the DC bus capacitor comprises:

[0080] If the sum of the currents of the collector sides of all upper tube power device units in the DSSC based on multiple devices in parallel is consistent with the current of the series bus side between the adjustable resistor and the negative electrode of the DC bus capacitor, and the current waveform and current peak of the collector side of each upper tube power device unit in the DSSC based on multiple devices in parallel differ within ±5%, then the DSSC based on multiple devices in parallel passes the dynamic current sharing test, otherwise, the DSSC based on multiple devices in parallel fails the dynamic current sharing test.

[0081] Embodiment 3

[0082] Based on the same inventive concept, the present application further provides a computer device, which comprises a processor and a memory, the memory is used to store a computer program, the computer program comprises program instructions, and the processor is used to execute the program instructions stored in the computer storage medium. The processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., which are the computing core and control core of the terminal, and are suitable for implementing one or more instructions, and are specifically suitable for loading and executing one or more instructions in the computer storage medium to implement a corresponding method flow or a corresponding function, so as to implement the steps of the DSSC device dynamic current sharing test method based on the parallel connection of multiple devices in the above embodiment.

[0083] Embodiment 4

[0084] Based on the same inventive concept, the present application further provides a storage medium, specifically a computer readable storage medium (Memory), which is a memory device in the computer device, and is used to store programs and data. It can be understood that the computer readable storage medium here can include the built-in storage medium in the computer device, and of course can also include the expansion storage medium supported by the computer device. The computer readable storage medium provides a storage space, and the storage space stores the operating system of the terminal. Moreover, one or more instructions suitable for being loaded and executed by the processor are also stored in the storage space, and the instructions can be one or more computer programs (including program codes). It should be noted that the computer readable storage medium here can be a high-speed RAM memory, or a non-volatile memory such as at least one disk memory. One or more instructions stored in the computer readable storage medium can be loaded and executed by the processor to implement the steps of the DSSC device dynamic current sharing test method based on the parallel connection of multiple devices in the above embodiment.

[0085] Those skilled in the art will appreciate that embodiments of the application can be devised for a method, a system, or a computer program product. Accordingly, the present application can be embodied in the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, etc.) embodying computer readable program code.

[0086] The present application is described in reference to the flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0087] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0088] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0089] Finally, it should be noted that the above-mentioned embodiments are merely intended for describing and illustrating, not limiting the technical solutions of the present application. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the specific embodiments of the present application can be modified or replaced by equivalents without departing from the spirit and scope of the present application, and any modifications or equivalent replacements without departing from the spirit and scope of the present application should be covered in the protection scope of the claims of the present application.

Claims

1. A DSSC device dynamic current sharing test system based on multi-device parallel connection, characterized in that, The system includes: a valve layer control board, a unit controller, and multiple drive boards; The valve layer control board is used to send test control pulse commands to the unit controller; The unit controller is used to generate the drive PWM pulse signal corresponding to the test control pulse command and send it to the driver board; The driver board is used to convert the received drive PWM pulse signal into an electric PWM signal for driving the power device, and to send the electric PWM signal to the power device in the half-bridge unit controlled by the driver board. In this case, the control object of one driver board is the power device in a half-bridge unit.

2. The system of claim 1, wherein, The system includes a DSSC based on parallel connection of multiple devices, consisting of a left half-bridge module and a right half-bridge module connected in parallel.

3. The system as described in claim 2, characterized in that, The tested DSSC, based on multiple devices connected in parallel, has a DC bus capacitor and a high-voltage adjustable DC source connected to its DC bus.

4. The system as described in claim 3, characterized in that, The left or right half-bridge module is composed of multiple half-bridge units connected in parallel.

5. The system as described in claim 4, characterized in that, The half-bridge unit is composed of multiple half-bridge structures connected in parallel, and the AC output terminals of each half-bridge structure are short-circuited through a laminated busbar to form the AC output terminal of the half-bridge unit.

6. The system as described in claim 5, characterized in that, The AC output terminals of each half-bridge unit of the left or right half-bridge module are short-circuited after being filtered by a conjugate inductor to form the AC output terminals of the left or right half-bridge module.

7. The system as described in claim 6, characterized in that, The AC output terminals of the left and right half-bridge modules are shorted by a copper busbar, and the adjustable resistor box and the negative terminal of the DC bus capacitor are connected in sequence by a flexible wire in the middle of the copper busbar.

8. A method for testing the dynamic current sharing performance of a DSSC device based on a multi-device parallel connection as described in any one of claims 1-7, characterized in that, The method includes: Set the adjustable high-voltage power supply output voltage; Initiate the flow sharing test procedure; The dynamic current sharing performance of the DSSC based on multiple parallel devices was tested by measuring the current data on the collector side of the power device unit of the upper transistor and the series bus side between the adjustable resistor and the negative terminal of the DC bus capacitor in the DSSC based on multiple parallel devices.

9. The method as described in claim 8, characterized in that, The adjustable high-voltage power supply output voltage setting range is 500V-4000V.

10. The method as described in claim 8, characterized in that, The flow sharing test procedure includes: Start the adjustable high-voltage power supply; After the capacitor is fully charged, a pulse command is sent from the host computer. The valve layer control board, unit controller and multiple drive boards generate and send out electrical PWM signals for driving power devices; Collect current data from the collector side of the upper transistor power device unit and the series bus side between the adjustable resistor and the negative terminal of the DC bus capacitor in the DSSC based on multiple devices in parallel. Turn off the adjustable high-voltage power supply.

11. The method as described in claim 10, characterized in that, The preset resistance value of the adjustable resistor box is 1Ω.

12. The method as described in claim 8, characterized in that, The dynamic current sharing of the DSSC based on the current data of the collector side of the upper power device unit and the series bus side between the adjustable resistor and the negative terminal of the DC bus capacitor in the DSSC based on multiple devices in parallel is tested, including: If the sum of the collector currents of all the upper-side power device units in the DSSC under test based on multiple parallel devices is consistent with the current on the series bus side between the adjustable resistor and the negative terminal of the DC bus capacitor, and the difference between the current waveform and current spike of each upper-side power device unit in the DSSC under test based on multiple parallel devices is within ±5%, then the DSSC under test based on multiple parallel devices passes the dynamic current sharing test; otherwise, the DSSC under test based on multiple parallel devices fails the dynamic current sharing test.

13. A computer device, characterized in that, include: One or more processors; The processor is used to execute one or more programs; When the one or more programs are executed by the one or more processors, the dynamic current sharing test method for DSSC devices based on parallel connection of multiple devices as described in any one of claims 8 to 12 is implemented.

14. A computer-readable storage medium, characterized in that, It contains a computer program, which, when executed, implements the dynamic current sharing test method for DSSC devices based on parallel connection of multiple devices as described in any one of claims 8 to 12.

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