Method for optimizing virtual NVMe read-write performance through LRU algorithm and virtual NVMe system

Abstract

The application provides a method for optimizing virtual NVMe read-write performance through an LRU algorithm and a virtual NVMe system, and the method comprises the following steps: constructing a cache management architecture in cooperation with a hash table and a double-linked list, quickly positioning a cache node corresponding to an internal address of an SSD through the hash table, and managing the access order of the SSD address through the double-linked list; when the NVMe performs an SSD read-write operation, the LRU algorithm is first called, and if there is no address in the hash table to execute the read-write file; a linked list order adjustment thread is created when the LRU algorithm is initialized, the node data of the longest non-accessed node exceeding the length of the linked list is flushed to the SSD mirror file, and then the node is deleted; when the read-write data is greater than the size of the linked list node data, the hash mapping is refreshed. The application combines the LRU algorithm, maps the commonly used internal address of the SSD and the corresponding data block, directly operates the memory to read and write the commonly used data, optimizes the read-write mode of the existing virtual simulation NVMe, and further improves the performance of the virtual simulation NVMe in the virtual hardware system.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer software, in particular to a method for optimizing virtual NVMe read-write performance through LRU algorithm and a virtual NVMe system. BACKGROUND

[0002] With the development of computer storage technology towards high speed and light weight, NVMe (Non-Volatile Memory Host Controller Interface Specification) has become one of the core technologies in the field of high-performance storage due to its low latency and high bandwidth. In virtualization, cloud computing and embedded simulation scenarios, virtual NVMe as a key component to simulate the function of physical NVMe hardware, its performance directly determines the overall running efficiency of the virtual hardware system, especially in data-intensive tasks (such as database interaction, high-frequency file read-write, virtual machine storage expansion), the requirement for read-write response speed of virtual NVMe is increasingly stringent.

[0003] The current mainstream virtual NVMe simulation technology generally adopts an implementation scheme of "relying on host read-write functions to directly operate SSD image files". The core logic of this scheme is that when the virtual NVMe executes a read-write request, it needs to call the file IO interface (such as read / write system call) of the host to perform data read-write on the pre-created SSD image file (i.e. a file simulating physical SSD storage medium), thereby completing the storage function simulation.

[0004] However, the above existing scheme has significant performance bottlenecks and is difficult to meet the use requirements in high-load scenarios, and the specific defects are as follows:

[0005] 1. To simulate the storage capacity of a physical SSD, the SSD image file is usually a super large file of GB level or even TB level; in the existing scheme, each read-write request needs to open, operate and close the image file, and the frequent opening / closing operation of the operating system on the super large file will generate a large amount of IO waiting time, directly limiting the read-write response rate of the virtual NVMe.

[0006] 2. Lack of high-frequency data caching mechanism; the existing scheme does not perform special processing on the high-frequency accessed SSD address data, and if the same address data is repeatedly accessed (such as repeatedly reading the same configuration file, frequently updating the same data block), the process of "calling host function-reading image file" still needs to be repeatedly executed, causing redundant consumption of storage resources and further reducing the read-write efficiency.

[0007] 3、System performance drag is obvious;Affected by the above two defects, the read and write performance of the existing virtual NVMe is much lower than that of the physical NVMe, and in the high concurrency read and write scene, it will become the performance short board of the virtual hardware system, for example, in the multi-virtual machine concurrent running, high frequency data interaction task, the delay of virtual NVMe will be transmitted to the upper layer application, resulting in the running efficiency of the whole system is greatly reduced, and the demand of actual application to storage performance cannot be met.

[0008] In summary, due to the core design defect of "directly operating SSD image file", the existing virtual NVMe simulation technology has the problems of obvious performance bottleneck and redundant resource consumption, and a technical solution capable of optimizing read and write logic and reducing IO overhead is needed to improve the performance of virtual NVMe in virtual hardware system. SUMMARY

[0009] In view of the defects in the prior art, the purpose of the present application is to provide a method for optimizing the read and write performance of virtual NVMe by LRU algorithm and a virtual NVMe system.

[0010] According to the method for optimizing the read and write performance of virtual NVMe by LRU algorithm provided by the present application, the method comprises the following steps:

[0011] The LRU algorithm construction step: a cache management architecture of hash table and double linked list is constructed, the cache node corresponding to the internal address of SSD is quickly located through the hash table, and the access order of SSD address is managed through the double linked list;

[0012] The image read and write optimization step: if the SSD address to be read and written exists in the hash table, the read and write operation is selected to be performed from the cache node or the SSD image file according to the corresponding data size in the linked list and the data size of this time read and write;If the address does not exist in the hash table, the read and write operation is directly performed on the SSD image file;

[0013] The performance optimization step: when the LRU algorithm is initialized, a linked list order adjustment thread is created, the node data of the longest access and the chain table length is flushed to the SSD image file and then deleted;When the read and write data is greater than the data size of the linked list node, the hash mapping is refreshed.

[0014] Preferably, the data structure of the hash table and the double linked list in the LRU algorithm construction step comprises:

[0015] The key value of the hash table is set as the internal address of the SSD to be accessed, and the value is set as the memory pointer of the corresponding node in the double linked list;Each node of the double linked list stores the internal address value of the SSD, the length of the data corresponding to the address, the memory storage area of the data, and the pointer to the predecessor and successor nodes of the node.

[0016] Preferably, the LRU algorithm construction step includes managing the access order of the SSD address by a double-linked list, which comprises:

[0017] When the virtual NVMe accesses the SSD address, the address value, data length and corresponding data of the address are stored in the linked list node, the independent memory space of the node is allocated, and the predecessor and successor pointers of the node are recorded; if the address is accessed again, the position of the node in the linked list is adjusted through the pointers.

[0018] Preferably, the LRU algorithm construction step further comprises:

[0019] When the SSD address hits the cache node through the hash table, the node is moved from the current position to the head of the double-linked list, and the position adjustment is completed by modifying the predecessor and successor pointer relationship of the node.

[0020] Preferably, the LRU algorithm construction step further comprises:

[0021] The maximum number of nodes of the double-linked list is set in advance to avoid high memory occupation or memory leakage; when the number of linked list nodes reaches the upper limit, the least recently accessed node located at the tail of the linked list is deleted, the memory occupied by the node is released, and the key-value pair of the corresponding SSD address in the hash table is deleted.

[0022] Preferably, the mirror read-write optimization step comprises:

[0023] If the node of the target SSD address exists in the hash table, the relationship between the read-write data size and the node storage data size is judged:

[0024] If it is a read operation and the required data size is less than or equal to the node storage data size, the corresponding length data is directly intercepted from the node memory area and returned;

[0025] If it is a write operation and the required data size is less than or equal to the node storage data size, the data to be written is copied to the node memory area, and the node data is marked as "modified";

[0026] If the read-write data size is greater than the node storage data size, the cache is skipped, and the read-write operation is performed on the SSD mirror file through the host file IO interface;

[0027] If the node of the target SSD address does not exist in the hash table, the SSD mirror file is operated through the host file IO interface, the read-write is completed, and it is judged whether to create a new node to join the cache according to the access frequency of the address, and only the node of the high-frequency access address is added to the cache.

[0028] Preferably, the performance optimization step comprises: creating an independent background thread at the initialization of the LRU algorithm, the thread performing sequential adjustment of the doubly linked list, ensuring that the "recently accessed" node is located at the head of the list, and the thread running does not affect the main read-write flow of the virtual NVMe.

[0029] Preferably, the performance optimization step further comprises:

[0030] When the read-write data size in the mirror read-write optimization step is greater than the node storage data size, the hash mapping is refreshed, the hash table key value is kept as the original SSD address value, if it is a read operation, memory is re-allocated to store the complete data read from the file, if it is a write operation, memory is re-allocated to store the complete data to be written, and the hash table and the node mapping of the doubly linked list are updated.

[0031] Preferably, the performance optimization step further comprises:

[0032] A thread synchronization mechanism is set to avoid data competition caused by concurrent operation of the background thread and the main read-write thread on the cache node, and a key read-write operation log is recorded, the log including the SSD address value, the data length and the operation time, which is used to recover the "modified" data not flushed to the disk after system abnormal crash.

[0033] According to the virtual NVMe system provided by the application, the method for optimizing the read-write performance of the virtual NVMe through the LRU algorithm is adopted.

[0034] Compared with the prior art, the application has the following beneficial effects:

[0035] 1. The application combines the LRU algorithm, maps the commonly used SSD internal address and the corresponding data block, directly operates the memory to read and write the commonly used data, optimizes the read-write mode of the existing virtual simulation NVMe, and further improves the performance of the virtual simulation NVMe in the virtual hardware system.

[0036] 2. The mainstream NVMe virtual simulation technology currently usually adopts the mode of realizing the read-write operation on the SSD mirror through calling the host read-write function, and this mode needs to frequently open and close the mirror file, and the SSD mirror of this kind of NVMe is generally a super large file, so the frequent opening and closing of the file greatly limits the running rate of the NVMe, and greatly reduces the running performance of the overall hardware system. The application can greatly improve the performance of the virtual simulation NVMe by combining the LRU algorithm. BRIEF DESCRIPTION OF DRAWINGS

[0037] Other features, objects and advantages of the application will become more apparent from the following detailed description of non-limiting embodiments, made with reference to the accompanying drawings:

[0038] Figure 1The read-write flow chart after LRU optimization for NVMe in the application;

[0039] Figure 2 The LRU algorithm structure diagram in the application. DETAILED DESCRIPTION

[0040] The application will be described in detail below with specific embodiments. The following examples will help those skilled in the art to further understand the application, but do not limit the application in any form. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the application. These are within the scope of the application.

[0041] The application discloses a method for optimizing virtual NVMe read-write performance by LRU algorithm, referring to Figure 1 and Figure 2 The method comprises the following steps:

[0042] The LRU algorithm construction step: this step constructs the cache management mechanism of high-frequency data through the collaborative design of hash table and double-linked list, and the core is to quickly locate and maintain the access order of SSD address, and the specific process is as follows:

[0043] Step S1.1: data structure building; build the basic framework of hash table and double-linked list - hash table is used to quickly find the cache node corresponding to the SSD address, and the key value is set as the SSD internal address to be accessed, and the value is set as the memory pointer of the corresponding node in the double-linked list; the double-linked list is used to manage the access order of the address, and each list node needs to store four core information: the current access SSD address value, the length of the data corresponding to the address, the memory storage area of the data itself, and the pointer to the predecessor and successor nodes of the node, to ensure that the node order can be quickly adjusted.

[0044] Step S1.2: access management of double-linked list; when the virtual NVMe accesses a certain SSD address, first store the address value, data length and corresponding data of the address into the list node, and allocate independent memory space for the node, and record the predecessor and successor pointers of the node; for example, when a new address is accessed, it is created as a new node and connected to the list through the predecessor / successor pointer, and if the address is accessed again subsequently, the position of the node in the list can be directly adjusted through the pointer.

[0045] Step S1.3: fast lookup configuration of hash table; use the SSD address value as the key value of the hash table, and map it to the corresponding hash bucket through hash calculation, to realize the quick positioning of the list node; if different addresses are mapped to the same hash bucket (i.e. hash conflict), the target address is matched through the list in the bucket, to ensure that the lookup operation is efficiently executed, and to avoid the influence of address lookup time consumption on the overall performance.

[0046] Step S1.4: Dynamic update of access order; when a certain SSD address hits a cache node through the hash table, the node needs to be moved from the current location to the head of the double-linked list and marked as "recently accessed"; for example, a node originally located in the middle of the list is relocated to the head of the list by modifying the pointer relationship between its front and back nodes, ensuring that it can be accessed preferentially in subsequent high-frequency access.

[0047] Step S1.5: Constraint control of list length; the maximum number of nodes in the double-linked list is pre-set (such as 512 nodes according to the host memory capacity), avoiding excessive memory occupation or memory leakage due to unlimited increase of nodes; if the current number of list nodes reaches the upper limit, the subsequent node elimination logic is triggered.

[0048] Step S1.6: Elimination of the least recently accessed node; when the number of list nodes exceeds the set upper limit, the node located at the tail of the list (i.e., the least recently accessed) is deleted from the list; before deletion, the memory occupied by the node needs to be released, and the corresponding key-value pair in the hash table is also deleted synchronously, ensuring that the cache resources can be recycled.

[0049] Mirror read-write optimization step: this step embeds the LRU algorithm into the read-write process of the virtual NVMe, preferentially processes high-frequency data through the cache, and reduces direct IO operations on the SSD mirror file, as follows:

[0050] Step S2.1: Call logic of LRU algorithm: when the virtual NVMe initiates an SSD read-write request, the LRU algorithm constructed in step S1.1 is first called to perform cache matching on the target SSD address:

[0051] Step S2.1.1: If the hash table contains a node corresponding to the address, first determine whether the data size of this read-write operation is consistent with the data size stored in the node;

[0052] Step S2.1.2: If it is a read operation and the required data size is less than or equal to the node's stored data size, the corresponding length of data is directly cut from the node's memory area and returned, without accessing the SSD mirror file;

[0053] Step S2.1.3: If it is a write operation and the required data size is less than or equal to the node's stored data size, the data to be written is directly copied to the node's memory area, and the node's data is marked as "modified" after the write is completed;

[0054] Step S2.1.4: If the data size of this read-write operation is greater than the node's stored data size (such as requesting to read or write 32KB data, and the node only stores 16KB data), skip the cache and directly call the file operation interface of the host to read or write the SSD mirror file, avoiding performance loss due to memory reallocation.

[0055] Step S2.2: Processing of cache miss; if the node of the target SSD address does not exist in the hash table, directly operate the SSD image file through the file IO interface of the host computer (such as calculating the file offset according to the address, and executing read / write operation), complete the read / write, and judge whether to create a new node to join the cache according to the access frequency of the address (such as access ≥ 3 times within 5 minutes) to avoid invalid cache occupation.

[0056] Performance optimization step; this step further improves the optimization effect through thread scheduling and data consistency guarantee measures, ensures the virtual NVMe read / write performance and data integrity, and the specific steps are as follows:

[0057] Step S3.1: Optimization target and core principle; while improving the read / write performance, ensure the consistency of SSD image data and cache data, and avoid data loss or tampering caused by cache operation.

[0058] Step S3.2: Creation of background maintenance thread; when the LRU algorithm is initialized, a separate background thread is created, which is responsible for the order adjustment of the double-linked list (such as regularly arranging the node order to ensure that the "recently accessed" node is always located at the head), and the thread runs without affecting the main read / write process of the virtual NVMe, avoiding interference with the core operation.

[0059] Step S3.3: Asynchronous flushing of dirty data; before the background thread executes node eviction (i.e. step S1.6), it first checks whether the data of the node to be evicted is "modified" (i.e. the node marked in step S2.1.3); if it is "modified", the node data is first written to the address corresponding to the SSD image file, and after the flushing is completed, the node and the hash table mapping are deleted, ensuring that the modified data is not lost.

[0060] Step S3.4: Dynamic refreshing of hash mapping; when the read / write data size exceeds the node storage size in step S2.1.4, the refreshing operation of the hash mapping is triggered:

[0061] Step S3.4.1: Keep the key value of the hash table as the original SSD address value to avoid address mapping confusion;

[0062] Step S3.4.2: If it is a read operation, reapply memory, store the complete data read from the SSD image file and the data size into the new node, and update the hash table mapping;

[0063] Step S3.4.3: If it is a write operation, reapply memory, store the complete data to be written and the data size into the new node, and update the hash table mapping;

[0064] Step S3.4.4: To reduce the impact on the main read / write process, this refreshing operation can be executed in an independent thread to ensure the response speed of the main process.

[0065] Step S3.5: constraint control of data consistency; a thread synchronization mechanism (such as a mutex) is set to avoid data competition caused by the background thread and the main read-write thread operating the cache node at the same time; at the same time, a log (such as address, data size, operation time) of the key read-write operation is recorded, and if the system crashes abnormally, the "modified" data not flushed to the disk can be recovered through the log to guarantee data integrity.

[0066] The application further discloses a virtual NVMe system, which executes the method for optimizing the virtual NVMe read-write performance through the LRU algorithm.

[0067] Those skilled in the art know that, in addition to implementing the system provided by the application and each device, module and unit thereof in a pure computer readable program code manner, the system provided by the application and each device, module and unit thereof can also be implemented in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers and embedded microcontrollers, etc. by logically programming the method steps to achieve the same functions. Therefore, the system provided by the application and each device, module and unit thereof can be considered as a hardware component, and the devices, modules and units included therein for achieving various functions can also be considered as structures in the hardware component; the devices, modules and units for achieving various functions can also be considered as both software modules for implementing methods and structures in the hardware component.

[0068] The specific embodiments of the application are described above. It needs to be understood that the application is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essential content of the application. In the case of no conflict, the embodiments of the application and the features in the embodiments can be combined with each other at will.

Claims

1. A method for optimizing virtual NVMe read-write performance by LRU algorithm, characterized in that, Comprise: LRU algorithm construction steps: build a cache management architecture of hash table and double linked list, quickly locate the cache node corresponding to the SSD internal address through the hash table, and manage the access order of the SSD address through the double linked list; Mirror read and write optimization steps: if there is a node of the target SSD address in the hash table, judge the relationship between the read and write data size and the node storage data size: if it is a read operation and the required data size is less than or equal to the node storage data size, the corresponding length data is directly cut from the node memory area and returned; if it is a write operation and the required data size is less than or equal to the node storage data size, the data to be written is copied to the node memory area, and the node data is marked as "modified"; if the read and write data size is greater than the node storage data size, skip the cache, and perform read and write operations on the SSD image file through the host file IO interface; if there is no such address in the hash table, directly perform read and write operations on the SSD image file; Performance optimization steps: create a linked list order adjustment thread when initializing the LRU algorithm, flush the node data that has not been accessed for the longest time and exceeds the length of the linked list to the SSD image file, and then delete the node; when the read and write data is greater than the size of the linked list node data, refresh the hash mapping.

2. The method for optimizing virtual NVMe read-write performance by LRU algorithm according to claim 1, characterized in that, The data structure of the hash table and the double linked list in the LRU algorithm construction steps comprises: The key value of the hash table is set as the SSD internal address to be accessed, and the value is set as the memory pointer of the corresponding node in the double linked list; each node of the double linked list stores the SSD internal address value, the length of the data corresponding to the address, the memory storage area of the data, and the pointers to the predecessor and successor nodes of the node.

3. The method for optimizing virtual NVMe read-write performance by LRU algorithm according to claim 2, characterized in that, The access order of the SSD address managed by the double linked list in the LRU algorithm construction steps comprises: When accessing the SSD address virtually, the address value, data length and corresponding data of the address are stored in the linked list node, independent memory space is allocated for the node, and the predecessor and successor pointers of the node are recorded; if the address is accessed again, the position of the node in the linked list is adjusted through the pointer.

4. The method for optimizing virtual NVMe read-write performance by LRU algorithm according to claim 2, characterized in that, The LRU algorithm construction steps further comprise: When the SSD address hits the cache node through the hash table, the node is moved from the current position to the head of the double linked list, and the position adjustment is completed by modifying the predecessor and successor pointer relationship of the node.

5. The method for optimizing virtual NVMe read-write performance through LRU algorithm according to claim 2, characterized in that, The LRU algorithm construction steps further comprise: The maximum number of nodes of the double linked list is set in advance to avoid high memory occupation or memory leakage; when the number of linked list nodes reaches the upper limit, the node that has not been accessed for the longest time located at the tail of the linked list is deleted, the memory occupied by the node is released, and the key value pair of the corresponding SSD address in the hash table is deleted.

6. The method for optimizing virtual NVMe read-write performance by LRU algorithm according to claim 1, characterized in that, The mirror read and write optimization steps comprise: If there is a node of the target SSD address in the hash table, judge the relationship between the read and write data size and the node storage data size: If it is a read operation and the required data size is less than or equal to the node storage data size, the corresponding length data is directly cut from the node memory area and returned; If it is a write operation and the required data size is less than or equal to the node storage data size, the data to be written is copied to the node memory area, and the node data is marked as "modified"; If the read / write data size is greater than the node storage data size, skip the cache, and perform read / write operations on the SSD image file through the host file IO interface; If the node of the target SSD address does not exist in the hash table, operate the SSD image file through the host file IO interface, complete the read / write operation, and judge whether to create a new node to join the cache according to the access frequency of the address. Only the nodes of high-frequency access addresses are added to the cache.

7. The method for optimizing virtual NVMe read-write performance through LRU algorithm according to claim 1, characterized in that, The performance optimization step includes: creating an independent background thread when the LRU algorithm is initialized, and the thread performs sequential adjustment of the double-linked list to ensure that the "recently accessed" node is located at the head of the list, and the thread runs without affecting the main read / write flow of the virtual NVMe.

8. The method for optimizing virtual NVMe read-write performance by LRU algorithm according to claim 1, characterized in that, The performance optimization step further includes: When the read / write data size is greater than the node storage data size in the image read / write optimization step, trigger the hash mapping refresh, keep the hash table key value as the original SSD address value, and if it is a read operation, re-allocate memory to store the complete data read from the file, if it is a write operation, re-allocate memory to store the complete data to be written, and update the node mapping of the hash table and the double-linked list.

9. The method for optimizing virtual NVMe read-write performance through LRU algorithm according to claim 1, characterized in that, The performance optimization step further includes: Set up a thread synchronization mechanism to avoid data competition caused by concurrent operation of the cache node by the background thread and the main read / write thread; at the same time, record the log of the key read / write operation, which includes the SSD address value, the data length and the operation time, for recovering the "modified" data not flushed to the disk after the system crashes abnormally.

10. A virtual NVMe system, comprising: The system adopts the method for optimizing the read / write performance of the virtual NVMe through the LRU algorithm according to claim 1.

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