Scan chain optimization method, computer equipment, storage medium and program product

Abstract

The invention provides a scan chain optimization method, computer equipment, a storage medium and a program product. The method comprises the following steps: determining a plurality of initial scan chains to be optimized; mixing the scan registers of the plurality of initial scan chains to obtain a scan register set; sorting the scan registers in the scan register set based on a scan chain wiring length to obtain a long-chain scan chain; cutting the long-chain scanning chain to obtain a plurality of scanning chain segments in one-to-one correspondence with the plurality of initial scanning chains; sorting the plurality of scanning chain segments according to the cutting sequence, and determining whether the scanning chain bit width corresponding to each scanning chain segment meets the bit width requirement or not; in response to the situation that the scanning chain bit width corresponding to any scanning chain segment does not meet the bit width requirement, the scanning register is moved between the adjacent scanning chain segments until the scanning chain bit widths corresponding to all the scanning chain segments meet the bit width requirement, and multiple optimized target scanning chains are obtained.

Description

Technical Field

[0001] This disclosure relates to the field of chip design technology, and in particular to a scan chain optimization method, computer equipment, storage medium, and program product. Background Technology

[0002] Design for Test (DFT) is a method to improve chip testability by inserting hardware structures or adding design rules within the chip design to ensure efficient detection of physical defects such as open circuits, short circuits, and transistor failures.

[0003] Scan chain is a key structured design technique in DFT implementation. It connects the registers (Flip-Flop, or FF) in the chip into a chain in a specific way, so that test data can be serially input and output like a shift register.

[0004] The register used in the scan chain is a scan register (Scan FF), which adds a multiplexer compared to a regular register. An enable signal switches the scan register between functional mode and scan mode. Functional mode means the scan register can normally receive and send logical data, while scan mode means the scan register receives the output of the previous scan register and forwards it to the next scan register.

[0005] Scan reordering refers to the process of rearranging the connection order of Scan FFs that already have physical locations, with the aim of optimizing the total wire length of the entire scan chain. The prerequisite for scan chain reordering is that changes in the serial position of the scan registers do not affect the overall test functionality. Because the physical locations of the scan registers on the link differ, the order in which they are serially connected will affect the final layout length of the entire scan chain.

[0006] like Figure 1A As shown, the boxes represent Scan FF, and the positions of the boxes indicate the physical locations of Scan FF. If the scan chain is connected in the order of scan registers 1, 2, 3, 4, less wire length will be used; if the scan chain is connected in the order of scan registers 1, 3, 2, 4, more wire length will be used. Therefore, the connection order of the scan registers has a significant impact on the wiring length.

[0007] However, the inventors of this disclosure have found that the related technologies have difficulty simultaneously achieving both optimization effect and optimization efficiency when optimizing the scan chain. Summary of the Invention

[0008] This disclosure proposes a scan chain optimization method, as well as computer equipment, storage media, and program products, to solve or partially solve the above-mentioned problems.

[0009] In a first aspect, this disclosure provides a scan chain optimization method, comprising: Identify multiple initial scan chains to be optimized; The scan registers remaining in each of the plurality of initial scan chains, excluding the start scan register and the end scan register, are mixed to obtain a scan register set; Based on the scan chain wiring length, the scan registers in the scan register set are sorted to obtain a long-chain scan chain; Based on the distance between each scan register in the long scan chain and each initial scan chain in the plurality of initial scan chains, the long scan chain is cut to obtain a plurality of scan chain segments that correspond one-to-one with the plurality of initial scan chains; The multiple scan chain segments are sorted according to the cutting order, and it is determined whether the scan chain bit width corresponding to each scan chain segment meets the bit width requirement. In response to any scan chain segment whose scan chain bit width does not meet the bit width requirement, the scan register is moved between adjacent scan chain segments until the scan chain bit width of all scan chain segments meets the bit width requirement, thus obtaining multiple optimized target scan chains.

[0010] A second aspect of this disclosure provides a computer device including one or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, and the one or more programs include instructions for performing the method of the first or second aspect.

[0011] A third aspect of this disclosure provides a non-volatile computer-readable storage medium containing a computer program that, when executed by one or more processors, causes the one or more processors to perform the method described in the first or second aspect.

[0012] A fourth aspect of this disclosure provides a computer program product comprising one or more computer programs that, when executed by one or more processors, implement the method as described in the first or second aspect.

[0013] The scan chain optimization method, computer device, storage medium, and program product provided in this disclosure can perform global optimization of routing by mixing and sorting the scan registers first; cutting based on distance helps to reduce the loss of routing length; and moving the scan register between adjacent scan chain segments to change the scan chain bit width corresponding to each scan chain segment can obtain all target scan chains that meet the bit width requirements after a finite number of processing steps, while the loss of routing length is small. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in this disclosure or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1A A schematic diagram illustrating the effect of the scan register connection order on the wiring is shown.

[0016] Figure 1B A schematic diagram of an exemplary Repartition process is shown.

[0017] Figure 1C An exemplary schematic diagram of hybrid reordering is shown.

[0018] Figure 1D Another exemplary schematic diagram of hybrid reordering is shown.

[0019] Figure 1E An exemplary diagram comparing the costs of movement and exchange is shown.

[0020] Figure 2 A schematic flowchart of an exemplary scan chain optimization method provided in an embodiment of this disclosure is shown.

[0021] Figure 3A A schematic diagram of an exemplary three scan chains according to an embodiment of the present disclosure is shown.

[0022] Figure 3B A schematic diagram of an exemplary long-chain scan chain according to an embodiment of the present disclosure is shown.

[0023] Figure 4A A schematic diagram of three exemplary scan chain segments according to an embodiment of the present disclosure is shown.

[0024] Figure 4B A schematic diagram illustrating an exemplary movement of a scan register between scan chain segments according to an embodiment of the present disclosure is shown.

[0025] Figure 5 A schematic diagram of the hardware structure of an exemplary computer device provided in an embodiment of this disclosure is shown. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0027] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0028] As mentioned earlier, the connection order of the scan registers has a significant impact on the wiring length of the scan chain. Generally, it is desirable to keep the wiring length as short as possible to facilitate wiring implementation.

[0029] In some cases, a chip design may contain multiple scan chains, each with a certain number of scan registers. This necessitates considering how to achieve the best optimization effect for all scan chains from a global perspective.

[0030] Generally, scan registers can be divided into two categories based on their bit width: ordinary registers with a bit width of 1 bit and memory registers with a bit width greater than 1 bit. For each scan chain, its maximum bit width (Max bit) is usually the sum of the bit widths of all its scan registers. Therefore, for each optimized scan chain, its total bit width should remain unchanged or be less than its maximum bit width to meet the bit width requirements.

[0031] When optimizing scan chains, scan registers can be swapped or moved between different scan chains, and then each scan chain is reordered to optimize the total wiring length. This swapping and reordering activity can be called repartitioning.

[0032] by Figure 1BFor example, suppose there are two scan chains in the chip design, with their scan registers being {1, 6, 3, 4} and {5, 2, 7, 8} respectively, and their connection methods are as follows: Figure 1B As shown, the position of the scan register in the diagram represents its physical location. If scan registers 2 and 6 are swapped and the scan chains are reordered, the wiring lengths of both scan chains will be optimized.

[0033] In some cases, there may also be an ordered section in the scan chain, which means that the connection order of a part of the scan registers in the scan chain is fixed. That is, the connection method inside the ordered section cannot be changed, so the order of its internal scan registers is not allowed to be changed.

[0034] Therefore, under the constraint of the bit width length of each scan chain, how to repartition and reallocate the scan chains, how to arrange the scan chains to which the memory in the scan register belongs and their sorting positions, and how to handle the case where the memory is in the Ordered Section are a series of important problems that need to be solved.

[0035] In related technologies, the repartition process for the scan chain does not consider the limitation on the scan chain length (or the limitation on the maximum bit width). That is, after repartitioning the scan chain, the length of the scan chain is not equal to the original length or exceeds the maximum length limit. In addition, in related technologies, reordering after exchanging scan chains or unidirectionally moving scan registers results in a locally optimal solution due to the limitations of local adjustment methods, and does not achieve the effect of significantly reducing the sum of the routing lengths of all scan chains.

[0036] If all scan registers in the design, regardless of which scan chain they belong to, are first mixed together and then reordered using the Traveling Salesman (TSP) algorithm, and then the sorted scan registers are reallocated back into the scan chain according to the original scan chain length, then due to the large bit width of memory, memory allocation will have to perform shift or swap operations to meet the length limit. How to perform shift and swap operations to obtain a scan chain with a valid length is a difficult problem, and there is currently no efficient method.

[0037] like Figure 1C As shown, assuming there are two scan chains in the chip design, each box represents a scan register, the number inside represents its bit width, the directed edge represents the connection order, the position of the box does not represent the actual physical location of the scan register, and the maximum bit width (Max bit) represents the scan chain length.

[0038] If the scan registers in the two scan chains are mixed and reordered, assuming the sorted result is as follows... Figure 1C As shown in the long chain diagram. It can be seen that, without moving or swapping the scan register, no matter how this long chain is cut, there will always be one scan chain whose length exceeds the original Max bit. Figure 1C Taking the cutting position as an example, cutting along the edge corresponding to that position yields two scan chains. The sum of the scan register widths of the right scan chain is 99, which is greater than the maximum width of 98. To solve this problem, a movement adjustment, as shown by the dashed line in the diagram, must be performed (moving the scan register corresponding to the end of the dashed line to the position indicated by the dashed arrow) before two scan chains of legal length can be cut from the long chain.

[0039] For example Figure 1D As shown, assume there are 3 scan chains in the chip design, where the boxes represent scan registers, the numbers inside represent bit widths, the directed edges represent the connection order, the position of the boxes does not represent the actual physical location of the scan registers, and the maximum bit width (Max bit) represents the scan chain length. Assume that after mixing all scan registers and reordering them, the result is as follows... Figure 1D In a long chain, if cut at the cutting position, although the scan chain on the right can satisfy the Max bit requirement (8 bits) of the first scan chain, it is difficult to obtain two scan chains that satisfy the remaining Max bit requirement no matter how the remaining part of the long chain is cut. In other words, for... Figure 1D The long chain shown cannot be cut into three scan chains that satisfy the three Max bit requirements (2 bits, 3 bits, and 8 bits) without moving or swapping the scan registers.

[0040] It is worth noting that after reordering all scan registers, since the reordered scan registers satisfy the optimal wiring length requirement, any movement or swapping of scan registers will increase the total wiring length. Furthermore, the greater the distance of the movement or swap (the number of scan registers crossed), the greater the increase in the total wiring length. For example... Figure 1E As shown, assuming boxes 1-8 represent sorted scan registers, moving 1 between 2 and 3 will have a shorter cost than moving 1 between 3 and 4; swapping positions 6 and 7 will have a shorter cost than swapping positions 5 and 8. Although allocating a valid scan chain is a prerequisite, minimizing the cost of moving and swapping is also necessary. Therefore, moving scan registers over long distances to satisfy the requirement of allocating a valid scan chain is not advisable.

[0041] In view of this, the present disclosure provides a scan chain optimization method, which can solve or partially solve the above problems to a certain extent.

[0042] Figure 2 A schematic flowchart of an exemplary scan chain optimization method 200 provided in an embodiment of this disclosure is shown. This scan chain optimization method 200 can be used to optimize the wiring length of the scan chain.

[0043] like Figure 2 As shown, the scan chain optimization method 200 may further include the following steps.

[0044] In step 202, multiple initial scan chains to be optimized are determined.

[0045] In this step, the scan chain to be optimized is referred to as the initial scan chain to distinguish it from the optimized scan chain.

[0046] Optionally, a file describing the scan chain structure and optimization constraints can be obtained first, such as a scan.def (Scan Description File) file. This file can include relevant information about the scan chains. For example, the number of scan chains; the category to which each scan chain belongs (e.g., a test-purpose category, generally called a partition); all scan registers contained in each scan chain, the names of the scan registers, the port names of the scan registers, and the type of the scan registers; if the scan register type is memory type, its bit width will be indicated; the start and end points of each scan chain, which indicate the corresponding fixed scan register ports; in other words, the start and end scan registers are fixed and do not participate in repartitioning; the scan chain contains Ordered Sections and the scan registers contained in each Ordered Section.

[0047] Since different scan chain partitions are used for different purposes (e.g., different testing purposes), only multiple scan chains belonging to the same partition are allowed to be repartitioned. In this embodiment, the multiple initial scan chains to be optimized can be multiple scan chains belonging to the same partition.

[0048] In this step, a file containing the physical locations of all scan registers in the multiple initial scan chains to be optimized can also be obtained. This file marks the coordinates of each scan register, and the distance value (the Manhattan distance) between any pair of scan registers can be obtained based on the coordinates for subsequent calculations.

[0049] In step 204, the remaining scan registers of each of the plurality of initial scan chains, excluding the start scan register and the end scan register, are mixed to obtain a scan register set.

[0050] In this step, the start and end scan registers of each initial scan chain are first removed. Then, the remaining scan registers of all initial scan chains are mixed to obtain a set of scan registers. In this set of scan registers, the scan registers no longer carry the markers of their respective scan chains and can be arbitrarily shuffled. It can be understood that the start and end scan registers of each initial scan chain do not participate in the mixing process because their positions are fixed.

[0051] In step 206, the scan registers in the scan register set are sorted based on the scan chain wiring length to obtain a long-chain scan chain.

[0052] In this step, the scan registers in the scan register set can be wired together. This connection is a path that passes through each scan register in the scan register set exactly once. To distinguish it from other scan chains, the chain formed by connecting the scan registers in the scan register set is called a long scan chain, which indicates that the length of the long scan chain is relatively longer than any other scan chain.

[0053] In graph theory, the path constituting the long scan chain is a Hamiltonian path. Since the goal of wiring is to minimize the wiring length, i.e., the path length, this problem can be further reduced to the Traveling Salesman Problem (TSP) in graph theory. Therefore, in this step, based on solving the Traveling Salesman Problem, a path with the minimum path length can be obtained, and then each scan register in the scan register set can be connected based on this path to obtain the long scan chain.

[0054] It is understood that there are many methods and tools for solving the Traveling Salesman Problem, and the embodiments of this disclosure may use, but are not limited to, any existing method for wiring.

[0055] It is important to note that because the connection method within an Ordered Section cannot be changed, the Ordered Section is treated as a whole; that is, the scan registers within an Ordered Section do not participate in the sorting process individually.

[0056] In this way, a sorted long scan chain can be obtained, and the wiring length of the long scan chain is the shortest.

[0057] Next, the scan registers in the long scan chain need to be allocated to each initial scan chain to obtain the optimized scan chain.

[0058] Therefore, in step 208, based on the distance between each scan register in the long scan chain and each initial scan chain in the plurality of initial scan chains, the long scan chain is cut to obtain a plurality of scan chain segments that correspond one-to-one with the plurality of initial scan chains.

[0059] In this step, the distance between each scan register in the long scan chain and each initial scan chain can be used to determine which segment should be cut from the long scan chain and allocated to the corresponding initial scan chain. It can be understood that if the distance from a scan register to an initial scan chain is the shortest, then the scan chain segment cut based on that scan register, when combined with the start and end scan registers of that initial scan chain to form a complete scan chain, will also have a relatively short wiring length. The total wiring length of the multiple scan chains obtained after allocating scan chain segments in this way is also relatively short.

[0060] In some embodiments, the long scan chain is segmented based on the distance between each scan register in the long scan chain and each of the plurality of initial scan chains to obtain a plurality of scan chain segments corresponding one-to-one with the plurality of initial scan chains. This may further include the following steps: Calculate the sum of the distances between each scan register in the long scan chain and the start and end scan registers of each initial scan chain in turn; Based on the sum of the distances, a scan chain segment corresponding to each initial scan chain is determined, and the long scan chain is cut to obtain a scan chain segment corresponding to each initial scan chain.

[0061] In this step, the method of calculating the sum of the distances between the scan register and the start and end scan registers of each initial scan chain can be used to determine which scan register has the shortest distance to which initial scan chain, thus quickly filtering out the scan register with the shortest distance for each initial scan chain.

[0062] It is understandable that, since the physical location of each scan register is known, the distance from any scan register to the starting scan register and the distance from any scan register to the ending scan register can be calculated. Then, by calculating the sum of these distances, the scan register with the smallest sum of distances corresponding to each initial scan chain can be found. A scan chain segment containing this smallest distance is then cut from the long scan chain and assigned to the corresponding initial scan chain. At this point, each scan register in this scan chain segment can be marked with the corresponding initial scan chain to indicate that the scan register in this scan chain segment has been assigned to a specific initial scan chain.

[0063] In some embodiments, calculating the sum of the distances between each scan register in the long scan chain and the start and end scan registers of each initial scan chain may further include the following steps: Determine the number of scan registers corresponding to each initial scan chain; The first target quantity is determined based on the largest number of scan registers; Starting from one end of the long scan chain, traverse the scan registers and sequentially calculate the sum of the distances between the first target number of scan registers and the starting and ending scan registers of each initial scan chain.

[0064] by Figure 3A Taking the three initial scan chains as an example, the number of scan registers corresponding to each initial scan chain is 6, 4, and 4 respectively. During the first cut, the first target number can be determined based on the largest number of scan registers (e.g., 6). Since each initial scan chain only needs to be allocated scan chain segments matching its number, in this embodiment, determining the traversal number based on the largest number of scan registers for each currently allocated initial scan chain (all initial scan chains before the first cut) can reduce the number of traversals required for each cut. Specifically, taking a maximum scan register number of 6 as an example, the first target number is determined to be 6.

[0065] Figure 3B A schematic diagram of an exemplary long-chain scan chain according to an embodiment of the present disclosure is shown. Figure 3B The square boxes represent scan registers, and the letters inside the boxes are the names of the scan registers. This long scan chain is assumed to consist of scan registers from three initial scan chains (excluding the start and end scan registers). The start and end points of each of the three initial scan chains are represented by circles with the same number in the diagram, such as ① representing the start and end points of the first scan chain. The start and end points do not need to be distinguished in the calculation, so the same label can be used. C represents the original number of scan registers in the initial scan chain.

[0066] like Figure 3B As shown, during the first segmentation, the scan registers can be traversed starting from one end of the long scan chain, with the number of traversals being the first target number. For example, starting from scan register a, the sum of the distances between scan registers a~f and the starting and ending scan registers of each initial scan chain is calculated sequentially.

[0067] Further, based on the sum of the distances, determining the scan chain segment corresponding to each initial scan chain, and cutting the long scan chain to obtain the scan chain segment corresponding to each initial scan chain, may further include the following steps: Determine the minimum value among the sums of the distances, and the first target scan register and the first initial scan chain corresponding to the minimum value; Based on the length of the first initial scan chain, a scan chain segment including the first target scan register is cut from the long scan chain as the first scan chain segment corresponding to the first initial scan chain.

[0068] Continue to refer to Figure 3B Assuming that the sum of the distances d1+d2 between scan register b and the start and end scan registers of the first scan chain is the minimum of all distance sums, the first scan chain corresponding to this minimum value can be determined as the first initial scan chain, and scan register b can be determined as the first target scan register.

[0069] Then, based on the length of the first initial scan chain (e.g., 6), a scan chain segment including scan register b can be cut from the long scan chain as the first scan chain segment corresponding to the first initial scan chain. Specifically, since the first initial scan chain includes only 4 scan registers after removing the start and end scan registers, the number of scan registers included in the first scan chain segment is also 4. To ensure that the scan chain segments cut from the long scan chain can be matched one-to-one with the initial scan chain, the calculation can start from the starting position of the current traversal during cutting. For example, with Figure 3B For example, scan registers a~d can be cut into segments to form the first scan chain. Each scan register in this first scan chain segment can be marked with a corresponding tag from the first initial scan chain to indicate that the scan register in this first scan chain segment has been assigned to the first initial scan chain. Furthermore, the first initial scan chain can be marked as assigned and will no longer participate in subsequent calculations.

[0070] In this way, without traversing the entire long scan chain, a first scan chain segment matching the first initial scan chain is obtained.

[0071] Furthermore, in some embodiments, calculating the sum of the distances between each scan register in the long scan chain and the start and end scan registers of each initial scan chain may further include the following steps: Determine the number of scan registers corresponding to each remaining initial scan chain; The second target number is determined based on the maximum number of scan registers corresponding to each of the remaining initial scan chains; Starting from one end of the long chain scan chain after cutting the first scan chain segment, traverse the scan registers and sequentially calculate the sum of the distances between the second target number of scan registers and the start and end scan registers of each remaining initial scan chain.

[0072] Continue to refer to Figure 3A and Figure 3B Since the first initial scan chain has already been allocated to scan chain segments, the second target number can be determined as the number of traversals required for the second cut based on the largest number of scan registers corresponding to each remaining initial scan chain. For example, with Figure 3A For example, we can determine that the quantity of the second objective is 4. Figure 3B As shown, during the second segmentation, the scan registers can be traversed starting from one end of the long scan chain after the first scan chain segment is cut, with the number of traversals being the second target number. For example, starting from scan register e, the sum of the distances between scan registers e~h and the starting and ending scan registers of each remaining initial scan chain is calculated sequentially.

[0073] Furthermore, based on the sum of the distances, a scan chain segment corresponding to each initial scan chain is determined, and the long scan chain is cut to obtain a scan chain segment corresponding to each initial scan chain. This may further include the following steps: Determine the minimum value among the sum of the distances between the second target number of scan registers and the starting and ending scan registers of each remaining initial scan chain, as well as the corresponding second target scan register and second initial scan chain; Based on the length of the second initial scan chain, a scan chain segment including the second target scan register is obtained from the long scan chain after cutting the first scan chain segment, and is used as the second scan chain segment corresponding to the second initial scan chain.

[0074] Continue to refer to Figure 3B Assuming that the sum of the distances between scan register e and the start and end scan registers of the second scan chain is the minimum of all distance sums, the second scan chain corresponding to this minimum value can be determined as the second initial scan chain, and scan register e can be determined as the second target scan register.

[0075] Then, based on the length of the second initial scan chain (e.g., 4), a scan chain segment including scan register e can be cut from the remaining long scan chain as the second scan chain segment corresponding to the second initial scan chain. Specifically, since the second initial scan chain includes only 2 scan registers after removing the start and end scan registers, the number of scan registers contained in the second scan chain segment is also 2. To ensure that the scan chain segments cut from the long scan chain can be matched one-to-one with the initial scan chain, the calculation can start from the beginning position of the current traversal during cutting. For example, with Figure 3B For example, the scan registers e~f can be cut off as the second scan chain segment.

[0076] In this way, without traversing the entire long scan chain, a second scan chain segment matching the second initial scan chain is obtained.

[0077] Next, following the above approach, the long scan chain is cut into segments until all scan chain segments that match the initial scan chain are obtained.

[0078] Understandable. Figure 3A and Figure 3B The examples are merely illustrative. For a chip design, long scan chains are typically very long, so the above approach can significantly improve processing efficiency.

[0079] It should be noted that segmenting the aforementioned long scan chain actually involves allocating scan chain segments from the long scan chain to specific initial scan chains. Assume the long scan chain is composed of N scan chains, with the original number of scan registers in each of the N scan chains being C1, C2, ..., Cn, and their bit widths being L1, L2, ..., Ln. The purpose of this step is to segment the long scan chain into N parts, obtaining N scan chain segments, which in turn form N new scan chains. The set of scan registers in each scan chain is equal to the set of scan registers in its corresponding initial scan chain. This step does not guarantee that the set of bit widths of the new scan chains after segmentation is equal to the set of bit widths of the initial scan chains. Therefore, the bit width of the new scan chains with allocated scan chain segments needs to be validated to ensure that the bit width of each scan chain within the same partition does not exceed the maximum bit of its corresponding initial scan chain.

[0080] In step 210, the multiple scan chain segments are sorted according to the cutting order, and it is determined whether the scan chain bit width corresponding to each scan chain segment meets the bit width requirement.

[0081] In this step, the scan chain segments are first sorted, and then it is determined whether the sum of the bit widths of the scan registers of the new scan chain corresponding to each scan chain segment meets the bit width requirement of the new scan chain (i.e., it cannot exceed the scan chain bit width of the corresponding initial scan chain). Here, to distinguish it from the bit width corresponding to the scan register, the bit width corresponding to the scan chain is called the scan chain bit width, which actually refers to the sum of the bit widths of all scan registers in the scan chain.

[0082] It is understandable that the reason why some new scan chains have a bit width that exceeds the Max bit of the corresponding initial scan chain, resulting in an invalid length, is because there are scan registers with a register quantity of 1, but whose bit width can be greater than 1 bit.

[0083] As mentioned earlier, long scan chains are cut sequentially starting from the end. The scan registers in a long scan chain are arranged according to the shortest wiring length. Therefore, multiple scan chain segments can be sorted according to the cutting order, thereby reducing the movement distance and wiring length cost when moving scan registers between adjacent scan chain segments in subsequent operations.

[0084] like Figure 4A As shown, taking a scan chain segment including segments 1 to 3 as an example, the scan chain segments are arranged sequentially according to the cutting order. Each scan chain segment can have neighboring scan chain segments located before or after it, which are referred to as neighbors here. For example, the next neighbor of segment 1 is segment 2, the previous neighbor of segment 2 is segment 1, the next neighbor of segment 2 is segment 3, the previous neighbor of segment 3 is segment 2, segment 1 is the head, and segment 3 is the tail.

[0085] Since each scan chain segment is assigned to a corresponding initial scan chain, the scan chain bit width of the new scan chain corresponding to the initial scan chain can be calculated based on the start scan register and end scan register of the initial scan chain and all scan registers of the corresponding scan chain segment to determine whether the bit width of the new scan chain meets the bit width requirement.

[0086] by Figure 4A For example, the scan chain width corresponding to segment 1 can be the sum of the bit widths of scan registers a~d, plus the bit widths of the starting and ending scan registers of the initial scan chain corresponding to segment 1. If the scan chain width is greater than the corresponding initial scan chain width, then the scan chain width corresponding to segment 1 does not meet the bit width requirement; otherwise, it meets the bit width requirement.

[0087] In this way, it is possible to determine whether the bit width of the corresponding scan chain segment meets the bit width requirement.

[0088] In step 212, in response to the fact that the scan chain bit width corresponding to any scan chain segment does not meet the bit width requirement, the scan register is moved between adjacent scan chain segments until the scan chain bit width corresponding to all scan chain segments meets the bit width requirement, thereby obtaining multiple optimized target scan chains.

[0089] In this step, by moving the scan register between adjacent scan chain segments to change the scan chain bit width corresponding to each scan chain segment, the use of algorithms in related technologies can be avoided (which sometimes have difficulty obtaining satisfactory results in a finite number of calculations). All target scan chains that meet the bit width requirements can be obtained after a finite number of processing steps, while the loss of wiring length is small.

[0090] In some embodiments, in response to the scan chain bit width corresponding to any scan chain segment not meeting the bit width requirement, the scan register is moved between adjacent scan chain segments until the scan chain bit width corresponding to all scan chain segments meets the bit width requirement, which may further include the following steps: The scan register of the scan chain segment whose scan chain width does not meet the width requirement is moved to the next scan chain segment adjacent to the scan chain segment whose scan chain width does not meet the width requirement, until the scan chain width corresponding to the scan chain segment whose scan chain width does not meet the width requirement meets the width requirement, and then it is determined whether the scan chain width corresponding to the next scan chain segment receiving the scan register meets the width requirement. In response to the scan chain bit width corresponding to the next scan chain segment in the receive scan register not meeting the bit width requirement, the scan register of the next scan chain segment is moved to the next scan chain segment adjacent to the next scan chain segment, until the scan chain bit width corresponding to all scan chain segments meets the bit width requirement.

[0091] by Figure 4B As shown in the example, for multiple arranged scan chain segments 1-3, each segment can be processed sequentially from left to right initially. Figure 4B As shown, starting from segment 1, processing proceeds from left to right until the last segment, segment 3. Each segment's scan chain bit width is checked sequentially to ensure it is greater than the bit width of the corresponding initial scan chain. If the scan chain bit width of segment 1 is less than or equal to the bit width of the initial scan chain, processing continues with segment 2.

[0092] If the scan chain width of segment 1 is greater than the corresponding initial scan chain width, move the scan register in segment 1 to segment 2 until the scan chain width of segment 1 meets the width requirement.

[0093] In some embodiments, to reduce wiring length loss, the scan register closest to segment 2 in segment 1 (i.e., the scan register located at the end) can be moved into segment 2, and the scan register moved into segment 2 can be located at the beginning of segment 2. Figure 4B As shown in the example, the first move can move the scan register d to the beginning of segment 2.

[0094] After moving the scan register once, it can be further determined whether the scan chain bit width corresponding to the current scan chain segment is greater than the bit width of the corresponding initial scan chain. If it is still greater, the scan register is moved again in the above way until the scan chain bit width corresponding to the current scan chain segment is less than or equal to the bit width of the corresponding initial scan chain.

[0095] For example, with Figure 4B Taking segment 1 as an example, if the scan chain width corresponding to segment 1 is greater than the width of the corresponding initial scan chain, then starting from its tail, that is, from scan register d, the scan register is moved forward sequentially according to the access order of d, c, b, a, and moved to the head of the next neighbor, that is, segment 2. After any move, if it is found that the current scan chain width is no longer greater than the width of the initial scan chain, then segment 1 is stopped, segment 2 is processed, and the above operation is repeated until segment 3 is processed.

[0096] Considering both wiring length loss and meeting bit width requirements, some embodiments of this disclosure classify the scan registers and set a movement priority for each class. This allows the scan registers to be moved according to the movement priority, thereby improving processing efficiency and optimization.

[0097] Alternatively, if the scan registers in the scan chain are considered as nodes and classified, they can be divided into the following types of nodes: A scan register with a width of 1 bit that does not belong to an ordered set, that is, a basic register that does not exist in any OrderedSection, can also be called a basic node. Scan registers with a bit width greater than 1 bit that do not belong to an ordered set, that is, memory (mem) that does not exist in any OrderedSection. An ordered set of scan registers with a bit width of 1 bit and scan registers with a bit width greater than 1 bit, that is: an Ordered Section containing basic registers and memory; The Ordered Section contains only the basic registers.

[0098] It is understandable that each scan chain segment may or may not contain the above four types of nodes.

[0099] For the aforementioned types of nodes, the order of movement priority is as follows: 1-bit scan registers not belonging to the ordered set; ordered sets containing both 1-bit and larger-than-1-bit scan registers; and larger-than-1-bit scan registers not belonging to the ordered set. In other words, when moving scan registers, nodes are moved according to their movement priority. It can be understood that since the Ordered Section cannot be changed internally, it needs to be moved as a whole.

[0100] Furthermore, in some embodiments, moving the scan register between adjacent scan chain segments includes: The move priority of each scan register is determined based on its type; Scan registers with higher move priority are moved before scan registers with lower move priority.

[0101] Specifically, when moving, movement can be done on a node-by-node basis. In other words, if the scan register to be moved belongs to the Ordered Section, then the entire Ordered Section is moved.

[0102] The order of node movement is as follows: first move the basic nodes (scan registers with a width of 1 bit that do not belong to the ordered set), after all such nodes have been moved, move the Ordered Section containing the basic registers and memory, and after all such nodes have been moved, move the memory (mem) that does not belong to any Ordered Section.

[0103] Ordered sections containing only basic nodes do not need to be moved, because these types of nodes are unlikely to cause the scan chain to be too wide. Therefore, after moving the above three types of nodes, the current scan chain width will necessarily be less than or equal to the corresponding initial scan chain width.

[0104] Furthermore, in some embodiments, in response to any scan chain segment's corresponding scan chain bit width not meeting the bit width requirement, the scan register is moved between adjacent scan chain segments until the scan chain bit widths corresponding to all scan chain segments meet the bit width requirement, further comprising: In response to the fact that the next scan chain segment or the next-next scan chain segment is the last scan chain segment in the sorted sequence of the plurality of scan chain segments, the movement direction is reversed, and the scan register of the next scan chain segment or the next-next scan chain segment is moved to the previous scan chain segment adjacent to the next scan chain segment or the next-next scan chain segment, until the scan chain bit width corresponding to the next scan chain segment or the next-next scan chain segment meets the bit width requirement, and it is determined whether the scan chain bit width corresponding to the previous scan chain segment receiving the scan register meets the bit width requirement; In response to the fact that the scan chain bit width corresponding to the previous scan chain segment in the receive scan register does not meet the bit width requirement, the scan register of the previous scan chain segment continues to be moved to the next scan chain segment adjacent to the previous scan chain segment, until the scan chain bit width corresponding to all scan chain segments meets the bit width requirement.

[0105] In some cases, when processing the last scan chain segment, the scan chain bit width corresponding to this scan chain segment does not meet the bit width requirement. However, this is the last scan chain segment. In this case, it is necessary to change the movement direction of the scan register and move the scan register of the current scan chain segment to the previous scan chain segment so that the scan chain bit width corresponding to the current scan chain segment meets the bit width requirement.

[0106] For example, with Figure 4B For example, nodes can be moved from right to left using the same process described above, except that the head node of the segment is moved to the tail of its preceding neighbor.

[0107] Repeat the above process until the scan chain bit widths corresponding to all scan chain segments meet the bit width requirements.

[0108] It is understandable that in some cases, when processing the first scan chain segment, the scan chain bit width corresponding to that segment may not meet the bit width requirement. However, since this is the first scan chain segment, it is necessary to reverse the movement direction of the scan register again, moving the scan register of the current scan chain segment to the next scan chain segment so that the scan chain bit width corresponding to the current scan chain segment meets the bit width requirement. This process is similar to the previous one and will not be repeated here.

[0109] The inventors of this disclosure have discovered that after three processing steps—from left to right (or from front to back), from right to left (or from back to front), and then from left to right (or from front to back)—it can be guaranteed that the scan chain bit width corresponding to each scan chain segment meets the bit width requirement.

[0110] In these three node moves, the first two moves locate suitable scan chain positions for the high-bit-width memory to avoid unsolvable situations. The third move only involves the movement of the basic nodes. During the third move, redundant scan chains of basic nodes will be assigned to scan chains with a bit width smaller than the original bit width. Therefore, using the above method, bit width processing can be completed in a maximum of three processes, greatly improving processing efficiency.

[0111] Furthermore, if no node moves during any of the three moves, the processing can be terminated early because the scanned chain width is no longer too large and no further processing is needed.

[0112] After obtaining the required scan chain segments, each scan chain segment is combined with the start scan register and end scan register of the corresponding initial scan chain to form a target scan chain. This results in multiple target scan chains that correspond one-to-one with the multiple initial scan chains, and the scan chain bit width of these target scan chains all meet the bit width requirements.

[0113] As can be seen from the above embodiments, some embodiments of the scan chain optimization method provided in this disclosure, by mixing and then sorting all scan chains belonging to the same partition during the repartition process, can perform global routing optimization, which is beneficial to reducing routing length. Through the implementation of the cutting process, the scan register is dynamically allocated according to the start and end points of the scan chain, taking into account the routing length of all scan chains. Furthermore, through the three-movement bit width problem handling method, the bit width problem can be solved in one go for any type of node in any distribution in the scan chain, regardless of the size of the memory bit width. This avoids the problem of repeated adjustments to obtain a feasible solution through swapping and moving, which makes the process difficult to converge. At the same time, it can ensure that for the originally adjacent basic nodes, they are still in adjacent positions or inserted into the middle of the memory or Ordered Section before and after the above-mentioned movement process, which is beneficial to reducing the generation of routing costs.

[0114] It should be noted that the method of this disclosure embodiment can be executed by a single device, such as a computer or server. The method of this embodiment can also be applied to a distributed scenario, where multiple devices cooperate to complete the task. In such a distributed scenario, one of these devices may execute only one or more steps of the method of this disclosure embodiment, and the multiple devices will interact with each other to complete the method described.

[0115] It should be noted that the above description describes some embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0116] This disclosure also provides a computer device for implementing the scan chain optimization method described above. Figure 5 A schematic diagram of the hardware structure of an exemplary computer device 500 provided in an embodiment of this disclosure is shown.

[0117] like Figure 5 As shown, the computer device 500 may include: a processor 502, a memory 504, a network interface 506, a peripheral interface 508, and a bus 510. The processor 502, memory 504, network interface 506, and peripheral interface 508 are interconnected within the computer device 500 via the bus 510.

[0118] Processor 502 may be a central processing unit (CPU), image processor, neural network processor (NPU), microcontroller (MCU), programmable logic device, digital signal processor (DSP), application-specific integrated circuit (ASIC), or one or more integrated circuits. Processor 502 can be used to perform functions related to the techniques described in this disclosure. In some embodiments, processor 502 may also include multiple processors integrated as a single logic component. For example, such as... Figure 5 As shown, processor 502 may include multiple processors 502a, 502b and 502c.

[0119] Memory 504 can be configured to store data (e.g., instructions, computer code, etc.). Figure 5As shown, the data stored in memory 504 may include program instructions (e.g., one or more programs for implementing the scan chain optimization method of embodiments of this disclosure) and data to be processed (e.g., the memory may store configuration files of other modules, etc.). Processor 502 may also access the program instructions and data stored in memory 504 and execute the program instructions to operate on the data to be processed. Memory 504 may include volatile or non-volatile storage devices. In some embodiments, memory 504 may include random access memory (RAM), read-only memory (ROM), optical disk, magnetic disk, hard disk, solid-state drive (SSD), flash memory, memory stick, etc.

[0120] Network interface 506 can be configured to provide communication with other external devices to computer device 500 via a network. This network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, Near Field Communication (NFC), etc.), a cellular network, the Internet, or a combination thereof. It is understood that the type of network is not limited to the specific examples described above.

[0121] The peripheral interface 508 can be configured to connect the computer device 500 to one or more peripheral devices to enable information input and output. For example, peripheral devices may include input devices such as keyboards, mice, touchpads, touch screens, microphones, and various sensors, as well as output devices such as displays, speakers, vibrators, and indicator lights.

[0122] Bus 510 can be configured to transfer information between various components of computer device 500 (such as processor 502, memory 504, network interface 506, and peripheral interface 508), such as internal buses (e.g., processor-memory bus), external buses (USB port, PCI-E bus), etc.

[0123] It should be noted that although the architecture of the computer device 500 described above only shows the processor 502, memory 504, network interface 506, peripheral interface 508, and bus 510, in specific implementations, the architecture of the computer device 500 may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the architecture of the computer device 500 described above may only include the components necessary for implementing the embodiments of this disclosure, and does not necessarily include all the components shown in the figures.

[0124] Based on the same inventive concept, corresponding to any of the above embodiments, this disclosure also provides a non-volatile computer-readable storage medium containing a computer program, which, when executed by one or more processors, causes the one or more processors to perform the scan chain optimization method.

[0125] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0126] The computer program stored in the storage medium of the above embodiments is used to cause the one or more processors to execute the scan chain optimization method as described in any of the above embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0127] Based on the same inventive concept, corresponding to the scan chain optimization method in any of the above embodiments, this disclosure also provides a computer program product, which includes one or more computer programs. In some embodiments, the one or more computer programs are executable by one or more processors to cause the one or more processors to perform the scan chain optimization method. Corresponding to the execution entity for each step in each embodiment of the scan chain optimization method, the processor executing the corresponding step may belong to the corresponding execution entity.

[0128] The computer program products of the above embodiments are used to cause the processor to execute the scan chain optimization method as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0129] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure (including the claims) is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this disclosure as described above, which are not provided in detail for the sake of brevity.

[0130] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this disclosure, the provided drawings may or may not show well-known power / ground connections to integrated circuit (IC) chips and other components. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this disclosure, and this also takes into account the fact that the details of implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this disclosure will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this disclosure, it will be apparent to those skilled in the art that the embodiments of this disclosure can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0131] Although this disclosure has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0132] This disclosure is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A scan chain optimization method, characterized in that, include: Identify multiple initial scan chains to be optimized; The scan registers remaining in each of the plurality of initial scan chains, excluding the start scan register and the end scan register, are mixed to obtain a scan register set; Based on the scan chain wiring length, the scan registers in the scan register set are sorted to obtain a long-chain scan chain; Based on the distance between each scan register in the long scan chain and each initial scan chain in the plurality of initial scan chains, the long scan chain is cut to obtain a plurality of scan chain segments that correspond one-to-one with the plurality of initial scan chains; The multiple scan chain segments are sorted according to the cutting order, and it is determined whether the scan chain bit width corresponding to each scan chain segment meets the bit width requirement. In response to any scan chain segment whose scan chain bit width does not meet the bit width requirement, the scan register is moved between adjacent scan chain segments until the scan chain bit width of all scan chain segments meets the bit width requirement, thus obtaining multiple optimized target scan chains.

2. The method as described in claim 1, characterized in that, Based on the distance between each scan register in the long scan chain and each of the plurality of initial scan chains, the long scan chain is segmented to obtain a plurality of scan chain segments that correspond one-to-one with the plurality of initial scan chains, including: Calculate the sum of the distances between each scan register in the long scan chain and the start and end scan registers of each initial scan chain in turn; Based on the sum of the distances, a scan chain segment corresponding to each initial scan chain is determined, and the long scan chain is cut to obtain a scan chain segment corresponding to each initial scan chain.

3. The method as described in claim 2, characterized in that, The process involves sequentially calculating the sum of distances between each scan register in the long scan chain and the starting and ending scan registers of each initial scan chain, including: determining the number of scan registers corresponding to each initial scan chain; determining a first target number based on the largest number of scan registers; traversing the scan registers starting from one end of the long scan chain and sequentially calculating the sum of distances between the first target number of scan registers and the starting and ending scan registers of each initial scan chain. Based on the sum of the distances, a scan chain segment corresponding to each initial scan chain is determined, and the long scan chain is cut to obtain a scan chain segment corresponding to each initial scan chain, including: determining the minimum value in the sum of the distances and the first target scan register and the first initial scan chain corresponding to the minimum value; based on the length of the first initial scan chain, a scan chain segment including the first target scan register is cut from the long scan chain as the first scan chain segment corresponding to the first initial scan chain.

4. The method as described in claim 3, characterized in that, The calculation process includes: sequentially calculating the sum of distances between each scan register in the long scan chain and the start and end scan registers of each initial scan chain; determining the number of scan registers corresponding to each remaining initial scan chain; determining a second target number based on the maximum number of scan registers corresponding to each remaining initial scan chain; traversing the scan registers starting from one end of the long scan chain after cutting the first scan chain segment, and sequentially calculating the sum of distances between the second target number of scan registers and the start and end scan registers of each remaining initial scan chain; Based on the sum of the distances, a scan chain segment corresponding to each initial scan chain is determined, and the long scan chain is cut to obtain a scan chain segment corresponding to each initial scan chain. This also includes: determining the minimum value among the sum of the distances between the second target number of scan registers and the starting and ending scan registers of the remaining initial scan chains, as well as the corresponding second target scan register and second initial scan chain; based on the length of the second initial scan chain, a scan chain segment including the second target scan register is cut from the long scan chain after cutting the first scan chain segment, as the second scan chain segment corresponding to the second initial scan chain.

5. The method as described in claim 1, characterized in that, In response to any scan chain segment's scan chain bit width not meeting the bit width requirement, the scan register is moved between adjacent scan chain segments until the scan chain bit widths of all scan chain segments meet the bit width requirement, including: The scan register of the scan chain segment whose scan chain width does not meet the width requirement is moved to the next scan chain segment adjacent to the scan chain segment whose scan chain width does not meet the width requirement, until the scan chain width corresponding to the scan chain segment whose scan chain width does not meet the width requirement meets the width requirement, and then it is determined whether the scan chain width corresponding to the next scan chain segment receiving the scan register meets the width requirement. In response to the scan chain bit width corresponding to the next scan chain segment in the receive scan register not meeting the bit width requirement, the scan register of the next scan chain segment is moved to the next scan chain segment adjacent to the next scan chain segment, until the scan chain bit width corresponding to all scan chain segments meets the bit width requirement.

6. The method as described in claim 5, characterized in that, Moving the scan register between adjacent scan chain segments includes: The move priority of each scan register is determined based on its type; Scan registers with higher move priority are moved before scan registers with lower move priority; The order of the moving priority is as follows: scan registers with a bit width of 1 that do not belong to the ordered set, ordered sets containing scan registers with a bit width of 1 and scan registers with a bit width greater than 1, and scan registers with a bit width greater than 1 that do not belong to the ordered set.

7. The method as described in claim 5 or 6, characterized in that, In response to any scan chain segment's scan chain bit width not meeting the bit width requirement, the scan register is moved between adjacent scan chain segments until the scan chain bit widths of all scan chain segments meet the bit width requirement. This also includes: In response to the fact that the next scan chain segment or the next-next scan chain segment is the last scan chain segment in the sorted sequence of the plurality of scan chain segments, the movement direction is reversed, and the scan register of the next scan chain segment or the next-next scan chain segment is moved to the previous scan chain segment adjacent to the next scan chain segment or the next-next scan chain segment, until the scan chain bit width corresponding to the next scan chain segment or the next-next scan chain segment meets the bit width requirement, and it is determined whether the scan chain bit width corresponding to the previous scan chain segment receiving the scan register meets the bit width requirement; In response to the fact that the scan chain bit width corresponding to the previous scan chain segment in the receive scan register does not meet the bit width requirement, the scan register of the previous scan chain segment continues to be moved to the next scan chain segment adjacent to the previous scan chain segment, until the scan chain bit width corresponding to all scan chain segments meets the bit width requirement.

8. A computer device, characterized in that, It includes one or more processors, memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, and the one or more programs include instructions for performing the method of any one of claims 1 to 7.

9. A non-volatile computer-readable storage medium containing a computer program, characterized in that, When the computer program is executed by one or more processors, the one or more processors perform the method according to any one of claims 1 to 7.

10. A computer program product, characterized in that, It includes one or more computer programs that, when executed by one or more processors, implement the method as described in any one of claims 1 to 7.

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