An Embedded SoC-Level Real-Time Monitoring and Analysis Device

Abstract

This invention discloses an embedded SoC-level real-time monitoring and analysis device, comprising a bus comparator, a system event counter, and a control register set. The bus comparator acquires access signals from the address bus, data bus, and instruction bus in real time and compares them with preset matching rules. Upon matching, it generates a trigger signal to drive the event status register to record, output interrupt signals, or debug signals, and serves as the input event for the system event counter. The system event counter monitors various events generated during operation, and generates a trigger signal when the monitoring result equals a preset reference value. The control register set configures the matching conditions of the bus comparator, sets the counting mode of the system event counter, and reads the comparison status, event counting results, and related monitoring information through the bus interface. This invention introduces a configurable event capture mechanism and multiple counting modes at the hardware level, reducing reliance on software debugging and improving the real-time performance of monitoring and analysis.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, specifically, it relates to an embedded SoC-level real-time monitoring and analysis device. Background Technology

[0002] As the scale and complexity of SoC (System on Chip) designs continue to increase, the monitoring of the operational status, event statistics, and performance analysis of the internal functional modules of the chip play a crucial role in system optimization, power management, and reliability assessment. Existing technologies mainly rely on software debugging methods or simple hardware monitoring mechanisms, but these have certain limitations in practical applications.

[0003] In software debugging, a common approach is to collect event data through interrupts or polling mechanisms. However, this method has the following drawbacks: First, under high load or high-speed operation scenarios, the software acquisition process is prone to delays or data loss, making it difficult to accurately reflect the real-time operating status of the system. Second, for high-frequency events and parallel-executed functional modules, the software approach cannot guarantee the integrity and accuracy of monitoring data. Third, software monitoring requires processor computing resources and storage space, thereby increasing system overhead and power consumption, which adversely affects performance optimization and power management.

[0004] In hardware debugging, existing technologies typically employ fixed breakpoints or register monitoring. These methods also have limitations: firstly, their trigger condition configuration capabilities are limited, making it difficult to flexibly adapt to complex application scenarios; secondly, monitoring multiple event combinations simultaneously is challenging, and their real-time statistical capabilities for high-frequency events are insufficient. Furthermore, these methods generally fail to achieve non-intrusive debugging and can easily impact the normal operation of the system.

[0005] To address the aforementioned issues, existing technologies have proposed several improvement solutions, such as adding hardware buffers, optimizing register design, or enhancing monitoring capabilities through software algorithms. However, due to the complex structure of SoC systems and frequent interactions between modules, these methods still struggle to achieve a balance between system real-time performance, monitoring accuracy, and low power consumption. Therefore, existing technologies still have significant shortcomings in achieving hardware-level real-time event capture, counting, and analysis. There is an urgent need for a flexible, configurable, low-overhead, and high-real-time monitoring and analysis device that can meet the performance optimization, debugging, and reliability analysis requirements of high-performance SoC systems without affecting normal system operation. Summary of the Invention

[0006] This invention addresses the technical problems of insufficient real-time performance in software debugging, high system resource consumption, and limited hardware monitoring functions in existing technologies. It provides an embedded SoC-level real-time monitoring and analysis device. By introducing a configurable event capture mechanism and multiple counting modes at the hardware level, it reduces reliance on software debugging methods, improves the practicality of monitoring and analysis, and enables non-intrusive debugging operations. This allows for monitoring and performance statistics of events within SoC modules without interfering with normal system operation. It can be widely applied in high-performance embedded processors, digital signal processors, and microcontrollers to monitor and analyze the operating status of performance-critical modules.

[0007] The present invention is implemented using the following technical solutions:

[0008] An embedded SoC-level real-time monitoring and analysis device is proposed, comprising:

[0009] The bus comparator is used to collect access signals from the address bus, data bus, and instruction bus inside the SoC in real time, compare the collected access signals with preset matching rules, and generate a trigger signal when the access signal matches the preset matching rules. The trigger signal is used to drive the event status register to record, output interrupt signals or debug signals, and serve as the input event for the system event counter.

[0010] The system event counter is used to monitor various events generated during the operation of the SoC, and generates the trigger signal when the monitoring result equals the preset reference value;

[0011] The control register group is used to configure the matching conditions of the bus comparator, set the counting mode of the system event counter, and read the comparison status, event counting results and related monitoring information through the bus interface.

[0012] In some embodiments of the present invention, the device consists of N identical bus comparators, M identical system event counters, and a control register group;

[0013] N parallel comparison events can be directly used as input events for M system event counters; or, they can be input to P OR gates or Q AND gates respectively, and the input combinations can be configured through the control register group to generate P OR gate events or Q AND gate events.

[0014] In some embodiments of the present invention, the bus comparator connects the bus to be captured and the comparison mode to the comparison module through a multiplexer, and both the bus selection and the comparison mode selection are configured by a control register group.

[0015] In the comparison module, five comparison modes are implemented based on user-defined reference values ​​and masks: (bus|mask) == (reference value|mask), (bus|mask) > (reference value|mask), (bus|mask) < (reference value|mask), (bus|mask) ≥ (reference value|mask), and (bus|mask) ≤ (reference value|mask). Through range matching and mask matching in the comparison module, a comparison event, output interrupt, or debug signal is generated after a successful comparison.

[0016] In some embodiments of the present invention, the system event counter corresponds to a start event, a stop event, a count event, and a reset event. The events are selected by an event gating unit, and an inverted gating unit is set for each event. The start event, stop event, count event, and reset event are configured as inputs to the counter device. When preset conditions are met, a trigger signal is generated to output the counter event, generate an interrupt, or provide a debugging signal.

[0017] The control register group configures start event strobe, start inversion strobe, start synchronization strobe, stop event strobe, stop inversion strobe, stop synchronization strobe, count event strobe, count inversion strobe, count synchronization strobe, reset event strobe, reset inversion strobe, reset synchronization strobe, and event mode. Among these, the start event strobe, stop event strobe, count event strobe, and reset event strobe are used to select the corresponding event as input from the total input events. The total input events include comparison events, OR gate events, AND gate events, counter events, peripheral events, and interrupt events.

[0018] By configuring the inversion gating register and the synchronization gating register, the event signal is logically inverted and synchronized to the working clock of the system event counter;

[0019] For counting events, when the event mode register is configured to be 1, the counting is performed in edge trigger count mode; when the event mode register is configured to be 0, the counting is performed in level duration mode.

[0020] In some embodiments of the present invention, the counter device consists of a counting module 1 and a counting module 2, and is configured through a register group; the register group includes a counting reference value, a global working enable, a free counting enable, a start / stop counting enable, a reset event enable, a global reset, a matching value reset enable, and an accumulation count enable;

[0021] Counting module 1 connects to counting events, reset events, and the register group to implement the counting function in the free counting enabled mode; counting module 2 connects to start events, stop events, counting events, reset events, and the register group to implement the counting function in the start-stop counting enabled mode.

[0022] When the count value of the counting module equals the count reference value, the counting module can generate a counter event and output an interrupt or debug signal.

[0023] In some embodiments of the present invention, a register value of 1 defaults to an enabled startup state; a count reference value of 0 indicates no participation in matching; free counting enable and start / stop counting enable control the two counting modules to operate in corresponding modes, wherein in free counting mode, the operation is determined solely by the counting event and event mode register configuration; in start / stop counting mode, the counting module count value depends on the start event, stop event, counting event, and event mode register configuration; when the reset event enable is 1, the counter device is reset to its initial state due to the reset event, and a value of 0 has no effect; when the global reset is 1, the counter device is reset to its initial state, and a value of 0 has no effect; when the matching value reset enable is 1, a reset to the initial state is triggered when the counting module count value equals the count reference value, and a value of 0 has no effect, while the counting module count value continues to accumulate; when the accumulation count enable is 1, a reset to the initial state is triggered if a stop event is triggered at this time, and a value of 0 has no effect.

[0024] In some embodiments of the present invention, the counter device states include: idle state, counting wait state, counting state, and matched state; the state machine includes:

[0025] The counter is initially in an idle state until a waiting event is triggered, after which it enters a counting waiting state. In the counting waiting state, if a start counting event is triggered, it enters the counting state; if a reset event 1 is triggered, it returns to the idle state. In the counting state, the counting module performs counting operations. If a stop counting event is triggered, the counting module stops counting and returns to the counting waiting state. If a reset event 2 occurs, it returns to the idle state. If a matching event is reached, it enters the matching state. In the matching state, it indicates that the counting result meets the matching condition and remains in this state until a reset event 3 causes it to return to the idle state. Among these, the counting module 2 has fewer free counting paths to the counting state compared to the counting module 1.

[0026] In some embodiments of the present invention, the state transition event combinations of counting module 1 and counting module 2 respectively include:

[0027] Under counting module 1,

[0028] The logic for the free counting event is as follows: (Global work enable == 1 && Free count enable == 0 && Start / stop count enable == 0).

[0029] The logic for waiting for counting events consists of (Global Work Enable == 1 && Free Count Enable == 1 && Start / Stop Count Enable == 0);

[0030] Start counting event logic (count event == 1);

[0031] The logic for stopping events is (count events == 0);

[0032] The matching event composition logic is: (counting module count value == counting reference value) && (counting reference value ≠ 0);

[0033] The logic for reset event 1 is: (Global Reset == 1) || ((Reset Event Enable == 1) && (Reset Event == 1)).

[0034] The logic for reset event 2 is: (Global Reset == 1) || ((Reset Event Enable == 1) && (Reset Event == 1)) || (Counter Module Count Value Overflow).

[0035] The logic for reset event 3 is: (Global Reset == 1) || ((Reset Event Enable == 1) && (Reset Event == 1)) || (Match Value Reset Enable == 1).

[0036] Under counting module 2,

[0037] The logic for waiting for counting events consists of: (Global work enable == 1 && Free count enable == 0 && Start / stop count enable == 1).

[0038] The logic for starting the counting event is as follows: (Start event == 1 && Stop event == 0 && Counting event == 1).

[0039] The logic for stopping the counting event is: ((Accumulated count enable == 1 && Stop counting == 1) || Counting event == 0);

[0040] The matching event composition logic is: (counting module count value == counting reference value) && (counting reference value ≠ 0);

[0041] The logic for reset event 1 is: (Global Reset == 1) || ((Reset Event Enable == 1) && (Reset Event == 1)).

[0042] The logic for reset event 2 is as follows: (Global Reset == 1) || ((Reset Event Enable == 1) && (Reset Event == 1)) || (Counter Module Count Value Overflow) || (Accumulated Count Enable == 0 && Stop Count == 1);

[0043] The logic for reset event 3 is: (Global Reset == 1) || ((Reset Event Enable == 1) && (Reset Event == 1)) || (Matching Value Reset Enable == 1).

[0044] In some embodiments of the present invention, the counting modes of the system event counter device under different configurations of the control register include:

[0045] When (Global Working Enable == 1 && Free Count Enable == 0 && Start / Stop Count Enable == 0), in this mode, the counter counts freely and is used as a timer to record clock cycles.

[0046] When (Global Working Enable == 1 && Free Count Enable == 1), in this mode, the count value of the counting module depends on the condition of (Count Event == 1), and records the duration period of the event level;

[0047] When (Global Work Enable == 1 && Free Count Enable == 1 && Event Mode == 1), in this mode, the count value of the counting module depends on the condition (Count Event == 1), and records the number of times the event is triggered;

[0048] When (Global Working Enable == 1 && Start Stop Count Enable == 1), in this mode, the count value of the counting module depends on the situation between the start and stop events (count event == 1), and records the duration period of the event level;

[0049] When (Global Work Enable == 1 && Start Stop Count Enable == 1 && Event Mode == 1), in this mode, the count value of the counting module depends on the situation between the start and stop events (count events == 1), recording the number of times the event is triggered.

[0050] In some embodiments of the present invention, the reset modes of the system event counter device under different configurations of the control register include:

[0051] When (Global Reset == 1), the reset is a global reset, which returns the counting module to the idle state;

[0052] When (Reset Event Enable == 1), if (Reset Event == 1), a reset is triggered, causing the counting module to return to the idle state;

[0053] When (Matching value reset enable == 1), if (Counting module value == Counting reference value), a reset is triggered, causing the counting module to return to the idle state;

[0054] When (Accumulation Count Enable == 1), it only applies when (Global Working Enable == 1 && Start / Stop Count Enable == 1). If (Stop Event == 1), a reset is triggered, causing the counting module to return to the idle state.

[0055] Compared with existing technologies, the advantages and positive effects of this invention are as follows: By integrating a hardware-level real-time monitoring and analysis device within the SoC, this invention enables real-time capture and statistics of address bus, data bus, instruction bus, and system events. It can complete monitoring and analysis operations without interfering with normal system operation, reducing reliance on software debugging methods and improving the real-time performance and reliability of monitoring. Furthermore, the configurable logic units reduce system resource overhead, while supporting flexible event capture and counting mechanisms to adapt to different application requirements, thus playing a role in performance optimization, power management, and reliability assessment.

[0056] Other features and advantages of the present invention will become clearer after reading the detailed description of the embodiments of the present invention in conjunction with the accompanying drawings. Attached Figure Description

[0057] Figure 1 This is a schematic diagram of the interface of the embedded SoC-level real-time monitoring and analysis device proposed in this invention at the SoC level.

[0058] Figure 2 This is a schematic diagram of the internal structure and interface of the embedded SoC-level real-time monitoring and analysis device proposed in this invention.

[0059] Figure 3 This is a schematic diagram of the internal structure and interface of a bus comparator device according to a specific embodiment of the present invention;

[0060] Figure 4 This is a schematic diagram of the internal structure and interface of the system event counter device according to a specific embodiment of the present invention;

[0061] Figure 5 This is an appendix to a specific embodiment of the present invention. Figure 4 A schematic diagram of the internal counter device interface of the system event counter device;

[0062] Figure 6 This is an appendix to a specific embodiment of the present invention. Figure 5 A schematic diagram of the state machine that the counting module 1 in the counter device needs to satisfy;

[0063] Figure 7 This is an appendix to a specific embodiment of the present invention. Figure 5 A schematic diagram of the state machine that the counting module 2 in the counter device needs to satisfy. Detailed Implementation

[0064] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0065] The core of the embedded SoC-level real-time monitoring and analysis device proposed in this invention lies in integrating a hardware-level monitoring and analysis device inside the SoC. This device is used to capture and perform statistical analysis of the data bus, address bus, instruction bus, and system events inside the SoC in real time and in various counting modes without affecting the normal operation of the system. This reduces the dependence on software debugging tools and improves the real-time performance and reliability of monitoring.

[0066] Specifically, the device of the present invention consists of three parts: a bus comparator, a system event counter, and a control register group.

[0067] like Figure 3 As shown, the bus comparator is used to collect and compare the address bus, data bus and instruction bus access signals inside the SoC in real time. When the bus comparator detects a bus access behavior that meets the preset matching rules, it generates a trigger signal. The trigger signal is used to drive the event status register to record, output interrupt signal or debug signal, and serve as the input event for the system event counter, realizing the hardware linkage function of event capture and statistics.

[0068] The bus comparator supports multiple matching modes, including range matching, mask matching, and multi-condition combination matching, and can perform combined comparisons of address, data, and instruction signals according to user-preset logical relationships.

[0069] The bus comparator also has multi-channel parallel comparison capability, which can be used to monitor multiple bus transactions at the same time, thereby meeting the real-time capture requirements of high-frequency access events.

[0070] like Figure 4 As shown, the system event counter is used to statistically analyze various events generated during the operation of the SoC. When the monitoring result is equal to the preset reference value, a trigger signal is generated. The trigger signal is used to drive the event status register to record, output interrupt signal or debug signal, and serve as the input event for the system event counter.

[0071] The system event counter supports multiple counting modes, including cumulative counting, time window counting, and condition-triggered counting, to count the number of times an event occurs, its duration, and the interval between events.

[0072] The system event counter supports event types including but not limited to cache hit, cache miss, interrupt request count, data transfer completion flag, and instruction execution count.

[0073] like Figure 5As shown, the control register group interacts with standard on-chip bus interfaces (such as APB, Advanced Peripheral Bus) through internal SoC registers to configure and exchange information about the functional devices of this invention. Its functions include configuring the matching conditions of the bus comparator, setting the counting mode of the system event counter, and reading the comparison status, event counting results, and related monitoring information through the bus interface. Through the settings of this register group, users can flexibly adjust and manage the monitoring scheme without interfering with the normal operation of the SoC.

[0074] The following describes specific embodiments, with reference to the appendix. Figure 1 To be continued Figure 7 This invention provides a detailed description of the embedded SoC-level real-time monitoring and analysis device proposed in this paper.

[0075] like Figure 1 The diagram shows the interface of the embedded SoC-level real-time monitoring and analysis device of this invention at the SoC level. The device exists as an independent functional unit within the SoC, accessing the address bus, data bus, and instruction bus through the processor core; accessing interrupt events through the interrupt debugging device; and accessing peripheral events through other peripheral devices. The on-chip interconnect bus provides the register access and control interface for interaction between the device and the user. Simultaneously, the interrupt debugging device responds to interrupt / debugging signals generated by the device and feeds back the processing results to the processor core.

[0076] like Figure 2 The diagram shows the internal structure and interface of the embedded SoC-level real-time monitoring and analysis device of this invention. The device mainly consists of eight identical bus comparator devices, four identical system event counter devices, and a control register group. Figure 1The address bus, data bus, and instruction bus at the SoC level are connected to eight identical bus comparator devices. Through the internal logic of each bus comparator device, a maximum of eight parallel comparison events can be generated. If the input bus meets the configuration logic of the bus comparator device, a trigger signal can be generated, which can be used to drive event status recording, output interrupts, or debug signals, and can also serve as input events for the system event counter. These eight parallel comparison events can be directly used as input events for the system event counter device, or they can be input to four OR gates or four AND gates respectively. The user configures the input combinations through control registers to generate four OR gate events and four AND gate events. These combined events can also be connected to the system event counter device and used to drive event status recording, output interrupts, or debug signals. The eight comparison events, four OR gate events, four AND gate events, four counter events generated by the four identical system event counter devices, peripheral events, and interrupt events constitute the total input event connected to the system event counter device. The counting mode of the system event counter device is configured by the user through the control register. When the count value reaches the preset reference value, it can generate a trigger signal to drive event status recording, output interrupt or provide debugging signal, and can also be used as the input event of the system event counter.

[0077] like Figure 3 The diagram shows the internal structure and interface of the bus comparator device in a specific embodiment of the present invention. The bus comparator device first connects the bus to be captured and the comparison mode to the comparison module via a multiplexer. Both bus selection and comparison mode selection are configured by a control register. The comparison module connects a user-defined reference value and a mask, supporting five comparison modes: (bus|mask) == (reference value|mask), (bus|mask) > (reference value|mask), (bus|mask) < (reference value|mask), (bus|mask) ≥ (reference value|mask), and (bus|mask) ≤ (reference value|mask). Through the comparison module, range matching and mask matching can be achieved. A successful comparison can generate a comparison event, output an interrupt, or provide a debugging signal.

[0078] like Figure 4The diagram shows the internal structure and interface of the system event counter device in a specific embodiment of the present invention. The total input events of this system event counter device include 8 comparison events, 4 OR gate events, 4 AND gate events, 4 counter events, peripheral events, and interrupt events. The system event counter device is configured with start event strobe, start inversion strobe, start synchronization strobe, stop event strobe, stop inversion strobe, stop synchronization strobe, count event strobe, count inversion strobe, count synchronization strobe, reset event strobe, reset inversion strobe, reset synchronization strobe, and event mode through a control register group. The start event strobe, stop event strobe, count event strobe, and reset event strobe are used to select the corresponding event as input from the total input events. The user can configure the inversion strobe register and the synchronization strobe register to logically invert the event signal and synchronize it to the operating clock of the system event counter device. When the event mode register is 1, the count event is counted in edge trigger count mode; when it is 0, it is counted in level duration mode. After configuring the four events as inputs to the counter device, a trigger signal can be generated when the user-preset conditions are met, which can be used to output counter events, generate interrupts, or provide debugging signals.

[0079] like Figure 5 As shown Figure 4 The diagram shows the interface of the internal counter device of the system event counter. This counter device consists of counter module 1 and counter module 2. The counter device is configured by the user through a register group, which includes a count reference value, global operation enable, free count enable, start / stop count enable, reset event enable, global reset, match value reset enable, and accumulation count enable. In this invention, a register value of 1 defaults to the enabled state. The count reference value in the register group is crucial for matching the count result and generating events; a value of 0 indicates no matching. A global operation enable of 1 controls the entire counter device to operate; a value of 0 indicates the counter is not operating. The free count enable and start / stop count enable control the two counter modules to operate in corresponding modes. In the free count mode, only the count event and associated events are counted. Figure 4 The event mode register configuration shown determines the count value; in start-stop counting mode, the count value of the counting module depends on the start event, stop event, and count event, as well as the attached event. Figure 4The event mode register configuration is shown below. When the reset event enable is 1, the counter device will be reset to its initial state due to the reset event; a value of 0 has no effect. When the global reset is 1, the counter device will be reset to its initial state; a value of 0 has no effect. When the match value reset enable is 1, a reset to the initial state is triggered when the count value of the counting module equals the count reference value; a value of 0 has no effect, and the count value of the counting module continues to accumulate. When the accumulation count enable is 1, a reset to the initial state is triggered if a stop event is triggered at this time; a value of 0 has no effect. The present invention will further explain how to implement multiple counting modes and reset modes through register configuration in Tables 1 and 2 below. Appendix Figure 5 The counting module 1, as described above, connects to counting events, reset events, and the register group to implement the counting function in the free counting enabled mode. The counting module 2 connects to start events, stop events, counting events, reset events, and the register group to implement the counting function in the start-stop counting enabled mode. Only one of the two counting modules is allowed to be in normal working condition at any given time to ensure the uniqueness of the output result and avoid confusion or misjudgment. When the count value of the counting module equals the counting reference value, the counting module can generate a counter event and output an interrupt or debugging signal.

[0080] Appendix Figure 6 and attached Figure 7 This is an appendix to a specific embodiment of the present invention. Figure 5 The state machine diagram required for the counter device. Counter device states: Idle state, Counting wait state, Counting state, Matched state. The counter initially enters the idle state until a waiting event is triggered, after which it enters the counting wait state. In the counting wait state, if a start counting event is triggered, it enters the counting state; if a reset event ① is triggered, it returns to the idle state. In the counting state, the counting module performs counting operations. If a stop counting event is triggered, the counting module stops counting and returns to the counting wait state; if a reset event ② occurs, it returns to the idle state; if a match event is reached, it enters the match state. The match state indicates that the counting result meets the match condition and remains in this state until a reset event ③ causes it to return to the idle state. Counting module 2 has one less path from free counting to the counting state compared to counting module 1; the rest are the same, but the state transition event combinations are different. The event combination logic is detailed below:

[0081] Under counting module 1,

[0082] The logic for the free counting event is as follows: (Global work enable == 1 && Free count enable == 0 && Start / stop count enable == 0).

[0083] The logic consists of waiting count events: (Global work enable == 1 && Free count enable == 1 && Start stop count enable == 0).

[0084] Start counting events to form the logic (counting events == 1).

[0085] The stop event is composed of logic (count event == 0).

[0086] The matching event consists of the following logic: (counting module count value == counting reference value) && (counting reference value ≠ 0).

[0087] The logic for reset event ① is: (Global Reset == 1) || ((Reset Event Enable == 1) && (Reset Event == 1)).

[0088] The logic for reset event ② is: (Global Reset == 1) || ((Reset Event Enable == 1) && (Reset Event == 1)) || (Counter Module Count Value Overflow).

[0089] The logic for reset event ③ is: (Global Reset == 1) || ((Reset Event Enable == 1) && (Reset Event == 1)) || (Matching Value Reset Enable == 1).

[0090] Under counting module 2,

[0091] The logic for waiting for counting events consists of (Global Work Enable == 1 && Free Count Enable == 0 && Start / Stop Count Enable == 1).

[0092] The logic for starting the counting event is: (Start event == 1 && Stop event == 0 && Counting event == 1).

[0093] The logic for the stop counting event is: ((Accumulated count enable == 1 && Stop counting == 1) || Counting event == 0).

[0094] The matching event consists of the following logic: (counting module count value == counting reference value) && (counting reference value ≠ 0).

[0095] The logic for reset event ① is: (Global Reset == 1) || ((Reset Event Enable == 1) && (Reset Event == 1)).

[0096] The logic for reset event ② is as follows: (Global Reset == 1) || ((Reset Event Enable == 1) && (Reset Event == 1)) || (Counter Module Count Value Overflow) || (Accumulated Count Enable == 0 && Stop Counting == 1).

[0097] The logic for reset event ③ is: (Global Reset == 1) || ((Reset Event Enable == 1) && (Reset Event == 1)) || (Matching Value Reset Enable == 1).

[0098] Table 1 below shows the counting modes of the system event counter device under different configurations of the control register in specific embodiments of the present invention:

[0099] Table 1. System event counter device counting modes under different control register configurations.

[0100] System event counter device counting mode Global Work Enable Free Count Enable Start / Stop Counting Enable Event Pattern In this mode, the counter counts freely and acts as a timer to record clock cycles. √ In this mode, the counting module's count value depends on the condition that (counting event == 1), and records the duration of the event level. √ √ In this mode, the counting module's count value depends on the condition that (count event == 1), recording the number of times the event is triggered. √ √ √ In this mode, the counting module's count value depends on the situation between start and stop events (count event == 1), recording the duration period of the event level. √ √ In this mode, the counting module's count value depends on the situation between start and stop events (count event == 1), recording the number of event triggers. √ √ √

[0101] When (Global Working Enable == 1 && Free Count Enable == 0 && Start / Stop Count Enable == 0), in this mode, the counter counts freely and is used as a timer to record clock cycles.

[0102] When (Global Working Enable == 1 && Free Count Enable == 1), in this mode, the count value of the counting module depends on the condition of (Count Event == 1), and records the duration period of the event level;

[0103] When (Global Work Enable == 1 && Free Count Enable == 1 && Event Mode == 1), in this mode, the count value of the counting module depends on the condition (Count Event == 1), and records the number of times the event is triggered;

[0104] When (Global Working Enable == 1 && Start Stop Count Enable == 1), in this mode, the count value of the counting module depends on the situation between the start and stop events (count event == 1), and records the duration period of the event level;

[0105] When (Global Work Enable == 1 && Start Stop Count Enable == 1 && Event Mode == 1), in this mode, the count value of the counting module depends on the situation between the start and stop events (count events == 1), recording the number of times the event is triggered.

[0106] Table 2 below shows the reset modes of the system event counter device under different configurations of the control register in specific embodiments of the present invention:

[0107] Table 2. System event counter device reset modes under different control register configurations.

[0108] System event counter device reset mode Global Reset Reset event enable Match value reset enable Accumulation count enable This reset is a global reset, returning the counting module to the idle state; √ When this register is enabled, if (reset event == 1), a reset is triggered, returning the counting module to the idle state. √ When this register is enabled, if (counting module value == counting reference value), a reset is triggered, returning the counting module to the idle state. √ When this register is enabled, it only applies in start-stop mode. If (stop event == 1), a reset is triggered, returning the counting module to the idle state. √

[0109] When (Global Reset == 1), the reset is a global reset, which returns the counting module to the idle state;

[0110] When (Reset Event Enable == 1), if (Reset Event == 1), a reset is triggered, causing the counting module to return to the idle state;

[0111] When (Matching value reset enable == 1), if (Counting module value == Counting reference value), a reset is triggered, causing the counting module to return to the idle state;

[0112] When (Accumulation Count Enable == 1), it only applies when (Global Working Enable == 1 && Start / Stop Count Enable == 1). If (Stop Event == 1), a reset is triggered, causing the counting module to return to the idle state.

[0113] The implementation steps of the embedded SoC-level real-time monitoring and analysis device given above in this invention are as follows:

[0114] Step 1: The bus comparator collects the access signals of the on-chip bus and compares them according to the preset matching conditions.

[0115] Step 2: When the matching condition is met, the bus comparator generates a trigger signal. The trigger signal is used to drive the event status register to record, output an interrupt signal or a debug signal, or serve as an input event for the system event counter.

[0116] Step 3: The system event counter performs cumulative counting, time window counting, or threshold detection according to the set counting mode.

[0117] Step 4: When the monitoring result is equal to the preset reference value, the system event counter generates a trigger signal to drive the event status register to record, output interrupt or debugging signals, and can be used as an input event again to realize event chain statistics.

[0118] Step 5: The user reads the matching status, event count results and related monitoring information through the on-chip bus interface in order to perform subsequent performance analysis and system optimization.

[0119] It should be noted that the above description is not intended to limit the present invention, and the present invention is not limited to the examples given above. Any changes, modifications, additions or substitutions made by those skilled in the art within the scope of the present invention should also fall within the protection scope of the present invention.

Claims

1. An in-line SoC level real-time monitoring and analysis apparatus, characterized by, The system event counter is used for monitoring various events generated in the running process of the SoC, and the trigger signal is generated when the monitoring result is equal to the preset reference value. The system event counter supports cumulative counting, time window counting and conditional trigger counting, and counts the occurrence frequency, duration and interval time of the events. The control register group is used for configuring the matching condition of the bus comparator, setting the counting mode of the system event counter, and reading the comparison state, event counting result and related monitoring information through the bus interface. The system event counter corresponds to a start event, a stop event, a counting event and a reset event, and the events are gated through an event gating unit, and an inversion gating unit is set for each event. The start event, the stop event, the counting event and the reset event are configured as inputs of the counter device, and the trigger signal is generated when the preset condition is met, which is used for outputting the counter event, generating an interrupt or providing a debug signal. The start event gating, the start inversion gating, the start synchronous gating, the stop event gating, the stop inversion gating, the stop synchronous gating, the counting event gating, the counting inversion gating, the counting synchronous gating, the reset event gating, the reset inversion gating, the reset synchronous gating and the event mode are configured through the control register group. The event signal is logically inverted and synchronized to the working clock of the system event counter through the inversion gating register and the synchronous gating register. For the counting event, the event mode register is configured as 1, and the counting is performed in the edge trigger frequency mode; the event mode register is configured as 0, and the counting is performed in the level duration mode. The counter device is composed of a counting module 1 and a counting module 2, and is configured through a register group. The counting module 1 is connected with the counting event, the reset event and the register group, and is used for realizing the counting function in the free counting enable mode. The counting module 2 is connected with the start event, the stop event, the counting event, the reset event and the register group, and is used for realizing the counting function in the start-stop counting enable mode. The counting module can generate the counter event, output the interrupt or the debug signal when the counting value of the counting module is equal to the counting reference value. The counting mode of the system event counter device under different configurations of the control register includes: When (global work enable == 1 && free count enable == 0 && start stop count enable == 0), the counter counts freely, and the clock cycle is recorded as a timer; When (global work enable == 1 && free count enable == 1), the count value of the count module depends on the case (count event == 1), and the event level duration cycle is recorded; When (global work enable == 1 && free count enable == 1 && event mode == 1), the count value of the count module depends on the case (count event == 1), and the event trigger times are recorded; When (global work enable == 1 && start stop count enable == 1), the count value of the count module depends on the case (count event == 1) between start stop events, and the event level duration cycle is recorded; When (global work enable == 1 && start stop count enable == 1 && event mode == 1), the count value of the count module depends on the case (count event == 1) between start stop events, and the event trigger times are recorded.

2. The in-line SoC level real-time monitoring and analysis apparatus of claim 1, wherein, The device is composed of N bus comparators of the same structure, M system event counters of the same structure, and a control register group; N parallel comparison events are directly input as input events of M system event counters, or are respectively input to P logic or gates or Q logic and gates, and input combinations are configured through the control register group, so as to generate P or gate events or Q and gate events.

3. The in-line SoC level real-time monitoring and analysis apparatus according to claim 1 or 2, characterized in that, The bus comparator connects the bus to be captured and the comparison mode to the comparison module through a multiplexer, and bus selection and comparison mode selection are configured by the control register group. In the comparison module, five comparison modes are realized according to user-defined reference values and masks: (bus | mask) == (reference value | mask), (bus | mask) > (reference value | mask), (bus | mask) < (reference value | mask), (bus | mask) >= (reference value | mask), and (bus | mask) <= (reference value | mask); after successful comparison, comparison events, output interrupts, or debugging signals are generated through range matching and mask matching of the comparison module.

4. The in-line SoC level real-time monitoring and analysis apparatus of claim 1, wherein, The register value is 1 by default to enable the start state; the value of the count reference value is 0 to not participate in matching; the free count enable and the start-stop count enable control two count modules to work in corresponding modes, wherein in the free count mode, only the count event and the event mode register configuration determine; in the start-stop count mode, the count module count value depends on the start event, the stop event, the count event and the event mode register configuration; the reset event enable is 1, the counter device is reset to the initial state under the influence of the reset event, and the value is 0 to have no effect; the global reset is 1, the counter device is reset to the initial state, and the value is 0 to have no effect; the matching value reset enable is 1, when the count module count value is equal to the count reference value, the reset to the initial state is triggered, the value is 0 to have no effect, and the count module count value continues to accumulate; the accumulated count enable is 1, if the stop event is triggered at this time, the reset to the initial state is triggered, the value is 0 to have no effect.

5. The in-line SoC level real-time monitoring and analysis apparatus of claim 1, wherein, The counter device state includes: idle state, count waiting state, count state and matching state; the state machine includes: The counter is initially in the idle state, until the waiting event is triggered, and after the trigger, the count waiting state is entered; in the count waiting state, if the start count event is triggered, the count state is entered, and if the reset event 1 is triggered, the idle state is returned; in the count state, the count module performs the count operation, if the stop count event is triggered, the count module stops the count operation, and the count waiting state is returned, if the reset event 2 occurs, the idle state is returned, and if the matching event occurs, the matching state is entered; in the matching state, the count result meets the matching condition, and in this state, the idle state is returned until the reset event 3.

6. The in-line SoC level real-time monitoring and analysis apparatus of claim 5, wherein, The state transition event combination of the count module 1 and the count module 2 respectively includes: In the count module 1, The free count event composition logic is: (global work enable == 1 && free count enable == 0 && start-stop count enable == 0); The waiting count event composition logic is: (global work enable == 1 && free count enable == 1 && start-stop count enable == 0); The start count event composition logic is: (count event == 1); The stop event composition logic is: (count event == 0); The matching event composition logic is: (count module count value == count reference value) && (count reference value!= 0); The reset event 1 composition logic is: (global reset == 1) || ((reset event enable == 1) && (reset event == 1)); (global reset == 1) || (reset event enable == 1 && reset event == 1); The reset event 2 composition logic is: (global reset == 1) || (reset event enable == 1 && reset event == 1) || (count module count value overflow); The reset event 3 composition logic is: (global reset == 1) || (reset event enable == 1 && reset event == 1) || (matching value reset enable == 1); In the count module 2, Wait count event composition logic: (global work enable == 1 && free count enable == 0 && start stop count enable == 1); Start count event composition logic: (start event == 1 && stop event == 0 && count event == 1); Stop count event composition logic: (accumulation count enable == 1 && stop count == 1) || (count event == 0); Match event composition logic: (count module count value == count reference value) && (count reference value!= 0); Reset event 1 composition logic: (global reset == 1) || (reset event enable == 1 && reset event == 1); Reset event 2 composition logic: (global reset == 1) || (reset event enable == 1 && reset event == 1) || (count module count value overflow) || (accumulation count enable == 0 && stop count == 1); Reset event 3 composition logic: (global reset == 1) || (reset event enable == 1 && reset event == 1) || (match value reset enable == 1).

7. The in-line SoC level real-time monitoring and analysis apparatus of claim 1, wherein, The reset mode of the system event counter device under different configurations of the control register comprises: When (global reset == 1), the reset is a global reset, and the count module returns to an idle state; When (reset event enable == 1), if (reset event == 1), a reset is triggered, and the count module returns to the idle state; When (match value reset enable == 1), if (count module count value == count reference value), a reset is triggered, and the count module returns to the idle state; When (accumulation count enable == 1), only under (global work enable == 1 && start stop count enable == 1), if (stop event == 1), a reset is triggered, and the count module returns to the idle state.

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