Access request processing method, device, system and chip

Abstract

The invention relates to an access request processing method, device and system and a chip. Comprising the following steps: receiving a data access request, and analyzing the data access request to obtain a target address requested to be accessed; determining an address field segment needing to be interleaved in the target address according to a preset interleaving granularity, the number of memories and the capacity of a single memory; interleaving the address field segment needing to be interleaved to obtain an interleaved address; sending the interleaved address to a bus routing module; and sending the interleaved address to the bus routing module to indicate the bus routing module to access the corresponding memory according to the interleaved address.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, in particular to a processing method, device and system of access request and chip. BACKGROUND

[0002] In chip design, static random-access memory (SRAM) is often used as an information storage body. When multiple service streams or processing units (such as multiple CPU threads, DMA engines, accelerator modules, etc.) as different masters simultaneously attempt to access the same SRAM, due to the limited number of access ports of the SRAM (such as single-port or dual-port SRAM), access conflicts will occur between these access requests, which must be queued for processing by an arbitration mechanism, resulting in some access requests being delayed or even discarded.

[0003] Suppose there is an SRAM in the system for caching task descriptors, multiple CPU threads will concurrently initiate read and write requests to this SRAM. If the SRAM only supports single-port access, only one thread can successfully access the SRAM at any time, and the remaining threads must wait. Even if the system has high theoretical concurrency capability, the actual throughput will be limited by the maximum access bandwidth of this SRAM, and ultimately can only reach the maximum performance limit supported by a single SRAM. This bottleneck not only limits the scalability of the system, but also puts higher requirements on software scheduling. In order to alleviate this problem, software needs to artificially disperse access tasks of different masters to different SRAMs when performing service layout, in order to minimize the simultaneous access of multiple access sources to the same SRAM. However, this approach often requires a deep understanding of the business logic, and in actual applications, due to the limitation of the number of SRAMs, address mapping methods, and the uncertainty of service streams, it is difficult to completely avoid access conflicts, resulting in the system performance cannot be fully utilized, and even unpredictable bandwidth bottlenecks occur. SUMMARY

[0004] Therefore, it is necessary to provide a processing method, device, system and chip of access request capable of improving system performance in view of the above technical problems.

[0005] In a first aspect, the present application provides a processing method of access request, comprising:

[0006] receiving an access request, parsing the access request to obtain a target address requested to be accessed;

[0007] determining an address domain segment in the target address that needs to be interleaved according to a pre-set interleaving granularity, the number of memories and the capacity of a single memory;

[0008] The address segments that need to be interleaved are interleaved to obtain the interleaved addresses;

[0009] The interleaved address is sent to the bus routing module to instruct the bus routing module to access the corresponding memory according to the interleaved address.

[0010] In some embodiments, determining the address segments to be interleaved in the target address based on a preset interleaving granularity, the number of memories, and the capacity of a single memory includes:

[0011] The address of the first address segment that needs to be interleaved is determined to be: addr1[n+a-1:n];

[0012] The address of the second address segment that needs to be interleaved is determined to be: addr2[b+a-1:b];

[0013] in , , Where m is the interleaving granularity, X is the number of memories, and Z is the capacity of each memory.

[0014] In some embodiments, the process of interleaving the address segments to be interleaved to obtain the interleaved address specifically includes:

[0015] The address from the nth to the (n+a-1)th address in the target address is replaced with the second address field addr2, and the address from the bth to the (b+a-1)th address in the target address is replaced with the first address field addr1. The other address fields of the target address remain unchanged, thereby obtaining the interleaved address.

[0016] Secondly, this application also provides an access request processing apparatus, comprising:

[0017] The receiving module is used to receive access requests, parse the access requests, and obtain the target address to be accessed.

[0018] The determination module is used to determine the address domain segments that need to be interleaved in the target address based on the pre-set interleaving granularity, the number of memories, and the capacity of a single memory.

[0019] The interleaving module is used to interleave the address segments that need to be interleaved to obtain the interleaved address;

[0020] The sending module is used to send the interleaved address to the bus routing module to instruct the bus routing module to access the corresponding memory according to the interleaved address.

[0021] Thirdly, this application also provides an access request processing system, including: an access request output device, a bus routing module, a set number of memories, and the access request processing device as described above.

[0022] The access request output device is used to output access requests;

[0023] The bus routing module is used to access the corresponding memory according to the interleaved address, obtain the target data of the access request, and return the target data to the access request output device through the access request processing device.

[0024] The memory is used to store the target data.

[0025] Fourthly, this application provides a chip including the access request processing apparatus as described above.

[0026] Fifthly, this application also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the aforementioned method for processing access requests.

[0027] Sixthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the aforementioned method for processing access requests.

[0028] The aforementioned access request processing method, apparatus, system, and chip receive a data access request, parse the data access request to obtain the target address to be accessed; determine the address domain segments in the target address that need to be interleaved according to a preset interleaving granularity, the number of memories, and the capacity of a single memory; interleave the address domain segments that need to be interleaved to obtain an interleaved address; and send the interleaved address to a bus routing module to instruct the bus routing module to access the corresponding memory according to the interleaved address. In this way, a large number of data access requests are evenly distributed to various memories through address interleaving, reducing the performance bottleneck that may be caused by multiple data access requests accessing the same memory, and effectively improving access bandwidth. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 A chip frame in one embodiment Figure 1 ;

[0031] Figure 2 A chip frame in one embodiment Figure 2 ;

[0032] Figure 3 Here is a flowchart of a data access method in one embodiment;

[0033] Figure 4 This is a schematic diagram of the interleaving principle in one embodiment;

[0034] Figure 5 This is a schematic diagram of the address distribution before interleaving in one embodiment. Figure 1 ;

[0035] Figure 6 This is a schematic diagram of the address distribution before interleaving in one embodiment. Figure 2 ;

[0036] Figure 7 This is a schematic diagram of the address distribution before interleaving in one embodiment. Figure 3 ;

[0037] Figure 8 This is a schematic diagram of the address distribution before interleaving in one embodiment. Figure 4 ;

[0038] Figure 9 This is a schematic diagram of the address distribution after interleaving in one embodiment. Figure 1 ;

[0039] Figure 10 This is a schematic diagram of the address distribution after interleaving in one embodiment. Figure 2 ;

[0040] Figure 11 This is a schematic diagram of the address distribution after interleaving in one embodiment. Figure 3 ;

[0041] Figure 12 This is a schematic diagram of the address distribution after interleaving in one embodiment. Figure 4 . Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0043] In some embodiments, see Figure 1As shown, an access request processing system is provided. This system includes multiple access request output devices, a bus routing module, and multiple memories connected to the bus routing module. Connecting multiple memories can significantly improve bandwidth performance; however, it's necessary to consider that when different access request output devices simultaneously access the same memory, collisions can occur, introducing new performance bottlenecks. In this case, only the maximum performance supported by a single memory can be achieved. Therefore, when laying out services, this situation needs to be considered, and different access sources should be prevented from accessing the same memory simultaneously as much as possible. This can create difficulties in software layout and often cannot effectively avoid bandwidth performance bottlenecks caused by access collisions.

[0044] Therefore, this application provides an access request processing system that adds an access request processing device before the bus routing module. Specifically, see [link to relevant documentation]. Figure 2 As shown, the chip includes multiple access request output devices, access request processing devices, a bus routing module, and multiple memories connected to the bus routing module. The access request processing device remaps addresses, and at a certain granularity, before the bus routing module, it evenly changes the destination address of accesses to the same memory and directs them to different memories. This eliminates the need to consider how to evenly distribute services across memory locations, effectively distributing collision traffic evenly across all memories. This disperses collision traffic, effectively improves access bandwidth, and solves the performance bottleneck problem of multiple sources accessing the same memory.

[0045] In one exemplary embodiment, such as Figure 3 As shown, a data access method is provided, which can be applied to Figure 2 A means for processing access requests in a system, the method comprising:

[0046] Step 102: Receive a data access request, parse the data access request, and obtain the target address to be accessed.

[0047] in, Figure 2 Multiple access request output devices serve as access sources for the bus routing module. These access request output devices can be processor cores or accelerator components.

[0048] Each access request output device corresponds to an access request processing device, which is connected between the corresponding access request output device and the bus routing module. Multiple memories are connected to the bus routing module.

[0049] Optionally, the memory can be static random-access memory (SRAM).

[0050] The access request output device sends the data access request to the corresponding access request processing device. The data access request may be a data read request or a data write request, and this embodiment does not limit the type of request.

[0051] The data access request carries the target address to be accessed. After receiving the data access request, the access request processing device parses the data access request to obtain the target address to be accessed.

[0052] Step 104: Determine the address domain segments that need to be interleaved in the target address based on the preset interleaving granularity, the number of memories, and the capacity of a single memory.

[0053] Optionally, the interleaving granularity can be flexibly set according to the actual situation. For example, the interleaving granularity can be 4KB.

[0054] The number of memory units is Figure 2 The number of memory modules connected to the bus routing module. All memory modules have the same capacity; for example, all memory modules have a capacity of 1Mb.

[0055] Optionally, the access request processing device can determine the address domain segments in the target address that need to be interleaved, i.e. the address domain segments that need to be swapped, based on the pre-set interleaving granularity, the number of memories, and the capacity of a single memory.

[0056] Step 106: Interleave the address segments that need to be interleaved to obtain the interleaved addresses.

[0057] In this process, after determining the address segments that need to be interleaved in the target address, the access request processing device interleaves the address segments that need to be interleaved. For example, if the address segments that need to be interleaved are segment 1 and segment 2, then the address of segment 1 and the address of segment 2 in the target address are swapped to obtain the interleaved address.

[0058] It should be noted that each access request output device corresponds to an access request processing device, and the interleaving principle of each access request processing device is the same. That is, for any access request processing device, after receiving the data access request sent by the corresponding access request output device, it can complete the interleaving through the steps provided above.

[0059] Step 108: Send the interleaved address to the bus routing module to instruct the bus routing module to access the corresponding memory according to the interleaved address.

[0060] The access request processing device sends the interleaved address to the bus routing module. The bus routing module accesses the corresponding memory according to the interleaved address. Specifically, when the data access request is a data read request, the bus routing module reads the data according to the interleaved address; when the data access request is a data write request, the bus routing module writes the data according to the interleaved address.

[0061] Optionally, the bus routing module can be an Advanced Extensible Interface (AXI) interconnect module, and the data access request can be an AXI access request. The AXI interconnect module can route the AXI access request to the corresponding memory according to the interleaved address.

[0062] Optionally, the memory is SRAM, which supports conversion of the AXI interface to a regular SRAM read / write interface.

[0063] For example, access request output device 0 sends a Read Address (AR) instruction request 0 using the Advanced Extensible Interface (AXI) protocol to the corresponding access request processing device 0, and access request output device 1 also sends an AXI AR instruction request 1 to the corresponding access request processing device 1. Both AXI AR instruction requests access memory 0. The access request processing device 0, through the interleaving method provided in this embodiment, uses a bus routing module to evenly distribute the AXI AR instruction request 0 to memory 0-3; similarly, the access request processing device 1, through the interleaving method provided in this embodiment, uses a bus routing module to evenly distribute the AXI AR instruction request 1 to memory 0-3, thus achieving traffic distribution in memory 0.

[0064] In the above embodiments, the access request processing device receives a data access request, parses the data access request to obtain the target address to be accessed; determines the address field segments in the target address that need to be interleaved according to a preset interleaving granularity, the number of memories, and the capacity of a single memory; interleaves the address field segments that need to be interleaved to obtain an interleaved address; and sends the interleaved address to the bus routing module to instruct the bus routing module to access the corresponding memory according to the interleaved address. In this way, a large number of data access requests are evenly distributed to various memories through address interleaving, reducing the performance bottleneck that may be caused by multiple data access requests accessing the same memory, and effectively improving access bandwidth.

[0065] In some embodiments, the process of determining the address segments to be interleaved in the target address based on a preset interleaving granularity, the number of memories, and the capacity of each memory specifically includes the following steps: determining the address of the first address segment to be interleaved as addr1[n+a-1:n]; determining the address of the second address segment to be interleaved as addr2[b+a-1:b]; wherein , , Where m is the interleaving granularity, X is the number of memories, and Z is the capacity of each memory.

[0066] In this embodiment, after parsing the target address, the access request processing device determines that addr1[n+a-1:n] and addr2[b+a-1:b] need to be interleaved. For ease of explanation, in this embodiment, addr1[n+a-1:n] is referred to as the address of the first address segment, and addr2[b+a-1:b] is referred to as the address of the second address segment. , , Where m is the interleaving granularity, X is the number of memories, and Z is the capacity of each memory.

[0067] For example, the interleaving granularity m=4KB, the number of memories X=4, and the capacity of each memory Z=1Mb. We can calculate n=12, a=2, b=20. The target address is represented by addr_in. Following the above principle, the address of the first address segment to be interleaved is: addr_in[13:12]; the address of the second address segment to be interleaved is: addr_in[21:20].

[0068] The above embodiments provide a method for determining the address domain segments that need to be interleaved. Subsequently, interleaving processing can be performed based on these address domain segments. The addition of this interleaving processing can reduce the performance bottleneck that may be caused by multiple data access requests accessing the same memory, and effectively improve the access bandwidth.

[0069] In some embodiments, interleaving the address segments that need to be interleaved to obtain the interleaved address specifically includes: replacing the address of the nth to n+a-1th bits in the target address with the second address segment addr2, replacing the address of the bth to b+a-1th bits in the target address with the first address segment addr1, and keeping the other address segments of the target address unchanged, thereby obtaining the interleaved address.

[0070] Based on the implementation method provided above, the access request processing device can determine that the address of the first address field segment to be interleaved is addr1[n+a-1:n]; and the address of the second address field segment to be interleaved is addr2[b+a-1:b]. Further, the access request processing device can perform interleaving processing according to these two addresses. Specifically, the address of the nth to n+a-1th bits in the target address is replaced with the second address field segment addr2, and the address of the bth to b+a-1th bits in the target address is replaced with the first address field segment addr1. The other address field segments of the target address remain unchanged, thereby obtaining the interleaved address.

[0071] For example, see Figure 4 As shown, the target address is represented by addr_in. The address of the first address field segment that needs to be interleaved, determined by the access request processing device, is addr_in[13:12]; the address of the second address field segment that needs to be interleaved is addr_in[21:20]. Therefore, the access request processing device can replace bits 12 and 13 of the target address addr_in with addr_in[21:20], and bits 20 and 21 of the target address addr_in with addr_in[13:12], while keeping other addresses unchanged, thus obtaining the interleaved address addr_out.

[0072] The above embodiments provide a specific method for performing interleaving processing. This interleaving processing can reduce the performance bottleneck that may be caused by multiple data access requests accessing the same memory, and effectively improve access bandwidth.

[0073] In some embodiments, the number of memories X=4, namely SRAM0, SRAM1, SRAM2, and SRAM3, with a memory capacity of 1MB and an interleaving granularity of 4KB. Without interleaving, the address distribution of each memory (SRAM) is as follows: Figures 5-8 As shown. After adding the interleaving process provided in this application, the address distribution of each memory becomes as follows. Figures 9-12As shown, the addresses on the original SRAM0 are interleaved and distributed across SRAM1, SRAM2, and SRAM3. Similarly, the addresses on SRAM1, SRAM2, and SRAM3 are also interleaved and distributed across other SRAMs, reducing performance bottlenecks that may result from multiple data access requests accessing the same memory and effectively improving access bandwidth. With the increasing demand for high-performance computing such as artificial intelligence, SRAM needs to support faster data access speeds and lower latency. The interleaving technology provided in this application can effectively reduce these latency issues and improve computational efficiency and performance by distributing read and write operations. Furthermore, the interleaving technology provided in this application allows software engineers to avoid meticulously planning business scenarios across different SRAMs, simplifying in-memory business deployment.

[0074] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0075] Based on the same inventive concept, this application also provides a data access device for implementing the data access method described above. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more data access device embodiments provided below can be found in the limitations of the data access method described above, and will not be repeated here.

[0076] In one exemplary embodiment, an access request processing apparatus is provided, comprising:

[0077] The receiving module is used to receive data access requests, parse the data access requests, and obtain the target address to be accessed.

[0078] The determination module is used to determine the address domain segments that need to be interleaved in the target address based on the pre-set interleaving granularity, the number of memories, and the capacity of a single memory.

[0079] The interleaving module is used to interleave the address segments that need to be interleaved to obtain the interleaved address;

[0080] The sending module is used to send the interleaved address to the bus routing module to instruct the bus routing module to access the corresponding memory according to the interleaved address.

[0081] In some embodiments, the determining module is specifically used to determine the address of the first address segment to be interleaved as addr1[n+a-1:n]; and to determine the address of the second address segment to be interleaved as addr2[b+a-1:b]; wherein , , Where m is the interleaving granularity, X is the number of memories, and Z is the capacity of each memory.

[0082] In some embodiments, the interleaving module is specifically used to replace the address of the nth to n+a-1th bits in the target address with the second address field addr2, and to replace the address of the bth to b+a-1th bits in the target address with the first address field addr1, while the other address fields of the target address remain unchanged, thereby obtaining the interleaved address.

[0083] Each module in the aforementioned data access device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can invoke and execute the operations corresponding to each module.

[0084] In one embodiment, an access request processing system is provided, comprising: an access request output device, a bus routing module, a set number of memories, and the aforementioned access request processing device. The access request output device is used to output a data access request; the bus routing module is used to access the corresponding memory according to the interleaved address, obtain the target data of the access request, and return the target data to the access request output device through the access request processing device; the memories are used to store the target data.

[0085] The number of memory units can be flexibly set according to actual needs. The number of access request output devices can be the same as or different from the number of access request processing devices, depending on the actual situation.

[0086] The access request output device is used to output a data access request to the access request processing device. The bus routing module is used to access the corresponding memory according to the interleaved address, obtain the target data of the access request, and return the target data to the processing device that issued the interleaved address. The processing device further returns the target data to the access request output device that issued the data access request.

[0087] In some embodiments, the access request processing device is configured to receive a data access request, parse the data access request to obtain the target address to be accessed; determine the address field segments in the target address that need to be interleaved according to a preset interleaving granularity, the number of memories and the capacity of a single memory; interleave the address field segments that need to be interleaved to obtain an interleaved address; and send the interleaved address to the bus routing module.

[0088] In some embodiments, the access request processing apparatus is specifically used for:

[0089] The address of the first address segment that needs to be interleaved is determined to be: addr1[n+a-1:n];

[0090] The address of the second address segment that needs to be interleaved is determined to be: addr2[b+a-1:b];

[0091] in , , Where m is the interleaving granularity, X is the number of memories, and Z is the capacity of each memory.

[0092] In some embodiments, the access request processing apparatus is specifically used for:

[0093] The address from the nth to the (n+a-1)th address in the target address is replaced with the second address field addr2, and the address from the bth to the (b+a-1)th address in the target address is replaced with the first address field addr1. The other address fields of the target address remain unchanged, thereby obtaining the interleaved address.

[0094] In one embodiment, a chip is provided, including the access request processing apparatus provided in the foregoing embodiments.

[0095] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0096] Receive a data access request, parse the data access request, and obtain the target address to be accessed;

[0097] The address domain segments that need to be interleaved in the target address are determined based on the pre-set interleaving granularity, the number of memories, and the capacity of a single memory.

[0098] The address segments that need to be interleaved are interleaved to obtain the interleaved addresses;

[0099] The interleaved address is sent to the bus routing module to instruct the bus routing module to access the corresponding memory according to the interleaved address.

[0100] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0101] The address of the first address segment that needs to be interleaved is determined to be: addr1[n+a-1:n];

[0102] The address of the second address segment that needs to be interleaved is determined to be: addr2[b+a-1:b];

[0103] in , , Where m is the interleaving granularity, X is the number of memories, and Z is the capacity of each memory.

[0104] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0105] The address from the nth to the (n+a-1)th address in the target address is replaced with the second address field addr2, and the address from the bth to the (b+a-1)th address in the target address is replaced with the first address field addr1. The other address fields of the target address remain unchanged, thereby obtaining the interleaved address.

[0106] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, performs the following steps:

[0107] Receive a data access request, parse the data access request, and obtain the target address to be accessed;

[0108] The address domain segments that need to be interleaved in the target address are determined based on the pre-set interleaving granularity, the number of memories, and the capacity of a single memory.

[0109] The address segments that need to be interleaved are interleaved to obtain the interleaved addresses;

[0110] The interleaved address is sent to the bus routing module to instruct the bus routing module to access the corresponding memory according to the interleaved address.

[0111] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0112] The address of the first address segment that needs to be interleaved is determined to be: addr1[n+a-1:n];

[0113] The address of the second address segment that needs to be interleaved is determined to be: addr2[b+a-1:b];

[0114] in , , Where m is the interleaving granularity, X is the number of memories, and Z is the capacity of each memory.

[0115] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0116] The address from the nth to the (n+a-1)th address in the target address is replaced with the second address field addr2, and the address from the bth to the (b+a-1)th address in the target address is replaced with the first address field addr1. The other address fields of the target address remain unchanged, thereby obtaining the interleaved address.

[0117] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0118] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0119] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for processing access requests, characterized in that, include: Receive a data access request, parse the data access request, and obtain the target address to be accessed; The address domain segments that need to be interleaved in the target address are determined based on the pre-set interleaving granularity, the number of memories, and the capacity of a single memory. The address segments that need to be interleaved are interleaved to obtain the interleaved addresses; The interleaved address is sent to the bus routing module to instruct the bus routing module to access the corresponding memory based on the interleaved address.

2. The method according to claim 1, characterized in that, The step of determining the address segments to be interleaved in the target address based on the pre-set interleaving granularity, the number of memories, and the capacity of a single memory includes: The address of the first address segment that needs to be interleaved is determined to be: addr1[n+a-1:n]; The address of the second address segment that needs to be interleaved is determined to be: addr2[b+a-1:b]; in , , Where m is the interleaving granularity, X is the number of memories, and Z is the capacity of each memory.

3. The method according to claim 2, characterized in that, The process of interleaving the address segments that need to be interleaved to obtain the interleaved address specifically includes: The address from the nth to the (n+a-1)th address in the target address is replaced with the second address field addr2, and the address from the bth to the (b+a-1)th address in the target address is replaced with the first address field addr1. The other address fields of the target address remain unchanged, thereby obtaining the interleaved address.

4. An access request processing apparatus, characterized in that, The device includes: The receiving module is used to receive data access requests, parse the data access requests, and obtain the target address to be accessed. The determination module is used to determine the address domain segments that need to be interleaved in the target address based on the pre-set interleaving granularity, the number of memories, and the capacity of a single memory. The interleaving module is used to interleave the address segments that need to be interleaved to obtain the interleaved address; The sending module is used to send the interleaved address to the bus routing module to instruct the bus routing module to access the corresponding memory according to the interleaved address.

5. The apparatus according to claim 4, characterized in that, The determining module is specifically used to determine the address of the first address segment that needs to be interleaved as addr1[n+a-1:n]; and to determine the address of the second address segment that needs to be interleaved as addr2[b+a-1:b]. in , , Where m is the interleaving granularity, X is the number of memories, and Z is the capacity of each memory.

6. The apparatus according to claim 5, characterized in that, The interleaving module is specifically used to replace the address from the nth to the (n+a-1)th bit of the target address with the second address field addr2, and to replace the address from the bth to the (b+a-1)th bit of the target address with the first address field addr1, while the other address fields of the target address remain unchanged, thereby obtaining the interleaved address.

7. A system for processing access requests, characterized in that, include: The access request output device, the bus routing module, the set number of memories, and the access request processing device as described in any one of claims 4-6 The access request output device is used to output a data access request; The bus routing module is used to access the corresponding memory according to the interleaved address, obtain the target data of the access request, and return the target data to the access request output device through the access request processing device. The memory is used to store the target data.

8. A chip, characterized in that, Includes the access request processing apparatus as described in any one of claims 4-6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 3.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 3.

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