Reading circuit and reading chip of detector

Abstract

The invention relates to a readout circuit and a readout chip of a detector. The readout circuit comprises at least one readout channel, and the readout channel comprises a charge sensitive pre-amplification circuit which is connected with a detector and is used for amplifying a charge signal output by the detector and outputting an initial voltage signal; the active shaping filter circuit is connected with the charge sensitive pre-amplification circuit and is used for receiving a control signal, carrying out filtering shaping processing on an initial voltage signal under the action of the control signal and outputting a shaping signal; the time constant of the active shaping filter circuit is regulated and controlled by the control signal; and the screening circuit is connected with the active shaping filter circuit and is used for receiving a preset voltage signal, comparing the shaping signal with the preset voltage signal and outputting a digital level signal according to a comparison result. The reading circuit has the advantage of being high in reading precision.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of detectors, in particular to a readout circuit and a readout chip of a detector. BACKGROUND

[0002] Micro-structured gas detector (MPGD) has the advantages of small volume, high count rate, high precision and low cost, and is widely used in high energy physics, nuclear physics and other fields. Micro-structured gas detector usually needs to be provided with a readout circuit to capture the detection signal.

[0003] The existing readout circuit generally adopts discrete device design. The discrete device needs to be placed on a PCB board and interconnected through metal welding on the PCB board. The parasitic interference is large, resulting in low readout precision. SUMMARY

[0004] Therefore, it is necessary to provide a readout circuit and a readout chip of a detector with high readout precision.

[0005] In a first aspect, the present application provides a readout circuit of a detector, comprising at least one readout channel, the readout channel comprising:

[0006] a charge-sensitive preamplifier connected with the detector, configured to amplify and process a charge signal output by the detector and output an initial voltage signal;

[0007] an active shaping filter circuit connected with the charge-sensitive preamplifier, configured to receive a control signal, filter and shape the initial voltage signal under the action of the control signal, and output a shaped signal; the time constant of the active shaping filter circuit is controlled by the control signal;

[0008] a discrimination circuit connected with the active shaping filter circuit, configured to receive a preset voltage signal, compare the shaped signal with the preset voltage signal, and output a digital level signal according to the comparison result.

[0009] In one of the embodiments, the control signal comprises an integral control signal and a differential control signal, and the active shaping filter circuit comprises:

[0010] an active high-pass differential module connected with the charge-sensitive preamplifier, configured to receive the differential control signal, and configured to perform high-pass differential processing on the charge signal to suppress the long tail part of the initial voltage signal and output an initial shaped signal;

[0011] an active low-pass integral module connected with the active high-pass differential module, configured to receive the integral control signal, and configured to perform filter processing on the initial shaped signal to form the shaped signal.

[0012] In one embodiment, the active high-pass differential module includes a first operational amplifier unit, a first capacitive unit, a second capacitive unit, and a first resistor. The first terminal of the first capacitive unit is connected to the charge-sensitive preamplifier circuit. The second terminal of the first capacitive unit is connected to the first terminal of the second capacitive unit, the first terminal of the first resistor, and the inverting input terminal of the first operational amplifier unit. The output terminal of the first operational amplifier unit is connected to the second terminal of the second capacitive unit, the second terminal of the first resistor, and the active low-pass integral module. The non-inverting input terminal of the first operational amplifier unit is grounded. The power supply terminal of the first operational amplifier unit is connected to a first power supply.

[0013] The active low-pass integration module includes a second resistor, a third resistor, a third capacitive unit, and a second operational amplifier unit. The first end of the second resistor is connected to the output end of the first operational amplifier unit. The second end of the second resistor is connected to the inverting input end of the second operational amplifier unit, the first end of the third resistor, and the first end of the third capacitive unit. The output end of the second operational amplifier unit is connected to the second end of the third resistor and the second end of the third capacitive unit. The non-inverting input end of the second operational amplifier unit is grounded. The power supply end of the second operational amplifier unit is connected to the first power supply.

[0014] In one embodiment, the target capacitive unit includes at least one of a first capacitive unit, a second capacitive unit, and a third capacitive unit; the target capacitive unit includes a first capacitor connected in parallel and at least one capacitor branch; the capacitor branch includes a switch and a second capacitor, a first terminal of the switch is connected to a first terminal of the first capacitor, a second terminal of the switch is connected to a first terminal of the second capacitor, and a control terminal of the switch is used to receive a target sub-control signal, the target sub-control signal being one of the micro-molecule control signal and the integrator control signal; the first terminal of the first capacitor is connected to the first terminal of the second capacitor.

[0015] In one embodiment, when the target capacitive unit includes multiple capacitor branches, the capacitance value of the second capacitor in each capacitor branch is different.

[0016] In one embodiment, the discrimination circuit includes a first-stage amplification unit, a second-stage amplification unit, a first-stage inverting unit, a second-stage inverting unit, a first power supply, a second power supply, a third power supply, and a fourth power supply, wherein...

[0017] The first-stage amplification unit is connected to the active shaping filter circuit, the first power supply, and the second power supply. It is used to receive the preset voltage signal and the shaping signal, and to perform differential amplification processing on the preset voltage signal and the shaping signal to generate a first differential amplification signal.

[0018] The second-stage amplification unit is connected to the first-stage amplification unit, the first power supply, and the second power supply, and is used to perform differential amplification processing on the first differential amplification signal to generate the second differential amplification signal.

[0019] The first-stage inverting unit is connected to the second-stage amplifying unit, the first power supply, and the second power supply, and is used to invert the second differential amplifier signal to generate an analog level signal.

[0020] The second-stage inverting unit is connected to the first-stage inverting unit, the third power supply, and the fourth power supply, and is used to invert the analog level signal to generate the digital level signal.

[0021] The first and second power supplies are used to provide different analog reference voltages, and the third and fourth power supplies are used to provide different digital reference voltages.

[0022] In one embodiment, the readout circuit further includes:

[0023] A scale signal configuration circuit includes at least one scale signal switching unit and a scale signal configuration unit, wherein the scale signal switching unit is connected to the scale signal configuration unit and a charge-sensitive preamplifier circuit respectively. In the case of multiple scale signal switching units, the charge-sensitive preamplifier circuits connected to different scale signal switching units are different.

[0024] The scale signal configuration unit is used to control the on / off state of the scale signal switching unit according to external control commands;

[0025] The scale signal switch unit is used to receive the scale signal, and when it is in the on state, it converts the scale signal into a test charge signal and outputs the test charge signal to the corresponding readout channel to instruct the readout channel to output a digital level signal according to the test charge signal.

[0026] In one embodiment, the scale signal configuration circuit includes multiple scale signal switching units.

[0027] The scale signal configuration unit includes multiple cascaded shift latch subunits, each shift latch subunit being connected to the scale signal switch unit. Each shift latch subunit includes a shift register and a latch, and the shift register and the latch are connected.

[0028] The shift register is used to shift the external control commands and generate control data;

[0029] The latch is used to read the control data and send the control data to the corresponding connected scale signal switch unit to control the on / off state of the scale signal switch unit.

[0030] In one embodiment, the readout circuit includes a plurality of readout channels, a channel selection circuit, a first output pin, and a second output pin;

[0031] The channel selection circuit is connected to the charge-sensitive preamplifier circuit and the active shaping filter circuit in each of the readout channels, as well as the first output pin and the second output pin.

[0032] The channel selection circuit is used to select the path between the target charge-sensitive preamplifier circuit and the first output pin, and to select the path between the target active shaping filter circuit and the second output pin.

[0033] The target charge sensitive preamplifier circuit and the target shaping filter circuit belong to the same readout channel among multiple readout channels.

[0034] Secondly, this application also provides a detector readout chip, including the detector readout circuit provided in any of the above embodiments.

[0035] In the readout circuit and readout chip of the aforementioned detector, the readout circuit includes at least one readout channel. Integrating multiple readout channels together reduces interference from manufacturing processes compared to using discrete components, thus improving readout accuracy. Each readout channel includes a charge-sensitive preamplifier circuit, an active shaping filter circuit, and a discrimination circuit. The charge-sensitive preamplifier circuit amplifies the charge signal output by the detector and outputs an initial voltage signal. The active shaping filter circuit then filters and shapes the initial voltage signal to generate a shaped signal, eliminating the long trailing edge of the initial voltage signal, reducing the pulse width and signal accumulation, and improving the circuit's count rate response. Furthermore, by adjusting the time constant of the active shaping filter circuit based on a control signal, the slope of the rising and falling edges of the signal can be increased, further improving the circuit's count rate response. Finally, the discrimination circuit compares the shaped signal with a preset voltage signal and outputs a digital level signal based on the comparison result, achieving accurate readout of the detector's charge signal. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 One of the readout circuits for a detector provided in one embodiment;

[0038] Figure 2 One embodiment provides a charge-sensitive preamplifier circuit;

[0039] Figure 3 This is a second readout circuit for a detector provided in one embodiment;

[0040] Figure 4 An active shaping filter circuit is provided as one embodiment;

[0041] Figure 5 A discrimination circuit is provided as an embodiment;

[0042] Figure 6 The third readout circuit of the detector provided in one embodiment;

[0043] Figure 7 A scale signal switching unit is provided in one embodiment;

[0044] Figure 8 A scale signal configuration unit is provided in one embodiment;

[0045] Figure 9 The fourth readout circuit of the detector provided in one embodiment;

[0046] Figure 10 A decoder provided in one embodiment.

[0047] Explanation of reference numerals in the attached figures:

[0048] 100 - Readout channel; 110 - Charge-sensitive preamplifier circuit; 120 - Active shaping filter circuit; 121 - Active high-pass differentiating module; 1211 - First capacitive unit; 1212 - Second capacitive unit; 1213 - First operational amplifier unit; 122 - Active low-pass integrating module; 1221 - Second operational amplifier unit; 1222 - Third capacitive unit; 130 - Discrimination circuit; 131 - First stage amplifier unit; 132 - Second stage amplifier unit; 133 - First stage inverting unit; 134 - Second stage inverting unit; 200 - Scale signal configuration circuit; 210 - Scale signal configuration unit; 211 - Shift register; 212 - Latch; 220 - Scale signal switching unit; 300 - Channel selection circuit. Detailed Implementation

[0049] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0051] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0052] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0053] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0054] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0055] In one embodiment, this application provides a readout circuit for a detector, including at least one readout channel 100. When the readout circuit includes multiple readout channels 100, each readout channel 100 operates in parallel, and different readout channels 100 can be used to read out the charge signals of different detectors. Figure 1As shown, the readout channel 100 includes a charge-sensitive preamplifier circuit 110, an active shaping filter circuit 120, and a discrimination circuit 130. The charge-sensitive preamplifier circuit 110 is connected to the detector and the active shaping filter circuit 120, respectively, and the active shaping filter circuit 120 is also connected to the discrimination circuit 130.

[0056] The charge-sensitive preamplifier circuit 110 is used to amplify the charge signal output by the detector and output an initial voltage signal. The charge-sensitive preamplifier circuit 110 can be composed of a low-noise operational amplifier, capacitors, and resistors, and can perform preliminary amplification of the charge signal to obtain the initial voltage signal.

[0057] The active shaping filter circuit 120 receives the control signal, filters and shapes the initial voltage signal under the control signal, and outputs the shaped signal. Compared to the initial voltage signal, the shaped signal has a smaller pulse width and less noise. The time constant of the active shaping filter circuit 120 is controlled by the control signal. The control signal can be generated by a host computer, which can be integrated with the active shaping filter circuit 120 on the same chip, or the control signal can be sent to the readout channel via remote communication. The active shaping filter circuit 120 is generally composed of components such as capacitors, resistors, and operational amplifiers. The control signal can actually adjust the time constant by adjusting the capacitance value, changing the slope of the rising and falling edges of the shaped signal, thereby accelerating the count rate response.

[0058] The discrimination circuit 130 receives a preset voltage signal, compares the formed signal with the preset voltage signal, and outputs a digital level signal based on the comparison result. The preset voltage signal can be a voltage signal pre-set by the host computer. Specifically, the discrimination circuit 130 outputs a first level signal when the voltage value of the formed signal is greater than the preset voltage signal, and outputs a second level signal when the voltage value of the formed signal is less than the preset voltage signal. For example, the first level signal can be a low level signal and the second level signal can be a high level signal, or vice versa.

[0059] In this embodiment, the detector's readout circuit includes at least one readout channel 100. The integration of multiple readout channels 100 together reduces interference from manufacturing processes compared to using discrete components, thus improving readout accuracy. Each readout channel 100 includes a charge-sensitive preamplifier circuit 110, an active shaping filter circuit 120, and a discrimination circuit 130. The charge-sensitive preamplifier circuit 110 is connected to the detector and the active shaping filter circuit 120, and the active shaping filter circuit 120 is also connected to the discrimination circuit 130. The charge signal output by the detector is amplified by the charge-sensitive preamplifier circuit 110 and an initial voltage signal is output. The initial voltage signal is then filtered and shaped by the active shaping filter circuit 120 to generate a shaped signal. This process eliminates the long tail of the initial voltage signal, reduces the pulse width and signal accumulation, and improves the circuit's count rate response. Furthermore, the time constant of the active shaping filter circuit 120 is adjusted based on the control signal to increase the slope of the rising and falling edges of the signal, further improving the circuit's count rate response. Finally, the shaped signal and the preset voltage signal are compared by the discrimination circuit 130, and a digital level signal is output based on the comparison result, thus achieving accurate reading of the detector's charge signal.

[0060] In one embodiment, the charge-sensitive preamplifier circuit 110 may include transistors Q1-Q7 and capacitor Cf. The connection relationship between transistors Q1-Q7 and capacitor Cf is as follows: Figure 2 As shown in the diagram, the gates of transistors Q1-Q4 and Q6 are connected to the BIAS reference circuit of the readout circuit to provide bias. Transistor Q5 can act as a resistor, and its gate voltage can be controlled by an external device, thereby changing its resistance. Transistor Q7 serves as the main amplifying device, amplifying the charge signal.

[0061] In one embodiment, such as Figure 3 As shown, the active shaping filter circuit 120 includes an active high-pass differentiating module 121 and an active low-pass integrating module 122. The active high-pass differentiating module 121 is connected to the charge-sensitive preamplifier circuit 110 and the active low-pass integrating module 122, respectively.

[0062] The active high-pass differentiating module 121 is used to receive the micro-molecule control signal and to perform high-pass differentiating processing on the charge signal to suppress the long tail of the initial voltage signal and output the initial forming signal. The micro-molecule control signal can be sent by a host computer to adjust the time constant of the active high-pass differentiating module 121.

[0063] Furthermore, such as Figure 4As shown, the active high-pass differentiating module 121 includes a first operational amplifier unit 1213, a first capacitive unit 1211, a second capacitive unit 1212, and a first resistor R1. The first terminal of the first capacitive unit 1211 is connected to the charge-sensitive preamplifier circuit 110. The second terminal of the first capacitive unit 1211 is connected to the first terminal of the second capacitive unit 1212, the first terminal of the first resistor R1, and the inverting input terminal of the first operational amplifier unit 1213. The output terminal of the first operational amplifier unit 1213 is connected to the second terminal of the second capacitive unit 1212, the second terminal of the first resistor R1, and the active low-pass integrating module 122. The non-inverting input terminal of the first operational amplifier unit 1213 is grounded. The power supply terminal of the first operational amplifier unit 1213 is connected to the first power supply AVDD. The first capacitive unit 1211 can be a combination of a capacitor and a resistor, and the second capacitive unit 1212 can also be a combination of a capacitor and a resistor. The first resistor R1 can be a single resistor or multiple resistors connected in series or parallel. The first capacitive unit 1211 and the first resistor R1 constitute the differential structure. The second capacitive unit 1212 can be used as a compensation capacitor to avoid self-excited oscillation caused by the equivalent capacitance of the input stage of the first operational amplifier unit 1213, thereby improving the stability of the active high-pass differential module 121.

[0064] The active low-pass integrator module 122 receives the integrator control signal and filters the initial shaping signal to form the shaped signal. Although the long tail of the initial shaping signal is suppressed, it has significant noise and its waveform does not meet the requirements of subsequent circuits. Therefore, the active low-pass integrator module 122 is used to filter the initial shaping signal to obtain a shaped signal with a high signal-to-noise ratio and a flat top. The integrator control signal is sent by the host computer and can be used to adjust the time constant of the active low-pass integrator module 122.

[0065] Furthermore, the active low-pass integrating module 122 includes a second resistor R2, a third resistor R3, a third capacitive unit 1222, and a second operational amplifier unit 1221. The first terminal of the second resistor R2 is connected to the output terminal of the first operational amplifier unit 1221. The second terminal of the second resistor R2 is connected to the inverting input terminal of the second operational amplifier unit 1221, the first terminal of the third resistor R3, and the first terminal of the third capacitive unit 1222. The output terminal of the second operational amplifier unit 1221 is connected to the second terminals of the third resistor R3 and the third capacitive unit 1222. The non-inverting input terminal of the second operational amplifier unit 1221 is grounded. The power supply terminal of the second operational amplifier unit 1222 is connected to the first power supply AVDD. The second resistor R2 can be a single resistor or multiple resistors connected in parallel or series. The third resistor R3 can be a single resistor or multiple resistors connected in parallel or series. The third capacitive unit 1222 can be a combination of a capacitor and a resistor. The second resistor R2 and the third capacitive unit 1222 form an integral structure. The third resistor R3 is connected in parallel with the second operational amplifier unit 1221, which can avoid the infinite low-frequency resistance of the second operational amplifier unit 1221.

[0066] In one embodiment, the target capacitive unit includes at least one of a first capacitive unit 1211, a second capacitive unit 1212, and a third capacitive unit 1222. The target capacitive unit includes a first capacitor connected in parallel and at least one capacitor branch. The capacitor branch includes a switch and a second capacitor, with a first terminal of the switch connected to a first terminal of the first capacitor and a second terminal of the switch connected to a first terminal of the second capacitor. The control terminal of the switch is used to receive a target sub-control signal, which is one of a micro-molecule control signal and an integrator control signal. The first terminal of the first capacitor is connected to the first terminal of the second capacitor. Exemplarily, the switch can be a transistor.

[0067] For example, such as Figure 4 As shown, the first capacitive unit 1211 may include a capacitor C1 and multiple capacitor branches. Each capacitor branch includes a capacitor C2 and a switch S1. The connection relationship between capacitor C1 and S1 is as follows: Figure 4 As shown. Switch S1 can be used to receive micro-molecule control signals and, under the influence of these signals, be in an on or off state to change the capacitance value of the first capacitive unit 1211, thereby changing the time constant of the active high-pass differential module 121.

[0068] Optionally, the second capacitive unit 1212 may include a capacitor C3 and multiple capacitor branches, each capacitor branch including a capacitor C4 and a switch S2, the connection relationship of capacitor C4 and switch S2 being as follows: Figure 4As shown. Switch S2 can be used to receive micro-molecule control signals and, under the influence of these signals, be in an on or off state to change the capacitance value of the second capacitive unit 1212, thereby changing the time constant of the active high-pass differential module 121.

[0069] Optionally, the third capacitive unit 1222 may include a capacitor C5 and multiple capacitor branches. Each capacitor branch includes a capacitor C6 and a switch S3, and the connection relationship between capacitor C6 and switch S3 is shown in the figure. Switch S3 can be used to receive an integrator control signal and, under the action of the integrator control signal, be in an on or off state to change the capacitance value of the third capacitive unit 1222, thereby changing the time constant of the active low-pass integrator module 122.

[0070] In one embodiment, when the target capacitive unit includes multiple capacitor branches, the capacitance value of the second capacitor in each capacitor branch is different.

[0071] In one embodiment, when the target capacitive unit includes multiple capacitor branches, the capacitance value of the second capacitor in each capacitor branch is the same.

[0072] In one embodiment, the first operational amplifier unit may include transistor Q8 and a first active load network, wherein the first active load network may include transistors Q9 to Q12, and the connection relationship of each transistor is as follows: Figure 4 As shown. The gate voltage of each transistor can be provided by the BIAS reference circuit in the readout circuit. The BIAS reference circuit provides different gate voltages to the transistors, allowing the transistors to operate during different operating periods. It can also provide different load impedances to transistor Q8, thereby changing the amplification factor of the first operational amplifier unit 1213 on the initial voltage signal.

[0073] In one embodiment, the second operational amplifier unit may include transistor Q13 and a second active load network, wherein the second active load network may include transistors Q14 to Q17, and the connection relationship of each transistor is as follows: Figure 4 As shown. The gate voltage of each transistor can be provided by the BIAS reference circuit in the readout circuit. The BIAS reference circuit provides different gate voltages to the transistors, allowing the transistors to operate during different operating periods. It can also provide different load impedances to transistor Q13, thereby changing the amplification factor of the second operational amplifier unit 1221 on the initial shaped signal.

[0074] In one embodiment, such as Figure 5As shown, the discrimination circuit 130 includes a first-stage amplification unit 131, a second-stage amplification unit 132, a first-stage inverting unit 133, a second-stage inverting unit 134, a first power supply AVDD, a second power supply AVSS, a third power supply DVDD, and a fourth power supply DVSS.

[0075] The first-stage amplification unit 131 is connected to the active shaping filter circuit 120, the first power supply AVDD, and the second power supply AVSS. It receives a preset voltage signal and a shaping signal, and performs differential amplification on the preset voltage signal and the shaping signal to generate a first differential signal. Further, as... Figure 5 As shown, the first-stage amplification unit 131 may include transistors Q18 to Q22. Transistors Q18 and Q19 are used for differential amplification of the preset voltage signal and the shaped signal. Transistors Q18 and Q19 may be NMOS transistors with large gm values ​​to provide high gain and fast response. Transistor Q20 serves as the tail current source of the first-stage amplification unit, while transistors Q21 and Q22 function as unidirectional conductors.

[0076] The second-stage amplifier unit 132 is connected to the first-stage amplifier unit 131, the first power supply AVDD, and the second power supply AVSS. It is used to perform differential amplification processing on the first differential signal to generate the second differential signal. For example... Figure 5 As shown, the second-stage amplification unit may include transistors Q23-Q29. Transistors Q23 and Q24 are used to perform further differential amplification on the first differential signal. Transistors Q23 and Q24 can be PMOS transistors with weak bulk effects. Transistor Q29 serves as the tail current source, and transistors Q25-Q28 form a positive feedback network. The second-stage amplification unit 132 is a positive feedback differential amplifier, which can improve the linearity of the output second differential signal.

[0077] The first-stage inverting unit 133 is connected to the second-stage amplifying unit 132, the first power supply AVDD, and the second power supply AVSS. It is used to invert the second differential amplifier signal to generate an analog level signal. For example... Figure 5 As shown, the first-stage inverter unit may include transistors Q30 to Q35, wherein transistors Q30 to Q31 constitute the first-stage inverter, transistors Q34 to Q35 constitute the second-stage inverter, transistor Q32 acts as a pull-up transistor, and transistor Q33 acts as a pull-down transistor to realize the push-pull output of analog level signals.

[0078] The second-stage inverting unit 134 is connected to the first-stage inverting unit 133, the third power supply DVDD, and the fourth power supply DVSS, and is used to invert the analog level signal to generate a digital level signal. The second-stage inverting unit may include transistors Q36 to Q37.

[0079] In this system, the first power supply AVDD and the second power supply AVSS provide different analog reference voltages, while the third power supply DVDD and the fourth power supply DVSS provide different digital reference voltages. The first power supply AVDD can be considered an analog power supply, the second power supply AVSS can be considered an analog ground, the third power supply DVDD can be considered a digital power supply, and the fourth power supply DVDD can be considered a digital ground. The first-stage inverting unit 133 uses the first power supply AVDD and the second power supply AVSS, while the second-stage inverting unit 134 uses the third power supply DVDD and the fourth power supply DVSS, thus realizing the conversion of the signal from analog level to digital level.

[0080] In one embodiment, such as Figure 6 As shown, the readout circuit also includes a scale signal configuration circuit 200. The scale signal configuration circuit 200 includes at least one scale signal switching unit 220 and a scale signal configuration unit 210, wherein the scale signal switching unit 220 is connected to the scale signal configuration unit 210 and a charge-sensitive preamplifier circuit 110, respectively. In the case of including multiple scale signal switching units 220, the charge-sensitive preamplifier circuits 110 connected to different scale signal switching units 220 are different.

[0081] The scale signal configuration unit 210 controls the on / off state of the scale signal switch unit 220 according to external control commands. The scale signal switch unit 220 receives the scale signal and, when in the on state, converts the scale signal into a test charge signal and outputs the test charge signal to the corresponding connected readout channel to instruct the readout channel to output a digital level signal according to the test charge signal. The scale signal is a voltage signal used to test the performance of the readout circuit, and the scale signal can be provided by an external power supply. Specifically, the scale signal switch unit 220 may include a switching transistor S4 and a scale capacitor Ct, and the connection relationship between the switching transistor S4 and the scale capacitor Ct is as follows: Figure 7 As shown. When the switching transistor S4 is in the on state, the scale signal is transmitted to the scale capacitor Ct. The scale capacitor Ct converts the scale signal into a test charge signal and outputs it to the corresponding connected readout channel 100 to test the performance of the readout channel 100.

[0082] In one embodiment, such as Figure 6 As shown, the scale signal configuration circuit includes multiple scale signal switching units 220. For example... Figure 8 As shown, the scale signal configuration unit 210 includes multiple cascaded shift latch subunits. The shift latch subunits are connected to the scale signal switch unit 220. The shift latch subunits include a shift register 211 and a latch 212, which are connected.

[0083] Shift register 211 is used to shift external control commands to generate control data. Latch 212 is used to read the control data and send it to the corresponding connected scale signal switch unit 220 to control the on / off state of the scale signal switch unit 220. The external control command indicates the readout channel 100 to be tested, and the external control command can be a frame of serial data. The external control command is input into shift register 211. After shifting the external control command, shift register 211 generates and temporarily stores the corresponding control data. Then, the corresponding latch 212 reads and stores the control data. When testing the readout circuit, the control data can be sent to the corresponding connected scale signal switch unit 210.

[0084] In one embodiment, such as Figure 9 As shown, the readout circuit includes multiple readout channels 100, a channel selection circuit 300, a first output pin, and a second output pin.

[0085] The channel selection circuit 300 is connected to the charge-sensitive preamplifier circuit 110 and the active shaping filter circuit 120 in each readout channel 100, as well as the first output pin and the second output pin.

[0086] The channel selection circuit 300 is used to select the path between the target charge-sensitive preamplifier circuit 110 and the first output pin, so as to output an initial voltage signal through the first output pin, facilitating performance testing of the target charge-sensitive preamplifier circuit 110. It also selects the path between the target active shaping filter circuit 120 and the second output pin, so as to output a shaping signal through the second output pin, facilitating performance testing of the target active shaping filter circuit 120. The target charge-sensitive preamplifier circuit and the target shaping filter circuit belong to the same readout channel 100 among multiple readout channels 100.

[0087] In some embodiments, the channel selection circuit 300 may not be connected in a one-to-one correspondence with each read channel. For example, if there are 32 read channels 100, they can be divided into 4 groups, with the channel selection circuit connected only to the first read channel in each group. The channel selection circuit may include, for example,... Figure 10 The decoder shown.

[0088] In one embodiment, this application also provides a detector readout chip, which includes the detector readout circuit provided in any of the above embodiments.

[0089] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0090] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0091] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A readout circuit for a detector, comprising at least one readout channel, characterized in that, The readout channel includes: A charge-sensitive preamplifier circuit, connected to the detector, is used to amplify the charge signal output by the detector and output an initial voltage signal. An active shaping filter circuit, connected to the charge-sensitive preamplifier circuit, is used to receive a control signal, filter and shape the initial voltage signal under the action of the control signal, and output a shaped signal; the time constant of the active shaping filter circuit is controlled by the control signal. The discrimination circuit is connected to the active shaping filter circuit, and is used to receive a preset voltage signal, compare the shaping signal and the preset voltage signal, and output a digital level signal according to the comparison result.

2. The readout circuit of the detector according to claim 1, characterized in that, The control signal includes an integrator control signal and a micromolecule control signal, and the active shaping filter circuit includes: An active high-pass differentiator module is connected to the charge-sensitive preamplifier circuit to receive the micro-molecule control signal and to perform high-pass differentiator processing on the charge signal to suppress the long tail portion of the initial voltage signal and output the initial shaping signal. An active low-pass integrator module, connected to the active high-pass differential module, is used to receive the integrator control signal and to filter the initial shaping signal to form the shaping signal.

3. The readout circuit of the detector according to claim 2, characterized in that, The active high-pass differential module includes a first operational amplifier unit, a first capacitive unit, a second capacitive unit, and a first resistor. The first terminal of the first capacitive unit is connected to the charge-sensitive preamplifier circuit. The second terminal of the first capacitive unit is connected to the first terminal of the second capacitive unit, the first terminal of the first resistor, and the inverting input terminal of the first operational amplifier unit. The output terminal of the first operational amplifier unit is connected to the second terminal of the second capacitive unit, the second terminal of the first resistor, and the active low-pass integral module. The non-inverting input terminal of the first operational amplifier unit is grounded. The power supply terminal of the first operational amplifier unit is connected to a first power supply. The active low-pass integration module includes a second resistor, a third resistor, a third capacitive unit, and a second operational amplifier unit. The first end of the second resistor is connected to the output end of the first operational amplifier unit. The second end of the second resistor is connected to the inverting input end of the second operational amplifier unit, the first end of the third resistor, and the first end of the third capacitive unit. The output end of the second operational amplifier unit is connected to the second end of the third resistor and the second end of the third capacitive unit. The non-inverting input end of the second operational amplifier unit is grounded. The power supply end of the second operational amplifier unit is connected to the first power supply.

4. The readout circuit of the detector according to claim 3, characterized in that, The target capacitive unit includes at least one of a first capacitive unit, a second capacitive unit, and a third capacitive unit; the target capacitive unit includes a first capacitor connected in parallel and at least one capacitor branch; the capacitor branch includes a switch and a second capacitor, the first terminal of the switch is connected to the first terminal of the first capacitor, the second terminal of the switch is connected to the first terminal of the second capacitor, the control terminal of the switch is used to receive a target sub-control signal, the target sub-control signal being one of the micro-molecule control signal and the integrator control signal; the first terminal of the first capacitor is connected to the first terminal of the second capacitor.

5. The readout circuit of the detector according to claim 4, characterized in that, When the target capacitive unit includes multiple capacitor branches, the capacitance value of the second capacitor in each capacitor branch is different.

6. The readout circuit of the detector according to any one of claims 1-5, characterized in that, The discrimination circuit includes a first-stage amplification unit, a second-stage amplification unit, a first-stage inverting unit, a second-stage inverting unit, a first power supply, a second power supply, a third power supply, and a fourth power supply, wherein... The first-stage amplification unit is connected to the active shaping filter circuit, the first power supply, and the second power supply. It is used to receive the preset voltage signal and the shaping signal, and to perform differential amplification processing on the preset voltage signal and the shaping signal to generate a first differential amplification signal. The second-stage amplification unit is connected to the first-stage amplification unit, the first power supply, and the second power supply, and is used to perform differential amplification processing on the first differential amplification signal to generate the second differential amplification signal. The first-stage inverting unit is connected to the second-stage amplifying unit, the first power supply, and the second power supply, and is used to invert the second differential amplifier signal to generate an analog level signal. The second-stage inverting unit is connected to the first-stage inverting unit, the third power supply, and the fourth power supply, and is used to invert the analog level signal to generate the digital level signal. The first and second power supplies are used to provide different analog reference voltages, and the third and fourth power supplies are used to provide different digital reference voltages.

7. The readout circuit of the detector according to claim 1, characterized in that, The readout circuit also includes: A scale signal configuration circuit includes at least one scale signal switching unit and a scale signal configuration unit, wherein the scale signal switching unit is connected to the scale signal configuration unit and a charge-sensitive preamplifier circuit respectively. In the case of multiple scale signal switching units, the charge-sensitive preamplifier circuits connected to different scale signal switching units are different. The scale signal configuration unit is used to control the on / off state of the scale signal switching unit according to external control commands; The scale signal switch unit is used to receive the scale signal, and when it is in the on state, it converts the scale signal into a test charge signal and outputs the test charge signal to the corresponding readout channel to instruct the readout channel to output a digital level signal according to the test charge signal.

8. The readout circuit of the detector according to claim 7, characterized in that, The scale signal configuration circuit includes multiple scale signal switching units. The scale signal configuration unit includes multiple cascaded shift latch subunits, each shift latch subunit being connected to the scale signal switch unit. Each shift latch subunit includes a shift register and a latch, and the shift register and the latch are connected. The shift register is used to shift the external control commands and generate control data; The latch is used to read the control data and send the control data to the corresponding connected scale signal switch unit to control the on / off state of the scale signal switch unit.

9. The readout circuit of the detector according to claim 1, characterized in that, The readout circuit includes multiple readout channels, a channel selection circuit, a first output pin, and a second output pin. The channel selection circuit is connected to the charge-sensitive preamplifier circuit and the active shaping filter circuit in each of the readout channels, as well as the first output pin and the second output pin. The channel selection circuit is used to select the path between the target charge-sensitive preamplifier circuit and the first output pin, and to select the path between the target active shaping filter circuit and the second output pin. The target charge sensitive preamplifier circuit and the target shaping filter circuit belong to the same readout channel among multiple readout channels.

10. A readout chip for a detector, characterized in that, Includes the readout circuit of the detector as described in any one of claims 1-9.

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