Interface circuit with filtering function

Abstract

The invention discloses an interface circuit with a filtering function. The interface circuit comprises a first decision circuit, a first shaping circuit, a charge pump circuit, a band-gap reference circuit, a first comparator, a second shaping circuit, a pulse width compensation circuit and a buffer circuit. Wherein the charge pump circuit, the band-gap reference circuit and the first comparator form a filtering module, so that noise within the specified time can be effectively filtered, and the accuracy and the stability of signals are ensured.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor, and particularly relates to an interface circuit with filtering function. BACKGROUND

[0002] As a bridge for connecting electronic devices with the outside, the input and output signals of the interface circuit are often affected by the external environment. With the continuous progress of integrated circuit technology, the integration of chips is getting higher and higher, and the working frequency of the circuit is getting faster and faster. This makes the electronic device have higher and higher requirements for the processing speed and accuracy of signals. At the same time, the signals in the high-speed circuit are more susceptible to interference, resulting in signal distortion and other problems. For example, in a high-speed data transmission interface such as a PCI-Express interface, the data transmission rate can reach several Gbps or even higher. In such a high-speed signal transmission process, even a small disturbance can cause data errors. The interface circuit with filtering function can be designed according to the characteristics of high-speed signals, and appropriate filtering techniques such as high-frequency filtering, low-pass filtering, etc. can be used to ensure the quality of high-speed signals and meet the requirements of integrated circuit technology development for signal processing.

[0003] The ordinary interface circuit does not have filtering function and has many shortcomings: the quality of the power supply is required to be high, and the noise and ripple in the power supply will directly affect the quality of the signal. If the power supply is unstable, it will cause the output signal of the interface circuit to be distorted, drifted, etc., affecting the performance of the device; because the transmission signal is susceptible to interference, it is mixed with noise, and data errors are prone to occur during transmission. SUMMARY

[0004] The application provides an interface circuit with filtering function to solve the problems in the prior art.

[0005] To achieve the above purpose, the application provides an interface circuit with filtering function, which comprises a first decision circuit, a first shaping circuit, a filtering module, a second shaping circuit, a pulse width compensation circuit and a buffer circuit connected in sequence.

[0006] The first decision circuit is used for determining the high and low levels of the input signal and outputting a decision signal to the first shaping circuit.

[0007] The filtering module is used for filtering the output voltage of the first shaping circuit to obtain a filtered voltage.

[0008] The filtered voltage is transmitted to the pulse width compensation circuit for pulse width compensation after being shaped by the second shaping circuit.

[0009] The buffer circuit is used for enhancing the driving capability of the signal after pulse width compensation.

[0010] Optionally, the filtering module comprises a charge pump circuit, a bandgap reference circuit and a first comparator.

[0011] The charge pump circuit is used to detect the output voltage of the first shaping circuit in real time, and transmit the output signal to the positive input terminal of the first comparator; the bandgap reference circuit generates a first charging current for the charge pump circuit; the first bias voltage is supplied to the first comparator; the first reference voltage is connected to the negative input terminal of the first comparator; if the voltage of the charge pump is higher than the first reference voltage generated by the bandgap reference, the first comparator outputs a high level, otherwise the first comparator outputs a low level.

[0012] Optionally, the first decision circuit comprises a Schmitt trigger and a transistor M6, the Schmitt trigger comprises a transistor M1, a transistor M2, a transistor M3, a transistor M4 and a transistor M5, a source terminal of the transistor M1 is connected to a power supply VDD, a drain terminal of the transistor M1 is connected to a source terminal of the transistor M2 and a source terminal of the transistor M5, a drain terminal of the transistor M2 is connected to a drain terminal of the transistor M3, a gate terminal of the transistor M5 and a gate terminal of the transistor M6, a source terminal of the transistor M3 is connected to a drain terminal of the transistor M4 and a source terminal of the transistor M6, and a source terminal of the transistor M4 is connected to a power supply GND; gate terminals of the transistor M1, the transistor M2, the transistor M3 and the transistor M4 are connected to each other to form an input terminal; a drain terminal of the transistor M5 is connected to the power supply GND, and a drain terminal of the transistor M6 is connected to the power supply VDD.

[0013] Optionally, the first shaping circuit comprises two inverters, which are respectively composed of a transistor M7, a transistor M8 and a transistor M9, a transistor M10, gate terminals of the transistor M7 and the transistor M8 are connected, and receive an output signal of the Schmitt trigger, a source terminal of the transistor M7 is connected to the power supply VDD, a source terminal of the transistor M8 is connected to the power supply GND, and a drain terminal of the transistor M7 and a drain terminal of the transistor M8 are connected to form an output terminal; gate terminals of the transistor M9 and the transistor M10 are connected, and receive the output signal of the Schmitt trigger, a source terminal of the transistor M9 is connected to the power supply VDD, a source terminal of the transistor M10 is connected to the power supply GND, and a drain terminal of the transistor M9 and a drain terminal of the transistor M10 are connected to form an output terminal.

[0014] Optionally, the second shaping circuit comprises an inverter composed of a transistor M18 and a transistor M19, a source terminal of the transistor M18 is connected to the power supply VDD, a source terminal of the transistor M19 is connected to the power supply GND, a drain terminal of the transistor M18 and a drain terminal of the transistor M19 are connected to form an output terminal, and gate terminals of the transistor M18 and the transistor M19 are connected, and receive an output signal of the first comparator.

[0015] Optionally, the pulse width compensation circuit comprises transistor M20, transistor M21, transistor M22, transistor M23 and resistor R1, the gate terminals of transistor M20 and transistor M21 are connected, and receive the output signal of the second shaping circuit, the source terminal of transistor M20 is connected to power supply VDD, the source terminal of transistor M21 is connected to power supply GND, the drain terminal of transistor M20 is connected to the first terminal of resistor R1 and constitutes an output terminal, and the drain terminal of transistor M21 is connected to the second terminal of resistor R1; the gate terminals of transistor M22 and transistor M23 are connected, and receive the output signal of the previous stage inverter, the source terminal of transistor M22 is connected to power supply VDD, the source terminal of transistor M23 is connected to power supply GND, the drain terminal of transistor M22 and the drain terminal of transistor M23 are connected and constitute an output terminal.

[0016] Optionally, the buffer circuit comprises transistor M24 and transistor M25, which constitute an inverter, the gate terminals of transistor M24 and transistor M25 are connected, and receive the output signal of the pulse width compensation circuit, the source terminal of transistor M24 is connected to power supply VDD, the source terminal of transistor M25 is connected to power supply GND, the drain terminal of transistor M24 and the drain terminal of transistor M25 are connected and constitute an output terminal.

[0017] Optionally, the charge pump circuit comprises switch NMOS1 and charging capacitor C1, the gate terminal of switch NMOS1 receives the output signal of the first shaping circuit, the drain terminal is connected to the positive input terminal of the first comparator and the upper terminal of charging capacitor C1, and flows into the first charging current generated by the bandgap reference, and the source terminal of switch NMOS1 is connected to the lower terminal of charging capacitor C1 and is connected to power supply GND.

[0018] Optionally, the bandgap reference circuit generates the first charging current for the charge pump circuit, generates the first bias voltage for the first comparator, and generates the first reference voltage connected to the negative input terminal of the first comparator.

[0019] Optionally, the first comparator comprises transistor M11, transistor M12, transistor M13, transistor M14, transistor M15, transistor M16 and transistor M17, the source terminals of transistor M12 and transistor M13 are connected to the drain terminal of transistor M11, the drain terminal of transistor M12 and the drain terminal and gate terminal of transistor M14, and the gate terminal of transistor M15 are connected, the drain terminal of transistor M13 and the drain terminal of transistor M15 are connected and constitute the first stage output of the first comparator, which is input to the gate terminal of transistor M17; the drain terminal of transistor M16 and the drain terminal of transistor M17 are connected and constitute the second stage output of the first comparator; the source terminals of transistor M11 and transistor M16 are connected to power supply VDD, and the gate terminals are connected to the first bias voltage, the source terminals of transistor M14, transistor M15 and transistor M17 are connected to power supply GND; the gate terminal of transistor M12 is the negative input terminal of the first comparator, and the gate terminal of transistor M13 is the positive input terminal of the first comparator.

[0020] Compared with the prior art, the present invention has the following advantages and technical effects:

[0021] This invention provides an interface circuit with filtering functionality, comprising a voltage decision circuit, a signal shaping circuit, a filtering circuit, a single-threshold decision circuit, a pulse width modulation circuit, and a buffer circuit. Compared to traditional interface circuits without filtering functionality, this circuit ensures signal accuracy and stability through filtering, thereby improving the reliability of data transmission. During data transmission, it reduces the bit error rate, ensuring accurate data transmission. Furthermore, it provides a more stable operating environment for the device, reducing malfunctions caused by external interference and internal noise. Simultaneously, it can filter noise and ripple in the power supply, reducing the power supply's impact on the signal. It enables the interface circuit to operate in a relatively stable power supply environment, reducing signal distortion caused by power supply fluctuations. Attached Figure Description

[0022] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0023] Figure 1 This is a block diagram of the interface circuit structure according to an embodiment of the present invention;

[0024] Figure 2 This is an interface circuit diagram of an embodiment of the present invention;

[0025] Figure 3 This is a voltage waveform diagram of the interface circuit in an embodiment of the present invention during operation. Detailed Implementation

[0026] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0027] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0028] Example 1

[0029] like Figures 1-2 As shown, this embodiment provides an interface circuit with filtering function, including a first decision circuit, a first shaping circuit, a filtering module, a second shaping circuit, a pulse width compensation circuit, and a buffer circuit connected in sequence.

[0030] The first decision circuit is configured to determine high and low levels of an input signal and output a decision signal to the first shaping circuit.

[0031] The filter module is configured to filter an output voltage of the first shaping circuit to obtain a filtered voltage.

[0032] The filtered voltage is transmitted to the pulse width compensation circuit for pulse width compensation after being shaped by the second shaping circuit.

[0033] The buffer circuit is configured to enhance driving capability of the signal after pulse width compensation.

[0034] The filter module comprises a charge pump circuit, a bandgap reference circuit and a first comparator.

[0035] The charge pump circuit is configured to detect an output voltage of the first shaping circuit in real time and transmit an output signal to a positive input terminal of the first comparator; the bandgap reference circuit generates a first charging current for the charge pump circuit; the first bias voltage is supplied to the first comparator; a first reference voltage is connected to a negative input terminal of the first comparator; if the voltage of the charge pump is higher than the first reference voltage generated by the bandgap reference, the first comparator outputs a high level, otherwise the first comparator outputs a low level.

[0036] Further, the first decision circuit comprises a Schmitt trigger and a transistor M6, the Schmitt trigger comprises a transistor M1, a transistor M2, a transistor M3, a transistor M4 and a transistor M5, a source terminal of the transistor M1 is connected to a power supply VDD, a drain terminal of the transistor M1 is connected to a source terminal of the transistor M2 and a source terminal of the transistor M5, a drain terminal of the transistor M2 is connected to a drain terminal of the transistor M3, a gate terminal of the transistor M5 and a gate terminal of the transistor M6, a source terminal of the transistor M3 is connected to a drain terminal of the transistor M4 and a source terminal of the transistor M6, and a source terminal of the transistor M4 is connected to a power supply GND. The gate terminals of the transistor M1, the transistor M2, the transistor M3 and the transistor M4 are connected to each other to form an input terminal. The drain terminal of the transistor M5 is connected to the power supply GND, and the drain terminal of the transistor M6 is connected to the power supply VDD, corresponding Figure 1 The first decision circuit in the structural block diagram. The Schmitt trigger itself has the characteristics of double threshold, and has certain anti-interference characteristics.

[0037] Further, the first shaping circuit comprises two inverters, transistor M7 and transistor M8 constitute an inverter, transistor M9 and transistor M10 constitute an inverter. The gate terminals of transistor M7 and transistor M8 are connected, receiving the output signal of the Schmitt trigger, the source terminal of transistor M7 is connected to the power supply VDD, the source terminal of transistor M8 is connected to the power supply GND, the drain terminals of transistor M7 and transistor M8 are connected to constitute an output terminal. The gate terminals of transistor M9 and transistor M10 are connected, receiving the output signal of the Schmitt trigger, the source terminal of transistor M9 is connected to the power supply VDD, the source terminal of transistor M10 is connected to the power supply GND, the drain terminals of transistor M9 and transistor M10 are connected to constitute an output terminal, and the two inverters correspond to the first shaping circuit in the structural diagram. Since the output signal of the Schmitt trigger may have jitter, an inverter is used to shape the signal, and the on-off of the switch NMOS1 in the subsequent filter circuit is controlled.

[0038] Further, the switch NMOS1 and the charging capacitor C1 constitute a charge pump circuit, the gate terminal of the switch NMOS1 receives the output signal of the first shaping circuit, the drain terminal is connected to the positive input terminal of the first comparator, and the node is not only connected to the upper end of the charging capacitor C1, but also flows into the first charging current generated by the bandgap reference (the bandgap reference circuit is not drawn). The source terminal of the switch NMOS1 is connected to the lower end of the charging capacitor C1 and is connected to the power supply GND. The charge pump circuit is mainly used for "timing", and since the charging voltage and time of the capacitor are linearly related, the corresponding charging time is designed according to this characteristic, so as to achieve the effect of filtering.

[0039] When the input signal is high, the output low-level switch signal is obtained after the first shaping circuit, at this time, NMOS1 is off, the charging capacitor C1 starts to charge, and when the charge pump voltage is greater than the first reference voltage, the first comparator outputs a high-level signal. Conversely, when the input signal is low, the switch signal is high, the switch NMOS1 is turned on, and the bypass charging capacitor C1 is bypassed, so that the charge on the charging capacitor C1 is zero, and the first comparator outputs a low-level signal. If the circuit is disturbed by noise, a short-pulse disturbance pulse is generated to make the capacitor start to charge, and when the disturbance pulse ends, the switch signal is high, and the charge on the charging capacitor C1 is zero.

[0040] Further, the first comparator comprises transistor M11, transistor M12, transistor M13, transistor M14, transistor M15, transistor M16 and transistor M17, the source terminals of transistor M12 and transistor M13 are connected with the drain terminal of transistor M11, the drain terminal of transistor M12 and the drain terminal and the gate terminal of transistor M14, the gate terminal of transistor M15 are connected, the drain terminal of transistor M13 and the drain terminal of transistor M15 are connected to constitute the first stage output of the first comparator, and are input to the gate terminal of transistor M17. The drain terminal of transistor M16 and the drain terminal of transistor M17 are connected to constitute the second stage output of the first comparator. The source terminals of transistor M11 and transistor M16 are connected with the power supply VDD, and the gate terminals are connected with the first bias voltage, the source terminals of transistor M14, transistor M15 and transistor M17 are connected with the power supply GND. The gate terminal of transistor M12 is the negative input terminal of the first comparator, and the gate terminal of transistor M13 is the positive input terminal of the first comparator. Transistor M11, transistor M12, transistor M13, transistor M14 and transistor M15 together constitute the first stage of the first comparator, and the second stage of the first comparator is composed of transistor M16 and transistor M17. Among them, transistor M11 and transistor M16 are current source tubes, which provide correct working current for the first comparator and ensure the normal work of the first comparator. The gain and comparison accuracy of the comparator are closely related, so two-stage comparator is selected in the design. The first comparator and the charge pump circuit together constitute the filtering module.

[0041] Further, the second shaping circuit comprises an inverter composed of transistor M18 and transistor M19, the source terminal of transistor M18 is connected with the power supply VDD, the source terminal of transistor M19 is connected with the power supply GND, the drain terminal of transistor M18 and the drain terminal of transistor M19 are connected to constitute the output terminal, and the gate terminals of transistor M18 and transistor M19 are connected to receive the output signal of the first comparator.

[0042] Further, the transistor M20, the transistor M21, the transistor M22, the transistor M23 and the resistor R1 constitute a pulse width compensation circuit, the gate terminals of the transistor M20 and the transistor M21 are connected, and the output signal of the second shaping circuit is received, the source terminal of the transistor M20 is connected to the power supply VDD, the source terminal of the transistor M21 is connected to the power supply GND, the drain terminal of the transistor M20 is connected to the first terminal of the resistor R1 and constitutes an output terminal, and the drain terminal of the transistor M21 is connected to the second terminal of the resistor R1. The gate terminals of the transistor M22 and the transistor M23 are connected, and the output signal of the former stage inverter is received, the source terminal of the transistor M22 is connected to the power supply VDD, the source terminal of the transistor M23 is connected to the power supply GND, and the drain terminal of the transistor M22 and the drain terminal of the transistor M23 are connected to constitute an output terminal. The inverter constituted by the transistor M20, the transistor M21 and the resistor R1 has a delay effect on the rising edge of the transmission signal, and has no effect on the falling edge of the transmission signal. Therefore, when the input signal is high, after a set filtering time, the comparison output high level is transmitted to the input terminal of the pulse width shaping circuit, and the corresponding low level signal is transmitted through the inverter constituted by the transistor M20, the transistor M21 and the resistor R1, and a high level signal is output, but the high level part of the signal is an arc, and is no longer a "square wave" signal with straight up and down, at this time, whether the signal is high or low is determined according to the threshold voltage of the latter stage inverter constituted by the transistor M22 and the transistor M23. Therefore, reasonable adjustment of the resistor R1 and the threshold voltage can compensate for the loss of the signal pulse width.

[0043] Further, the buffer circuit is constituted by the transistor M24 and the transistor M25 as an inverter, the gate terminals of the transistor M24 and the transistor M25 are connected, and the output signal of the pulse width compensation circuit is received, the source terminal of the transistor M24 is connected to the power supply VDD, the source terminal of the transistor M25 is connected to the power supply GND, and the drain terminal of the transistor M24 and the drain terminal of the transistor M25 are connected to constitute an output terminal.

[0044] Figure 3 The timing diagram of the inventive circuit is shown in the figure, where VRH and VRL are the upper and lower threshold values of the Schmidt trigger, which will be analyzed in detail as follows:

[0045] t0-t1: The input signal starts to rise, but does not reach the high threshold voltage VRH of the Schmidt trigger, and the subsequent circuit remains unchanged.

[0046] t1-t2: The input signal is higher than the threshold voltage VRH, but the duration is short, which can be understood as noise interference at this time. The duration is short, the charge pump voltage starts to rise but does not reach the first reference voltage, and the output voltage of the first comparator remains low. The high level pulse is filtered out.

[0047] t2-t3: The input signal rises to a high level again after interference.

[0048] t3-t4: the time period is the set filter time, when the duration of the high level of the input signal does not exceed the filter time, it will be filtered out.

[0049] t4-t5: at this time, the duration of the high level of the input signal has exceeded the set filter time, the charge pump voltage exceeds the first comparator voltage, the first comparator output voltage is high, and the output signal is also high.

[0050] t5-t6: the input signal starts to drop, at this time, the switch signal, the first comparator and the charge pump voltage are all low, but the compensation signal is slow due to the existence of resistor R1, at this time, the voltage has not yet dropped below the threshold voltage of the inverter in the pulse compensation circuit, so the output signal remains high.

[0051] t6-t7: the input signal is reduced to low level, and each voltage signal remains in the previous stage state.

[0052] t7: the voltage of the compensation signal continues to decrease, and finally drops below the threshold voltage in the compensation circuit, the output signal becomes low, at this time, the pulse width compensation of the signal is completed.

[0053] Compared with other interface circuits, the advantages of the present application include:

[0054] There is an anti-interference advantage, which can ensure the stability of the circuit under noise interference;

[0055] High precision filter time, because the bandgap reference circuit is added in the circuit, the generated voltage does not change with temperature and voltage, so the first reference voltage and the first charging current have high precision, which can realize accurate filter time;

[0056] Good expansibility, the charging current control circuit can be added to adjust the recovery time;

[0057] Low cost, easy to design, easy to copy, small layout area and low cost.

[0058] The above is only the preferred specific embodiment of the present application, but the protection scope of the present application is not limited thereto, any skilled person in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An interface circuit with filtering function, characterized in that, The first decision circuit, the first shaping circuit, the filtering module, the second shaping circuit, the pulse width compensation circuit and the buffer circuit are sequentially connected. The first decision circuit is used for judging high and low levels of an input signal and outputting a decision signal to the first shaping circuit. The filtering module is used for filtering an output voltage of the first shaping circuit to obtain a filtering voltage. The filtering voltage is transmitted to the pulse width compensation circuit for pulse width compensation after being shaped by the second shaping circuit. The buffer circuit is used for enhancing driving capability of the signal after pulse width compensation.

2. The circuit of claim 1, wherein, The filtering module comprises a charge pump circuit, a bandgap reference circuit and a first comparator. The charge pump circuit is used for detecting the output voltage of the first shaping circuit in real time and transmitting an output signal to a positive input terminal of the first comparator. The bandgap reference circuit generates a first charging current for the charge pump circuit, a first bias voltage for the first comparator and a first reference voltage connected to a negative input terminal of the first comparator.

3. The circuit of claim 1, wherein The first decision circuit comprises a Schmitt trigger and a transistor M6. The Schmitt trigger comprises transistors M1, M2, M3, M4 and M5.

4. The circuit of claim 1, wherein, The source terminal of the transistor M1 is connected to a power supply VDD, the drain terminal of the transistor M1 is connected to the source terminal of the transistor M2 and the source terminal of the transistor M5, the drain terminal of the transistor M2 is connected to the drain terminal of the transistor M3, the gate terminal of the transistor M5 and the gate terminal of the transistor M6, the source terminal of the transistor M3 is connected to the drain terminal of the transistor M4 and the source terminal of the transistor M6, and the source terminal of the transistor M4 is connected to a power supply GND.

5. The circuit of claim 1, wherein, The gate terminals of the transistors M1, M2, M3 and M4 are connected to each other to form an input terminal, the drain terminal of the transistor M5 is connected to the power supply GND, and the drain terminal of the transistor M6 is connected to the power supply VDD. The first shaping circuit comprises two inverters formed by transistors M7, M8 and transistors M9, M10. The gate terminals of the transistors M7 and M8 are connected to each other to receive an output signal of the Schmitt trigger, the source terminal of the transistor M7 is connected to the power supply VDD, the source terminal of the transistor M8 is connected to the power supply GND, and the drain terminal of the transistor M7 and the drain terminal of the transistor M8 are connected to form an output terminal. The gate terminals of the transistors M9 and M10 are connected to each other to receive the output signal of the Schmitt trigger, the source terminal of the transistor M9 is connected to the power supply VDD, the source terminal of the transistor M10 is connected to the power supply GND, and the drain terminal of the transistor M9 and the drain terminal of the transistor M10 are connected to form an output terminal. The second shaping circuit comprises an inverter formed by a transistor M18 and a transistor M19. The source terminal of the transistor M18 is connected to the power supply VDD, the source terminal of the transistor M19 is connected to the power supply GND, the drain terminal of the transistor M18 and the drain terminal of the transistor M19 are connected to form an output terminal, and the gate terminals of the transistors M18 and M19 are connected to each other to receive an output signal of the first comparator.

6. The circuit of claim 1, wherein, The pulse width compensation circuit comprises a transistor M20, a transistor M21, a transistor M22, a transistor M23 and a resistor R1, the gate terminals of the transistor M20 and the transistor M21 are connected, and receive the output signal of the second shaping circuit, the source terminal of the transistor M20 is connected to the power supply VDD, the source terminal of the transistor M21 is connected to the power supply GND, the drain terminal of the transistor M20 is connected to the first terminal of the resistor R1 and constitutes an output terminal, and the drain terminal of the transistor M21 is connected to the second terminal of the resistor R1; the gate terminals of the transistor M22 and the transistor M23 are connected, and receive the output signal of the previous stage inverter, the source terminal of the transistor M22 is connected to the power supply VDD, the source terminal of the transistor M23 is connected to the power supply GND, and the drain terminal of the transistor M22 and the drain terminal of the transistor M23 are connected to constitute an output terminal.

7. The circuit of claim 1, wherein, The buffer circuit comprises a transistor M24 and a transistor M25 to constitute an inverter, the gate terminals of the transistor M24 and the transistor M25 are connected, and receive the output signal of the pulse width compensation circuit, the source terminal of the transistor M24 is connected to the power supply VDD, the source terminal of the transistor M25 is connected to the power supply GND, and the drain terminal of the transistor M24 and the drain terminal of the transistor M25 are connected to constitute an output terminal.

8. The circuit of claim 2, wherein, The charge pump circuit comprises a switch NMOS1 and a charging capacitor C1, the gate terminal of the switch NMOS1 receives the output signal of the first shaping circuit, the drain terminal is connected to the positive input terminal of the first comparator and the upper end of the charging capacitor C1, and the first charging current generated by the bandgap reference flows in, and the source terminal of the switch NMOS1 is connected to the lower end of the charging capacitor C1 and is connected to the power supply GND.

9. The circuit of claim 2, wherein, The bandgap reference circuit generates the first charging current for the charge pump circuit, generates the first bias voltage for the first comparator, and generates the first reference voltage connected to the negative input terminal of the first comparator.

10. The circuit of claim 2, wherein, The first comparator comprises a transistor M11, a transistor M12, a transistor M13, a transistor M14, a transistor M15, a transistor M16 and a transistor M17, the source terminals of the transistor M12 and the transistor M13 are connected to the drain terminal of the transistor M11, the drain terminal of the transistor M12 and the drain terminal and the gate terminal of the transistor M14 and the gate terminal of the transistor M15 are connected, the drain terminal of the transistor M13 and the drain terminal of the transistor M15 are connected to constitute the first stage output of the first comparator and are input to the gate terminal of the transistor M17; the drain terminal of the transistor M16 and the drain terminal of the transistor M17 are connected to constitute the second stage output of the first comparator; the source terminals of the transistor M11 and the transistor M16 are connected to the power supply VDD, and the gate terminals are connected to the first bias voltage, the source terminals of the transistor M14, the transistor M15 and the transistor M17 are connected to the power supply GND; The gate terminal of the transistor M12 is the negative input terminal of the first comparator, and the gate terminal of the transistor M13 is the positive input terminal of the first comparator.

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