Low-power-consumption power supply state monitoring terminal

Abstract

The utility model relates to the technical field of electric power monitoring and power supply management, and discloses a low-power-consumption power supply state monitoring terminal which comprises a shell and an internal circuit board, and the circuit board is powered by a system main power supply and comprises an integrated sampling circuit, a reference voltage generating circuit, a three-level gradient power supply control framework and a power-off control circuit. In the three-stage gradient power supply control architecture, only a micro-power-consumption first comparator works continuously, other modules are powered on as required, sampling signals are validated through double comparators and an RC delay decision circuit, instantaneous interference of mains supply is filtered out, a power-off control circuit realizes active power-off and forced power-off dual modes, and the power-off control circuit is switched on and off. According to the utility model, through a three-stage gradient power supply control architecture, the standby power consumption of the system can be reduced to a microampere level, the requirement of high anti-interference performance is satisfied, and the system is suitable for long-term monitoring scenes without fixed power supply.

Description

Technical Field

[0001] This utility model relates to the field of power monitoring and power management technology, and in particular to a low-power power status monitoring terminal. Background Technology

[0002] In the field of power monitoring, reducing standby power consumption is a core technological challenge in achieving long-term battery life for battery-powered terminals. Currently, typical hardware solutions for low-power monitoring fall into three main categories, but each has inherent drawbacks that are difficult to overcome:

[0003] Single-stage comparator direct wake-up architecture: This type of solution typically uses a low-power comparator to monitor the input voltage. When the voltage exceeds a threshold, it directly wakes up the microcontroller from sleep mode. Its drawback is that the circuit structure is too simple; the comparator will generate a wake-up signal for any transient interference pulse exceeding the threshold (such as mains noise or electrical switch surges), leading to frequent false wake-ups of the microcontroller. The energy consumed by each false wake-up will significantly shorten battery life over long-term operation. Poor interference immunity and the goal of "low power consumption" are fundamentally contradictory in this architecture.

[0004] Continuously operating enhanced monitoring architecture: To improve reliability, some solutions add continuous hardware filtering or signal conditioning circuits to the monitoring loop, or use multi-stage comparators for redundant judgment. The drawback is that these auxiliary circuits used to improve noise immunity require continuous power supply. Even when the microcontroller is in sleep mode, the system still has a high baseline quiescent current (often tens to hundreds of microamps). While this improves noise immunity, it significantly sacrifices standby power consumption, failing to meet the application requirements for ultra-long battery life (such as several years).

[0005] Processor-centric software monitoring architecture: Some solutions rely on the microcontroller's own analog-to-digital converter and software algorithms to determine power status through periodic sampling and digital filtering. The drawback is that even if the microcontroller can enter deep sleep mode, its core and necessary voltage regulation circuits still need to maintain a microamp-level operating current; and modules used for wake-up determination (such as built-in ADCs or comparators) need to be kept powered or periodically activated. Therefore, the overall standby power consumption of the system is difficult to reduce to below 10 microamps, limiting its ultra-long battery life in scenarios without a fixed power supply. Furthermore, the complexity of the software program and the potential risk of system crashes also affect the final reliability and determinism of the system.

[0006] Furthermore, none of the above solutions designed a delay-based decision mechanism at the hardware circuit level, that is, to determine whether the power supply state remains effective by comparing the instantaneous signal with the delayed signal. This design flaw makes it impossible to fundamentally immunize against transient interference.

[0007] In summary, the problems with existing technologies can be attributed to the fact that, at the hardware architecture level, "ultra-low quiescent current" (below microamperes), "high interference immunity" (preventing false wake-ups), and "high reliability" (system self-sufficiency) cannot be achieved simultaneously. Designers often need to make trade-offs.

[0008] Therefore, there is an urgent need for a low-power power state monitoring terminal with a brand-new hardware circuit architecture that can systematically integrate rather than compromise the core characteristics of "ultra-low quiescent current" and "high anti-interference", and solve the above-mentioned technical problems through hardware structure design. Utility Model Content

[0009] The purpose of this utility model is to overcome the shortcomings of the prior art and provide a low-power power status monitoring terminal, including a housing and a circuit board disposed within the housing. The circuits on the circuit board are powered by a system main power supply and integrate:

[0010] The system includes a sampling circuit, whose input terminal is used to connect to an external monitored line; a reference voltage generation circuit, whose power supply terminal is connected to the main power supply of the system, used to generate a first reference voltage and a second reference voltage; a first comparator, whose power supply terminal is connected to the main power supply of the system, whose non-inverting input terminal is connected to the first output terminal of the sampling circuit, and whose inverting input terminal is connected to the first reference voltage; and a first switch, whose input terminal is connected to the main power supply of the system, and whose control terminal is connected to the output terminal of the first comparator. The second and third comparators share a common power supply terminal connected to the output terminal of the first switch, and are powered by the first switch. The non-inverting input terminal of the second comparator is connected to the second output terminal of the sampling circuit, and its inverting input terminal is connected to the second reference voltage. The non-inverting input terminal of the third comparator is connected to the third output terminal of the sampling circuit through a delay decision circuit, and its inverting input terminal is connected to the second reference voltage. The logic control circuit has its power supply terminal connected to the output terminal of the first switch, and its input terminals are respectively connected to the output terminals of the second and third comparators. The second switch has its input terminal connected to the system's main power supply, and its control terminal connected to the output terminal of the logic control circuit. The processor has its power supply terminal connected to the output terminal of the second switch, and its signal sampling terminal connected to the sampling signal output terminal of the sampling circuit.

[0011] Preferably, the delay decision circuit is an RC delay decision circuit.

[0012] Preferably, the RC delay decision circuit includes a first delay resistor and a first delay capacitor. The first delay resistor is connected in series between the third output terminal of the sampling circuit and the non-inverting input terminal of the third comparator, and the first delay capacitor is connected between the non-inverting input terminal of the third comparator and ground.

[0013] Preferably, the sampling circuit is a resistor divider sampling circuit.

[0014] Preferably, the resistor-divider sampling circuit further includes a first voltage divider resistor and a second voltage divider resistor connected in series, and the connection point between the first voltage divider resistor and the second voltage divider resistor constitutes a secondary voltage divider node.

[0015] Preferably, the sampling circuit further includes a current-limiting resistor; one end of the current-limiting resistor is connected to the secondary voltage divider node, and the other end serves as the first output terminal of the sampling circuit.

[0016] The second and third output terminals of the sampling circuit, as well as the signal sampling terminal of the processor, are all directly connected to the secondary voltage divider node.

[0017] Preferably, the first comparator is a low-power voltage detector with a quiescent current of less than 2 microamps.

[0018] Preferably, the logic control circuit is a NAND gate chip.

[0019] Preferably, a second delay resistor is connected in series between the output terminal of the logic control circuit and the control terminal of the second switch; the control terminal of the second switch is also connected to ground through a second delay capacitor.

[0020] Preferably, it further includes a power-down control circuit, which includes an OR gate logic circuit and a monostable trigger circuit. The first input terminal of the OR gate logic circuit is connected to the output terminal of the logic control circuit, and its second input terminal is connected to the output terminal of the monostable trigger circuit. Its output terminal is connected to the control terminal of the second switch through the second delay resistor. The trigger input terminal of the monostable trigger circuit is connected to the power-down control pin of the processor.

[0021] The beneficial effects of this invention are as follows: Three-level gradient power supply: The first comparator acts as a resident low-power "sentinel," triggering each subsequent circuit before it can be activated. This design physically cuts off the power consumption path of non-working modules, reducing system standby power consumption to the microampere level, enabling continuous monitoring of the core circuit and achieving true long-term standby. A hardware delay decision path is introduced. A set decision time window is constructed through the delay decision circuit, requiring the sampled signal to simultaneously meet the dual conditions of "instantaneous value exceeding the threshold" and "after the time window delay, its value remains above the threshold" to be considered a valid event. This purely hardware "AND" logic decision mechanism physically immunizes against brief interference pulses (such as surges and noise), responding only to continuous and effective power state changes. This ensures extremely high anti-interference reliability while maintaining millisecond-level fast response, fundamentally eliminating false wake-ups. A power-down control circuit is designed, allowing the processor to cut off its own power supply through hardware circuits connected to its GPIO pins, or to be forcibly powered down by the system when the monitored signal is abnormal. This has resulted in a hardware circuit structure that supports autonomous power management and forced shutdown in case of abnormalities, ensuring that the processor is in an ideal state of "zero static current" when there are no tasks, thus completely eliminating the basic power consumption in the traditional low-power standby mode. Attached Figure Description

[0022] Figure 1 This is a system architecture block diagram of a low-power power state monitoring terminal;

[0023] Figure 2 A circuit diagram of one specific embodiment of the power supply section of this utility model system;

[0024] Figure 3 This is a circuit structure diagram of one specific embodiment of the sampling circuit of this utility model;

[0025] Figure 4 This is a circuit structure diagram of a specific embodiment of the reference voltage generation circuit of this utility model;

[0026] Figure 5 This is a circuit structure diagram of a specific embodiment of the delay decision circuit and logic control circuit of this utility model;

[0027] Figure 6 This is a circuit structure diagram of one specific embodiment of the power control circuit of this utility model.

[0028] Figure Labels

[0029] F1 is a fuse, U0 is a low-dropout linear regulator, C1 is a rectifier filter capacitor, C2 and C3 are output filter capacitors, R1, R2, R3, R4, and R5 are high-voltage divider resistors, BR1 is a bridge rectifier, R6 is the first voltage divider resistor, R7 is the second voltage divider resistor, Rin is a current-limiting resistor, Uref is a low-power reference voltage source, Ra, Rb, Rc, and Rd are voltage divider resistors, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, and C14 are filter capacitors, U1 is the first comparator, Rp1 and Rp2 are pull-up resistors, Q1 is the first switch, Q2 is the second switch, Rg1 and Rg2 are gate resistors, U2 is the second comparator, U3 is the third comparator, Re1 is the first delay resistor, Re2 is the second delay resistor, Ce1 Ce1 is the first delay capacitor, Ce2 is the second delay capacitor, U4 is a NAND gate chip, RA and RB are input current limiting resistors, U5 is the processor, U7 is a 555 timer, Rt is the timing resistor, Ct is the timing capacitor, U8 is an OR gate chip, A is the connection node between the first delay resistor Re1 and the first delay capacitor Ce1, Vp is the primary voltage divider node, Vmain is the main voltage divider node, Vsub is the secondary voltage divider node, V1 is the first output terminal of the sampling circuit, V2 is the second output terminal of the sampling circuit, V3 is the third output terminal of the sampling circuit, Vb is the reference voltage output terminal, Vref1 is the first reference voltage, Vref2 is the second reference voltage, VCC (SYS) is the system main power supply, VCC (Arb) is the first-level controlled power supply node, and VCC (MCU) is the second-level controlled power supply node. Detailed Implementation

[0030] The technical solution of this utility model is described in further detail below with reference to the accompanying drawings, but the scope of protection of this utility model is not limited to the following description.

[0031] The features and performance of this utility model will be further described in detail below with reference to the embodiments. The chip models, resistor and capacitor parameters and power supply specifications mentioned therein are preferred embodiments, which are intended to clearly illustrate the technical solutions and are not intended to limit this utility model. The use of functionally equivalent devices or parameter adjustments all fall within the protection scope of this utility model.

[0032] Example 1

[0033] like Figure 1 As shown, a low-power power status monitoring terminal includes a housing and a circuit board disposed within the housing. The circuitry on the circuit board is powered by a system mains power supply and integrates:

[0034] The sampling circuit has its input terminal used to connect to the external monitored line.

[0035] The reference voltage generation circuit is connected to the main power supply VCC (SYS) of the system and is used to generate the first reference voltage Vref1 and the second reference voltage Vref2.

[0036] The first comparator U1 has its power supply terminal connected to the system main power supply VCC(SYS), its non-inverting input terminal connected to the first output terminal of the sampling circuit, and its inverting input terminal connected to the first reference voltage Vref1.

[0037] The first switch Q1 has its input terminal connected to the system's main power supply VCC(SYS) and its control terminal connected to the output terminal of the first comparator; the second comparator U2 and the third comparator U3 have their power supply terminals connected to the output terminal of the first switch Q1 and are powered by the first switch Q1.

[0038] The non-inverting input of the second comparator U2 is connected to the second output of the sampling circuit, and its inverting input is connected to the second reference voltage Vref2; the non-inverting input of the third comparator U3 is connected to the third output of the sampling circuit through a delay decision circuit, and its inverting input is connected to the second reference voltage Vref2.

[0039] The logic control circuit has its power supply terminal connected to the output terminal of the first switch Q1, and its input terminals connected to the output terminals of the second comparator U2 and the third comparator U3, respectively.

[0040] The second switch Q2 has its input terminal connected to the system's main power supply VCC(SYS) and its control terminal connected to the output terminal of the logic control circuit.

[0041] The processor U5 has its power supply terminal connected to the output terminal of the second switch Q2 and is powered by the second switch Q2. Its signal sampling terminal is connected to the sampling signal output terminal of the sampling circuit.

[0042] Based on the above connections, this utility model terminal implements a clear three-level gradient power supply control architecture to match its three-level wake-up logic, thereby achieving ultra-low standby power consumption and high anti-interference capability.

[0043] Level 1: Power Input and Direct Supply Circuit. The system's main power supply VCC(SYS) directly provides continuous power to the reference voltage generation circuit and the first comparator U1, enabling them to continuously operate as the system's "sentinel." Simultaneously, the system's main power supply VCC(SYS) also supplies power to the inputs of the first switch Q1 and the second switch Q2, establishing a path for subsequent controlled power supply. All direct supply circuits in this level utilize low-power devices to ensure extremely low system standby current.

[0044] Level 2: First-level controlled power supply path. When the first comparator U1 detects a valid signal input (i.e., the sampled voltage is higher than the first reference voltage Vref1) and controls the first switch Q1 to turn on, the system main power supply VCC(SYS) establishes the first-level controlled power supply node VCC(Arb) at its output node via the first switch. The first-level controlled power supply node VCC(Arb) supplies power to the second comparator U2, the third comparator U3, and the logic control circuit, enabling them to start working and independently compare and logically judge the instantaneous value and the delayed value of the sampled voltage.

[0045] Level 3: Second-level controlled power supply path. When the logic control circuit confirms that the comparison results of the previous two levels are valid (i.e., both the instantaneous value and the delayed value are higher than the second reference voltage Vref2) and controls the second switch to turn on, the system main power supply VCC (SYS) establishes a second-level controlled power supply node VCC (MCU) at its output node via the second switch. The second-level controlled power supply node VCC (MCU) supplies power to the processor U5, waking it up from a completely power-off state and enabling it to execute monitoring tasks.

[0046] Example 2

[0047] Based on Embodiment 1, this embodiment provides a specific implementation of the system power supply, sampling circuit, reference voltage generation circuit, and first comparator U1.

[0048] System power supply:

[0049] like Figure 2 As shown, the terminal can use a 3.6V / 2400mAh lithium thionyl chloride battery as a primary energy source. This battery has an annual self-discharge rate of ≤1%, suitable for long standby times. The positive terminal of the battery is connected to the input (IN) of a low-dropout linear regulator (LDO) U0 via a 1A fuse F1. Fuse F1 prevents short circuits from burning out the battery. The negative terminal of the battery is connected to system ground (GND). Output filter capacitors C2 and C3 are connected in parallel to the output (OUT) of the LDO. Filter capacitor C2 can be a 100μF / 16V electrolytic capacitor, and filter capacitor C3 can be a 100nF ceramic capacitor (located near the output pin of the LDO U0) to suppress power ripple and ultimately provide a stable 3.3V DC voltage as the system's main power supply VCC (SYS). The circuit board has a unified ground plane (GND) and adopts a single-point grounding method: the negative terminal of the battery, the ground terminal (GND) of the low-dropout linear regulator U0, the ground terminal of the reference voltage circuit, and the ground terminal of the first comparator are all converged at the same grounding node to avoid high voltage interference with low voltage circuits.

[0050] Sampling circuit:

[0051] like Figure 3As shown, the sampling circuit is a resistor divider sampling circuit. Its core function is to linearly reduce the monitored signal of a higher voltage and convert it into a sampling voltage suitable for processing by the subsequent low-voltage circuit. In this embodiment, the circuit is specifically described using a typical scenario of monitoring 220VAC AC mains power. Its design withstand voltage is not less than 500V to meet the insulation safety requirements of high-voltage monitoring.

[0052] In this embodiment, the sampling circuit includes five identical high-voltage divider resistors (R1, R2, R3, R4, R5), specifically five thick-film chip resistors, each with a resistance of 2MΩ and a withstand voltage of 500V. These five resistors are connected in series to form a complete high-voltage divider branch. One end of this branch serves as the high-potential input terminal, and the other end serves as the low-potential input terminal or is connected to ground. In this AC mains monitoring example, one end of the high-voltage divider resistor R1 (high-potential input terminal) is connected to the live wire (L) of the mains input terminal; one end of the high-voltage divider resistor R5 (low-potential input terminal) is connected to the neutral wire (N) of the mains input terminal.

[0053] This embodiment takes monitoring 220VAC AC mains power as an example. The connection point between high-voltage divider resistors R2 and R3 is defined as the primary voltage divider node Vp. The signal from this node first passes through a rectifier circuit to convert the AC voltage into DC voltage for processing by the subsequent comparator. In this embodiment, a miniature bridge rectifier BR1 (e.g., a full-bridge rectifier composed of four 1N4007 diodes) is used, with its AC input terminal connected to the primary voltage divider node Vp. The positive terminal of the DC output of the bridge rectifier BR1 is connected to the positive terminal of the rectifier filter capacitor C1, which can be a 10μF / 250V electrolytic capacitor. The negative terminal of the rectifier filter capacitor C1 is connected to system ground (GND), and the positive terminal of the rectifier filter capacitor C1 forms the main voltage divider node Vmain. (For DC monitoring scenarios, the rectification stage can be omitted, and the primary voltage divider node Vp can be directly connected to the subsequent voltage divider circuit.)

[0054] Two secondary voltage divider resistors are connected in series between the main voltage divider node Vmain and system ground: a first voltage divider resistor R6 (2.2MΩ, optional) and a second voltage divider resistor R7 (20kΩ, optional). The connection point between the first voltage divider resistor R6 and the second voltage divider resistor R7 is the secondary voltage divider node Vsub. By selecting the resistance values ​​of each voltage divider resistor as described above, the voltage range of the secondary voltage divider node Vsub (e.g., 0-2.5V) can be made to perfectly match the reference voltage threshold set by the subsequent stage within the target voltage monitoring range (the first reference voltage is lower than the second reference voltage, such as Vref1=0.5V, Vref2=1.2V).

[0055] Three independent electrical connection paths are drawn from the secondary voltage divider node Vsub to form the three output terminals of the sampling circuit, as follows:

[0056] (1) The sampling circuit further includes a current-limiting resistor Rin (e.g., 100kΩ); the first end of the current-limiting resistor Rin is connected to the secondary voltage divider node Vsub, and its second end constitutes the first output terminal V1 of the sampling circuit and is connected to the non-inverting input terminal of the first comparator U1.

[0057] (2) Second output terminal V2: The connection path is directly led out from the secondary voltage divider node Vsub and used as the second output terminal V2 of the sampling circuit, which is connected to the non-inverting input terminal of the second comparator U2;

[0058] (3) Third output terminal V3: The connection path is directly led out from the secondary voltage divider node Vsub and used as the third output terminal V3 of the sampling circuit, which is connected to the input terminal of the delay decision circuit.

[0059] The secondary voltage divider node Vsub also serves as the sampling signal output terminal of the sampling circuit, connected to the signal sampling terminal of the processor.

[0060] Reference voltage circuit:

[0061] like Figure 4 As shown, the reference voltage generation circuit is directly and continuously powered by the system's main power supply VCC (SYS), ensuring the stability of the reference voltage (unaffected by the switching on and off of subsequent circuits). Its core is a low-power reference voltage source Uref, whose ground terminal (GND) is connected to system ground (GND). The input terminal (IN) of the low-power reference voltage source Uref is connected to the system's main power supply VCC (SYS). The output terminal (OUT) of the low-power reference voltage source Uref forms a 2.5V reference voltage output terminal Vb. A filter capacitor C4, specifically a 100nF ceramic capacitor, is connected in parallel between the reference voltage output terminal Vb and system ground (GND) to suppress voltage fluctuations.

[0062] Starting from the Vb terminal, connect a series voltage divider resistor Ra (16kΩ, optional) and a voltage divider resistor Rb (4kΩ, optional). Connect the other end of the voltage divider resistor Ra to Vb and the other end of the voltage divider resistor Rb to system ground (GND). Connect a filter capacitor C5 (100nF ceramic capacitor, optional) in parallel across the voltage divider resistor Rb. The two ends of the voltage divider resistor Rb serve as the output terminals of the first reference voltage Vref1 (e.g., 0.5V), which are connected to the inverting input terminal of the first comparator U1.

[0063] Simultaneously, a voltage divider resistor Rc (13kΩ, optional) and a voltage divider resistor Rd (12kΩ, optional) are connected in series from the Vb terminal. The other end of the voltage divider resistor Rc is connected to Vb, and the other end of the voltage divider resistor Rd is connected to system ground (GND). A filter capacitor C6, specifically a 100nF ceramic capacitor, is connected in parallel across the voltage divider resistor Rd. The two ends of the voltage divider resistor Rd serve as the output terminals of the second reference voltage Vref2 (e.g., 1.2V), which are connected to the inverting input terminals of the second comparator U2 and the third comparator U3.

[0064] First comparator U1:

[0065] like Figure 3 As shown, the first comparator U1 can be a low-power voltage detector chip with a quiescent current of 0.8μA. Its low-power characteristics, combined with a three-level gradient power supply control architecture, keep the system standby power consumption below 1μA (the actual power consumption is dominated by the 0.8μA of the first comparator U1), supporting continuous monitoring and allowing subsequent circuits to be powered on only when necessary. Its power supply pin (VCC) is connected to the system main power supply VCC (SYS), and its ground pin (GND) is connected to the system ground. A filter capacitor C7, specifically a 10nF ceramic capacitor, is connected in parallel between the power supply pin and ground to avoid power supply noise interference. Its detection pin (IN, as the non-inverting input) is connected to the first output terminal V1 of the sampling circuit through the current limiting resistor Rin (which can be 100kΩ). A filter capacitor C8, which can be a 1nF ceramic capacitor, is connected in parallel between the detection pin and ground to suppress high-frequency noise caused by mains power surges. Its output pin (OUT) has an open-drain structure and is connected to the system main power supply VCC (SYS) through a pull-up resistor Rp1, for example, 100kΩ; the output pin is also directly connected to the control terminal of the first switch Q1; when the first comparator U1 outputs a low level, it triggers the first switch Q1 to turn on, and when it outputs a high level, the first switch Q1 turns off.

[0066] Based on the above hardware connections, when the system enters standby mode, only the system main power supply VCC(SYS) continuously supplies power to the reference voltage generation circuit and the first comparator U1, while the other modules are in a power-off state, and the standby current is controlled in the microampere level. When an external monitored voltage is effectively connected, the sampling circuit generates a corresponding sampling voltage. Taking the monitoring of 220VAC mains power as an example, this voltage range is approximately 0-2.5V. The first comparator U1 continuously compares the current-limited sampling voltage with the first reference voltage Vref1 (e.g., 0.5V). If the sampling voltage is lower than Vref1, the first comparator U1 outputs a high level, the first switch Q1 remains off, the first-stage controlled power supply node VCC(Arb) has no output, and its subsequent modules remain in sleep mode. If the sampling voltage is higher than Vref1, the first comparator U1 outputs a low level, triggering the first switch Q1 to turn on. The system main power supply VCC(SYS) outputs the first-stage controlled power supply voltage through the first switch Q1, which powers the second comparator U2, the third comparator U3, and the logic control circuit. The system enters the "dual comparator anti-interference verification" stage, completing the process connection from the first-stage wake-up to the second-stage verification.

[0067] Example 3

[0068] Based on Embodiment 2, this embodiment provides a specific implementation of a delay decision circuit, a second comparator U2, a third comparator U3, a logic control circuit, a first switch Q1, a second switch Q2, and a processor U5.

[0069] Delay decision circuit:

[0070] To achieve interference-resistant delayed decision-making, this embodiment sets up a delayed signal path. Specifically, the sampled signal is processed by a delayed decision-making circuit. In this embodiment, an RC delayed decision-making circuit is preferably used to implement this delayed function, such as... Figure 5As shown, the delay decision circuit is an RC low-pass filter circuit used to delay the sampled signal to avoid misjudgment caused by transient mains interference. In this circuit, the first delay resistor Re1 can be a 100kΩ metal film resistor, and the first delay capacitor Ce1 can be a 1μF / 16V ceramic capacitor. The time constant τ(Re1×Ce1) of the RC delay decision circuit is designed to be approximately 100 milliseconds. This value is selected to effectively filter out transient interference pulses with a duration significantly shorter than this time constant (e.g., less than 20ms), while ensuring a reliable response to valid signal changes with a duration significantly longer than this time constant (e.g., greater than 100ms). Taking a 50Hz AC mains environment as an example, this design can effectively filter out interference within a single cycle (20ms) and confirm power outage events lasting hundreds of milliseconds, thus achieving an optimal balance between speed and interference immunity. One end of the first delay resistor Re1 is connected to the third output terminal V3 of the sampling circuit, and the other end is connected to one end of the first delay capacitor Ce1. The other end of the first delay capacitor Ce1 is connected to system ground (GND). The connection node between the first delay resistor Re1 and the first delay capacitor Ce1 is defined as node A. Node A is connected to the non-inverting input terminal of the third comparator U3.

[0071] First switch Q1, second switch Q2:

[0072] like Figure 5 As shown, both the first switch Q1 and the second switch Q2 are P-channel MOSFETs. The source of the first switch Q1 is connected to the system main power supply VCC(SYS), the drain output is defined as the first controlled power supply node VCC(Arb), and the gate is connected to the output of the first comparator U1. A gate resistor Rg1 (optional, 1MΩ) is connected in parallel between the gate and the source to ensure that the gate level is stable when the first switch Q1 is turned off. The source of the second switch Q2 is connected to the system main power supply VCC(SYS), the drain output is defined as the second controlled power supply node VCC(MCU), and the gate is connected to the output of the logic control circuit. A gate resistor Rg2 (optional, 1MΩ) is connected in parallel between the gate and the source to ensure that the gate level is stable when the second switch Q2 is turned off.

[0073] Second comparator U2, third comparator U3:

[0074] like Figure 5As shown, the second comparator U2 and the third comparator U3 are integrated into a dual-channel low-power comparator chip. A dual-channel low-power comparator chip with a single-channel quiescent current of less than 1μA can be selected. This selection ensures that even during the verification phase after the 'first-level wake-up', the increased current consumption of the system is extremely low, consistently adhering to the hierarchical, on-demand power supply management philosophy and avoiding the drawback of introducing excessively high quiescent current to improve anti-interference capabilities. The chip's power supply pin (VCC) is connected to the drain of the first switch Q1 (i.e., the first-level controlled power supply node VCC(Arb)); a filter capacitor C9, specifically a 10nF ceramic capacitor, is connected in parallel between the power supply pin and system ground (GND) to suppress power supply ripple; the chip's ground pin (GND) is connected to system ground. The non-inverting input of the first channel (U2) is connected to the second output V2 of the sampling circuit, and its inverting input is connected to the second reference voltage Vref2; the non-inverting input of the second channel (U3) is connected to node A, and its inverting input is connected to the second reference voltage Vref2.

[0075] Logic control circuit:

[0076] like Figure 5 As shown, the logic control circuit is a dual-input NAND gate chip U4. A valid wake-up signal is output only when both the instantaneous comparison result and the delayed comparison result are high (indicating the signal remains valid). This purely hardware-based dual-verification decision mechanism eliminates false triggering caused by a single signal transition from a circuit principle perspective, ensuring high reliability and eliminating the risk of software malfunction. The power supply pin (VCC) of the NAND gate chip U4 is connected to the first-level controlled power supply node VCC(Arb). A filter capacitor C10, specifically a 10nF ceramic capacitor, is connected in parallel between the power supply pin and system ground (GND). The ground pin (GND) is connected to system ground. Its first input terminal is connected to the output terminal of the second comparator U2 through an input current limiting resistor RA (10kΩ can be selected); its second input terminal is connected to the output terminal of the third comparator U3 through an input current limiting resistor RB (10kΩ can be selected); the input current limiting resistors RA and RB are used to limit the current flowing into the input terminal of the NAND gate chip to avoid damage to the device; its output terminal is connected to the system main power supply VCC (SYS) through a pull-up resistor Rp2 (1MΩ can be selected), and is also connected to the gate of the second switch Q2.

[0077] To ensure logic stability at power-on and prevent the logic control circuit from erroneously outputting a shutdown signal due to asynchronous output state establishment times between the second comparator U2 and the third comparator U3, a second delay resistor Re2 is connected in series between the output terminal of the NAND gate chip U4 and the gate of the second switch Q2. The gate of the second switch Q2 is also connected to system ground (GND) through a second delay capacitor Ce2. The second delay resistor Re2 and the second delay capacitor Ce2 constitute an RC debouncing circuit. Its function is that, during the initial power-on of the first-stage controlled power supply node VCC (Arb), even if the NAND gate chip U4 outputs a brief high-level pulse due to a race condition, the RC debouncing circuit will cause the gate voltage of the second switch Q2 to change slowly, thereby effectively filtering out this interference pulse and ensuring that the system ultimately responds with the logic decision result after U2 and U3 have stabilized. The resistance value of the second delay resistor Re2 is selected from the range of 10kΩ to 100kΩ, and the capacitance value of the second delay capacitor Ce2 is selected from the range of 0.01μF to 0.1μF. The time constant (τ=Re2×Ce2) of the RC circuit formed by the two is designed to be between 0.1 milliseconds and 10 milliseconds.

[0078] The second delay resistor Re2 can be a 51kΩ thick-film chip resistor, and the second delay capacitor Ce2 can be a 0.1μF ceramic capacitor with a rated voltage of 16V. At this time, the time constant is approximately 5 milliseconds, which can reliably filter out interference pulses with a duration of less than 1 millisecond. Simultaneously, the impact on normal system wake-up and power-down operations (whose setup or determination time is typically greater than 50 milliseconds) is negligible. Furthermore, the time constant of this RC debounce circuit should be significantly smaller than the hundreds of milliseconds delay used by the delay decision circuit to determine the mains power status, ensuring that the two delay functions are clear and do not interfere with each other.

[0079] Processor U5:

[0080] like Figure 5 As shown, the processor U5 is a low-power microcontroller. The power supply pin (VDD) of the processor U5 is connected to the second-stage controlled power supply node VCC (MCU). A filter capacitor C11 and a filter capacitor C12 are connected in parallel between this power supply pin and system ground (GND). Filter capacitor C11 can be a 100nF ceramic capacitor, and filter capacitor C12 can be a 10μF / 16V electrolytic capacitor, used to suppress power supply ripple. All its ground pins (GND) are connected to system ground. The analog-to-digital converter (ADC) pin (PA0) of the processor U5 is connected as a signal sampling terminal to the sampling signal output terminal of the sampling circuit, i.e., the secondary voltage divider node Vsub.

[0081] Based on the above hardware connection relationships, the hardware circuit operation process is as follows:

[0082] The voltage signal at the secondary voltage divider node Vsub of the sampling circuit is directly transmitted to the non-inverting input of the second comparator U2 for instantaneous comparison with the second reference voltage Vref2. On the other hand, the voltage signal charges the capacitor Ce1 through the delay resistor Re1, forming a delayed voltage signal at node A, which is then transmitted to the non-inverting input of the third comparator U3 for delayed comparison with the same second reference voltage Vref2.

[0083] The output levels of the second comparator U2 and the third comparator U3 are transmitted to the two input terminals of the logic control circuit (NAND gate chip U4) through the input current-limiting resistors RA and RB, respectively. According to the hardware logic of the NAND gate, the output terminal of the NAND gate chip U4 will only output a low level when the output terminals of U2 and U3 are both high.

[0084] The low-level signal at the output of the NAND gate chip U4 is transmitted to the gate of the second switch Q2 via the second delay resistor Re2, controlling the second switch Q2 to conduct, thereby establishing a voltage on the second-stage controlled power supply node VCC (MCU) to power the processor U5. If the outputs of U2 and U3 are not simultaneously high, the NAND gate chip U4 outputs a high level. This high-level signal increases the gate voltage of Q2 via the second delay resistor Re2, thereby keeping the second switch Q2 off.

[0085] Therefore, this invention creates a "time window" by introducing a hardware decision architecture that includes a delay decision circuit. System wake-up must simultaneously meet two conditions: "the instantaneous voltage exceeds the threshold" and "the voltage still exceeds the threshold after the delay." This mechanism physically ensures that only a continuously effective power signal can wake up the subsequent system, while any pulse interference shorter than this time window is invalidated, thus fundamentally resolving the contradiction between low power consumption and high noise immunity.

[0086] Furthermore, as a preferred embodiment, this embodiment may also include a power-down control circuit to provide a hardware structure that supports the active power-down of the processor and the forced power-down due to system abnormalities, thereby further reducing system power consumption.

[0087] like Figure 6 As shown, the power-down control circuit consists of a monostable trigger circuit and an OR gate logic circuit, specifically a dual-input OR gate chip U8. One general-purpose input / output pin (PA1) of the processor U5 is defined as the power-down trigger signal output terminal.

[0088] The monostable trigger circuit uses an 8-pin DIP-packaged 555 timer U7, configured for monostable operation. The pin connections of the 555 timer U7 are as follows:

[0089] Pin 1 (GND) is directly connected to system ground (GND).

[0090] Pin 2 (TRIG) is connected to the PA1 pin of processor U5 via a 10kΩ current-limiting resistor.

[0091] Pin 3 (OUT) is directly connected to the second input of the OR gate chip U8.

[0092] Pin 4 (RESET) and pin 8 (VCC) are connected to the system main power supply VCC (SYS).

[0093] Connect a 10nF ceramic filter capacitor C14 between pin 5 (CTL) and system ground (GND).

[0094] Pin 6 (THRES) and pin 7 (DISCH) are directly shorted to form a common timing node.

[0095] Connect a 10nF ceramic filter capacitor C13 between pin 8 (VCC) and system ground (GND).

[0096] The external timer connections are as follows: One end of the timing resistor Rt (a 100kΩ metal film resistor can be selected) is connected to the system main power supply VCC (SYS), and the other end is connected to the common shorting node between pins 6 and 7; the positive terminal of the timing capacitor Ct (a 10μF / 16V electrolytic capacitor can be selected) is connected to this common shorting node, and the negative terminal is connected to system ground (GND). The timing resistor Rt and the timing capacitor Ct form a monostable timing core, with a timing duration T = 1.1 × Rt × Ct ≈ 1.1 seconds.

[0097] OR gate chip U8: Its power supply terminal is connected to the system main power supply VCC (SYS), and its ground terminal is connected to system ground (GND). Its first input terminal is connected to the output terminal of the logic control circuit (AND gate chip U4). Its second input terminal is connected to the output terminal of the 555 timer U7. Its output terminal is connected to the gate of the second switch Q2 through the RC debounce circuit, serving as the sole control node for the second switch Q2. Specifically, a second delay resistor Re2 is connected in series between the output terminal of the OR gate chip U8 and the gate of the second switch Q2, and the gate of the second switch Q2 is also connected to system ground (GND) through the second delay capacitor Ce2. The parameter selection and connection method of the RC debounce circuit are the same as described above, and its time constant (0.1 ms to 10 ms) is also designed to filter out any brief interference pulses that may appear on the control path, ensuring the stability of the control of the second switch Q2.

[0098] Based on the above hardware connection relationships, the hardware operation process of the power-down control circuit is as follows:

[0099] If a low-level pulse signal appears on the PA1 pin of processor U5, this pulse signal is transmitted to the trigger input of 555 timer U7, causing the output of 555 timer U7 to generate a high-level pulse with a duration of T = 1.1 × Rt × Ct ≈ 1.1 seconds. This ensures sufficient and deterministic hardware delay to complete the critical operation and unconditionally cuts off its own power supply after completion. This high-level signal is transmitted to the RC debounce circuit via OR gate chip U8, causing the gate voltage of the second switch Q2 to rise, thereby turning off the second switch Q2 and cutting off its power supply to processor U5.

[0100] When the sampling voltage is lower than the second reference voltage Vref2, the output of the logic control circuit (AND gate chip U4) is high. This high-level signal is also transmitted to the RC debounce circuit via OR gate chip U8, causing the gate voltage of the second switch Q2 to rise, thereby turning off the second switch Q2.

[0101] When the sampling voltage remains higher than the second reference voltage Vref2, and the PA1 pin of processor U5 does not output a specific pulse signal, both NAND gate chip U4 and 555 timer U7 output a low level. At this time, OR gate chip U8 transmits a low-level signal to the RC debounce circuit, keeping the gate voltage of the second switch Q2 low, and keeping the second switch Q2 on, thereby maintaining the power supply to processor U5.

[0102] The above description is merely a preferred embodiment of this utility model. It should be understood that this utility model is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of this utility model should be protected within the scope of the appended claims.

Claims

1. A low-power power status monitoring terminal, comprising a housing and a circuit board disposed within the housing, characterized in that, The circuitry on the circuit board is powered by a main power supply system and integrates: The sampling circuit has its input terminal used to connect to the external monitored line. A reference voltage generation circuit, whose power supply terminal is connected to the main power supply of the system, is used to generate a first reference voltage and a second reference voltage. The first comparator (U1) has its power supply terminal connected to the main power supply of the system, its non-inverting input terminal connected to the first output terminal of the sampling circuit, and its inverting input terminal connected to the first reference voltage. The first switch (Q1) has its input terminal connected to the main power supply of the system and its control terminal connected to the output terminal of the first comparator; the second comparator (U2) and the third comparator (U3) have their power terminals connected to the output terminal of the first switch (Q1) and are powered by the first switch (Q1). The non-inverting input of the second comparator (U2) is connected to the second output of the sampling circuit, and its inverting input is connected to the second reference voltage; the non-inverting input of the third comparator (U3) is connected to the third output of the sampling circuit through a delay decision circuit, and its inverting input is connected to the second reference voltage. The logic control circuit has its power supply terminal connected to the output terminal of the first switch (Q1), and its input terminals connected to the output terminals of the second comparator (U2) and the third comparator (U3) respectively. The second switch (Q2) has its input terminal connected to the main power supply of the system and its control terminal connected to the output terminal of the logic control circuit. The processor (U5) has its power supply terminal connected to the output terminal of the second switch (Q2), and its signal sampling terminal connected to the sampling signal output terminal of the sampling circuit.

2. The low-power power status monitoring terminal according to claim 1, characterized in that, The delay decision circuit is an RC delay decision circuit.

3. A low-power power status monitoring terminal according to claim 2, characterized in that, The RC delay decision circuit includes a first delay resistor (Re1) and a first delay capacitor (Ce1). The first delay resistor (Re1) is connected in series between the third output terminal of the sampling circuit and the non-inverting input terminal of the third comparator (U3). The first delay capacitor (Ce1) is connected between the non-inverting input terminal of the third comparator (U3) and ground.

4. The low power consumption power state monitoring terminal according to claim 1, wherein The sampling circuit is a resistor-divider sampling circuit.

5. A low-power power status monitoring terminal according to claim 4, characterized in that, The resistor-divider sampling circuit also includes a first voltage divider resistor (R6) and a second voltage divider resistor (R7) connected in series, and the connection point between the first voltage divider resistor (R6) and the second voltage divider resistor (R7) constitutes a secondary voltage divider node.

6. A low-power power status monitoring terminal according to claim 5, characterized in that, The sampling circuit also includes a current-limiting resistor (Rin); one end of the current-limiting resistor (Rin) is connected to the secondary voltage divider node, and the other end serves as the first output terminal of the sampling circuit. The second and third output terminals of the sampling circuit, as well as the signal sampling terminal of the processor (U5), are all directly connected to the secondary voltage divider node.

7. A low-power power status monitoring terminal according to claim 1, characterized in that, The first comparator (U1) is a low-power voltage detector with a quiescent current of less than 2 microamps.

8. A low-power power status monitoring terminal according to claim 1, characterized in that, The logic control circuit is a NAND gate chip (U4).

9. A low-power power status monitoring terminal according to claim 8, characterized in that, A second delay resistor (Re2) is connected in series between the output terminal of the logic control circuit and the control terminal of the second switch (Q2); the control terminal of the second switch (Q2) is also connected to ground through a second delay capacitor (Ce2).

10. A low-power power status monitoring terminal according to claim 9, characterized in that, It also includes a power-down control circuit, which comprises an OR gate logic circuit and a monostable trigger circuit. The first input terminal of the OR gate logic circuit is connected to the output terminal of the logic control circuit, and its second input terminal is connected to the output terminal of the monostable trigger circuit. Its output terminal is connected to the control terminal of the second switch (Q2) through the second delay resistor (Re2). The trigger input terminal of the monostable trigger circuit is connected to the power-down control pin of the processor (U5).

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