Transistor and electronic device

Abstract

The present disclosure provides a transistor and an electronic device, adopts GaAsSb / InGaAs heterojunction material, can adjust the doping concentration of the P+ type GaAsSb layer, the In component in the InGaAs layer, and the side inclination angle of the InGaAs layer and the P+ type GaAsSb layer and other parameters, so that GaAsSb / InGaAs is more flexible in the adjustment of the energy band structure and the device structure, can effectively increase the tunneling probability of the carrier, enhance the gate control ability, so as to reduce the subthreshold swing of the tunneling field effect transistor and increase the on-current, therefore, the present disclosure can realize the significant improvement of the device performance of the GaAsSb / InGaAs tunneling field effect transistor without increasing the complexity of the device preparation.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a transistor and an electronic device. BACKGROUND

[0002] Under the background of the evolution of semiconductor devices to low power consumption and high efficiency, tunneling field effect transistor (TFET) becomes a key candidate device to break through the bottleneck of the switching characteristics of traditional metal oxide semiconductor field effect transistor (MOSFET) due to its unique working mechanism. Unlike traditional devices that rely on hot excitation of carriers, TFET realizes current regulation based on quantum tunneling effect, and its theoretical sub-threshold swing (S.S.) can break through the physical limit of 60 mV / dec of MOSFET devices, significantly reducing the device turn-on voltage and static power consumption, and showing great application potential in low-power scenarios such as Internet of Things and portable electronics. The actual performance of TFET is highly dependent on the band engineering design of the channel material, and GaAsSb / InGaAs heterojunction is an ideal choice due to its excellent material properties. GaAsSb and InGaAs have matching lattice structures and controllable band alignment characteristics, and the narrow bandgap characteristics of GaAsSb and the high electron mobility of InGaAs form a synergistic effect to improve device current.

[0003] To further optimize the performance of TFET devices, precise control of material parameters to realize flexible tailoring of band structure becomes a core technical path. However, most traditional heterojunction TFET devices improve device performance through a single means, lacking systematic optimization; some new device structures only have theoretical feasibility, and are difficult to prepare in practice, with high cost. SUMMARY

[0004] Embodiments of the present disclosure provide a transistor and an electronic device for increasing the tunneling probability of carriers and enhancing the gate control capability, thereby improving the performance of TFET devices.

[0005] The transistor and the electronic device provided by the embodiments of the present disclosure have the following specific solutions:

[0006] In one aspect, the present disclosure provides a transistor, comprising:

[0007] an InP substrate;

[0008] an N+ type InGaAs layer located on one side of the InP substrate;

[0009] an InGaAs layer and a drain spaced apart from each other on a side of the N+ type InGaAs layer away from the InP substrate, the drain covering an edge region of the N+ type InGaAs layer, and the InGaAs layer covering a middle region of the N+ type InGaAs layer;

[0010] a P+ type GaAsSb layer located on a side of the InGaAs layer away from the InP substrate;

[0011] a source electrode located on a side of the P+ type GaAsSb layer away from the InP substrate, the source electrode covering a middle region of the P+ type GaAsSb layer;

[0012] a dielectric layer covering a region between the source electrode and the drain electrode;

[0013] a gate electrode located on a side of the dielectric layer away from the InP substrate, the gate electrode being insulated from the source electrode and the drain electrode by the dielectric layer.

[0014] In some embodiments, in the transistor provided by the embodiments of the present disclosure, a surface of the N+ type InGaAs layer away from the InP substrate has a step structure, the step structure comprising: a step top surface, a step bottom surface located at a periphery of the step top surface, and a step inclined surface connecting the step top surface and the step bottom surface;

[0015] the InGaAs layer is located on the step top surface, and the drain electrode is located on the step bottom surface;

[0016] the dielectric layer comprises: a first sub-dielectric layer covering a top surface edge region of the P+ type GaAsSb layer, a second sub-dielectric layer covering a side surface of the P+ type GaAsSb layer, a side surface of the InGaAs layer, and the step inclined surface, and a third sub-dielectric layer covering part of the step bottom surface; the first sub-dielectric layer, the second sub-dielectric layer, and the third sub-dielectric layer are in an integrated structure;

[0017] the gate electrode covers part of the first sub-dielectric layer, covers the second sub-dielectric layer, and covers part of the third sub-dielectric layer.

[0018] In some embodiments, in the transistor provided by the embodiments of the present disclosure, a side surface of the InGaAs layer and the P+ type GaAsSb layer has an inclination angle of 65-80°.

[0019] In some embodiments, in the transistor provided by the embodiments of the present disclosure, a side surface of the InGaAs layer and the P+ type GaAsSb layer has an inclination angle of 70°.

[0020] In some embodiments, in the transistor provided by the embodiments of the present disclosure, the impurity concentration of the InGaAs layer is 1×10 15 cm -3 ~1×10 16 cm -3 , and the material chemical formula of the InGaAs layer is In xGa 1-x As, x = 0.49~0.61.

[0021] In some embodiments, in the transistor provided by the above-mentioned embodiments of the present disclosure, the impurity concentration of the InGaAs layer is 1x10 15 cm -3 , x = 0.59.

[0022] In some embodiments, in the transistor provided by the above-mentioned embodiments of the present disclosure, the material formula of the P+ type GaAsSb layer is GaAs 0.5 Sb 0.5 , the doping concentration of the P+ type GaAsSb layer is 1x10 19 cm -3 ~8x10 19 cm -3 .

[0023] In some embodiments, in the transistor provided by the above-mentioned embodiments of the present disclosure, the doping concentration of the P+ type GaAsSb layer is 2x10 19 cm -3 .

[0024] In some embodiments, in the transistor provided by the above-mentioned embodiments of the present disclosure, the material formula of the N+ type InGaAs layer is In 0.53 Ga 0.47 As, the doping concentration of the N+ type InGaAs layer is 1x10 19 cm -3 .

[0025] In another aspect, the present disclosure also provides an electronic device comprising the above-mentioned transistor provided by the embodiments of the present disclosure.

[0026] The beneficial effects of the present disclosure are as follows:

[0027] The transistor and electronic device provided by the embodiments of the present disclosure adopt GaAsSb / InGaAs heterojunction materials, which can make GaAsSb / InGaAs more flexible in the adjustment of energy band structure and device structure by adjusting the doping concentration of the P+ type GaAsSb layer, the In component in the InGaAs layer, and the side inclination angle of the InGaAs layer and the P+ type GaAsSb layer, effectively increase the tunneling probability of carriers, and enhance the gate control capability, so as to reduce the subthreshold swing of the tunneling field effect transistor and increase the on-current, thus the present disclosure can significantly improve the device performance of the GaAsSb / InGaAs tunneling field effect transistor without increasing the complexity of device preparation. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 A structure schematic diagram of a transistor provided by an embodiment of the present disclosure is shown in FIG. 1;

[0029] Figure 2 A simulation result of I-V characteristics of the transistor shown in FIG. 1 obtained by changing different In components of the InGaAs layer; Figure 1

[0030] Figure 3 A simulation result of device performance parameters of the transistor shown in FIG. 1 obtained by changing different In components of the InGaAs layer; Figure 1

[0031] Figure 4 A simulation result of I-V characteristics of the transistor shown in FIG. 1 obtained by changing the doping concentration of the P+ type GaAsSb layer; Figure 1

[0032] Figure 5 A simulation result of device performance parameters of the transistor shown in FIG. 1 obtained by changing the doping concentration of the P+ type GaAsSb layer; Figure 1

[0033] Figure 6 A simulation result of I-V characteristics of the transistor shown in FIG. 1 obtained by changing θ; Figure 1

[0034] Figure 7 A simulation result of device performance parameters of the transistor shown in FIG. 1 obtained by changing θ. Figure 1 DETAILED DESCRIPTION

[0035] ​​​​​​For the purposes of the present disclosure, the goals, technical solutions, and advantages of the embodiments will be more clearly understood from the following description of the embodiments of the present disclosure, taken in conjunction with the accompanying drawings. It should be noted that in the drawings, the thicknesses of layers, films, panels, regions, and the like are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an area illustrated or described as flat can typically have rough and / or nonlinear features. A sharp angle illustrated can typically be rounded. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region that is to be constructed and / or manufactured. Rather, the shapes are intended to illustrate the general location of the region and the relative proximity or distance between regions. Similarly, the same or similar reference numerals are used to represent the same or similar elements or components throughout the description of the figures. To keep the following description of embodiments of the present disclosure clear and concise, detailed descriptions of known functions and constructions are omitted from the present disclosure.

[0036] Unless otherwise defined, technical terms or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first", "second", and similar terms do not denote any order, quantity, or importance, but are used to identify different components. The terms "include" or "comprise" and similar terms are intended to mean that the elements or objects listed after the terms encompass the elements or objects recited after the terms, and other elements or objects not listed after the terms. The terms "connected" or "coupled" and similar terms are not limited to physical or mechanical connections or couplings, but also include electrical connections or couplings, whether direct or indirect. The terms "inner", "outer", "upper", "lower", and the like are used only to describe relative positions, and when the absolute positions of the described objects are changed, the relative positions can also be changed accordingly.

[0037] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on the other element or layer, directly connected to the other element or layer, or an intervening element or layer can be present. When an element or layer is referred to as being "on one side of" another element or layer, it can be directly on the side of the other element or layer, directly connected to the other element or layer, or an intervening element or layer can be present. However, when an element or layer is referred to as being "directly on" another element or layer, or "directly connected to" another element or layer, there is no intervening element or layer present. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0038] The present disclosure provides a transistor, as shown in the following figure, which can be a tunneling field effect transistor, comprising: Figure 1

[0039] InP substrate 101;

[0040] N+ type InGaAs layer 102, located on one side of the InP substrate 101;

[0041] InGaAs layer 103 and drain 104, respectively, are arranged at a side of the N+ type InGaAs layer 102 away from the InP substrate 101, the drain 104 covers the edge region of the N+ type InGaAs layer 102, and the InGaAs layer 103 covers the middle region of the N+ type InGaAs layer 102; specifically, the InGaAs layer 103 is an unintentionally doped intrinsic InGaAs layer;

[0042] P+ type GaAsSb layer 105, located at a side of the InGaAs layer 103 away from the InP substrate 101;

[0043] Source 106, located at a side of the P+ type GaAsSb layer 105 away from the InP substrate 101, the source 106 covers the middle region of the P+ type GaAsSb layer 105;

[0044] Dielectric layer 107, covering the region between the source 106 and the drain 104;

[0045] Gate 108, located at a side of the dielectric layer 107 away from the InP substrate 101, the gate 108 is insulated from the source 106 and the drain 104 by the dielectric layer 107.

[0046] ​The transistor provided by the embodiments of the present disclosure adopts GaAsSb / InGaAs heterojunction materials, and can be more flexible in adjusting the energy band structure and device structure by adjusting the doping concentration of the P+ type GaAsSb layer, the In component in the InGaAs layer, and the side surface inclination angle of the InGaAs layer and the P+ type GaAsSb layer, can effectively increase the tunneling probability of the carriers, and enhance the gate control capability, so as to reduce the subthreshold swing of the tunneling field effect transistor and increase the on-current, and therefore the device performance of the GaAsSb / InGaAs tunneling field effect transistor can be significantly improved without increasing the complexity of device preparation.

[0047] In some embodiments, in the transistor provided by the embodiments of the present disclosure, as shown in Figure 1 , the materials of the source 106 and the drain 104 each include one or more of Ti, Al, Ta, Mo, Au, and Ni, and the material of the gate 108 can include one or more of Ti, Al, Ta, Mo, Au, and Ni. It can be understood that the materials of the source 106, the drain 104, and the gate 108 can be the same or different.

[0048] In some embodiments, in the transistor provided by the embodiments of the present disclosure, as shown in Figure 1 , the material of the dielectric layer 107 can be SiO2, Al2O3, or the like.

[0049] In some embodiments, in the transistor provided by the embodiments of the present disclosure, as shown in Figure 1 , the N+ type InGaAs layer 102 has a step structure away from the surface of the InP substrate 101, and the step structure includes: a step top surface A1, a step bottom surface A2 located at the periphery of the step top surface A1, and a step inclined surface A3 connecting the step top surface A1 and the step bottom surface A2.

[0050] The InGaAs layer 103 is located on the step top surface A1, and the drain 104 is located on the step bottom surface A2.

[0051] The dielectric layer 107 includes: a first sub-dielectric layer 1071 covering the top surface edge region of the P+ type GaAsSb layer 105, a second sub-dielectric layer 1072 covering the side surface of the P+ type GaAsSb layer 105, the side surface of the InGaAs layer 103, and the step inclined surface A3, and a third sub-dielectric layer 1073 covering part of the step bottom surface A2; the first sub-dielectric layer 1071, the second sub-dielectric layer 1072, and the third sub-dielectric layer 1073 are integrated structures.

[0052] The gate 108 covers part of the first sub-dielectric layer 1071, covers the second sub-dielectric layer 1072, and covers part of the third sub-dielectric layer 1073.

[0053] In some embodiments, in the above transistor provided by the embodiments of the present disclosure, as shown in Figure 1 , the N+ type InGaAs layer 102, the InGaAs layer 103 and the P+ type GaAsSb layer 105 can be epitaxially grown on the InP substrate 101, and then the N+ type InGaAs layer 102, the InGaAs layer 103 and the P+ type GaAsSb layer 105 are etched, so that the InGaAs layer 103 and the P+ type GaAsSb layer 105 form inclined side surfaces, and the N+ type InGaAs layer 102 forms the above-mentioned step structure away from the surface of the InP substrate 101. For example, the side surface inclination angle θ of the InGaAs layer 103 and the P+ type GaAsSb layer 105 is 65-80°, for example, θ is 65°, 70°, 80°, etc., and preferably θ is 70°. In this way, by adjusting the value of θ, the device structure can be more flexible, the gate control capability can be improved, and the tunneling probability of the carriers can be effectively increased.

[0054] In some embodiments, in the above transistor provided by the embodiments of the present disclosure, as shown in Figure 1 , the InGaAs layer 103 will inevitably be doped with a certain concentration of impurities during growth. For example, the impurity concentration of the InGaAs layer 103 can be 1×10 15 cm -3 ~1×10 16 cm -3 , and preferably the impurity concentration of the InGaAs layer 103 is 1×10 15 cm -3 ; the material chemical formula of the InGaAs layer 103 is In x Ga 1-x As, x=0.49-0.61, for example, x can be 0.49, 0.50, 0.51, 0.52, 0.53, 0.54, 0.55, 0.56, 0.57, 0.58, 0.59, 0.60 or 0.61. Preferably, x=0.59, that is, the material chemical formula of the InGaAs layer 103 is preferably In 0.59 Ga 0.41 As. In this way, by adjusting the value of the In component x, the band gap width and the band offset can be accurately controlled, the band alignment optimization on the tunneling path can be realized, the GaAsSb / InGaAs can be more flexible in the adjustment of the band structure, and the tunneling probability of the carriers can be effectively increased.

[0055] In some embodiments, in the above transistor provided by the embodiments of the present disclosure, as shown in Figure 1 , the material chemical formula of the P+ type GaAsSb layer 105 is GaAs 0.5 Sb0.5 The doping concentration of the P+ type GaAsSb layer 105 is 1×10⁻⁶. 19 cm -3 ~8×10 19 cm -3 For example, the doping concentration of a P+ type GaAsSb layer 105 can be 1×10⁻⁶. 19 cm -3 2×10 19 cm -3 3×10 19 cm -3 4×10 19 cm -3 5×10 19 cm -3 6×10 19 cm -3 7×10 19 cm -3 Or 8×10 19 cm -3 Preferably, the doping concentration of the P+ type GaAsSb layer 105 is 2 × 10⁻⁶. 19 cm -3 Thus GaAs 0.5 Sb 0.5 With optimal lattice matching with the InP substrate 101, the potential barrier can be optimized by adjusting the doping concentration of the P+ type GaAsSb layer 105, making the band structure adjustment of GaAsSb / InGaAs more flexible and effectively increasing the tunneling probability of charge carriers.

[0056] In some embodiments, in the transistors provided in this disclosure, such as Figure 1 As shown, the chemical formula of the N+ type InGaAs layer 102 is In 0.53 Ga 0.47 The doping concentration of the N+ type InGaAs layer 102 is 1×10⁻⁶. 19 cm -3 This way, the In 0.53 Ga 0.47 As and InP substrate 101 have optimal lattice matching.

[0057] Specifically, such as Figure 2 As shown, Figure 2 To Figure 1 The IV characteristics of the transistor shown were simulated, with the horizontal axis representing the gate voltage and the vertical axis representing the drain current; as shown... Figure 3 As shown, Figure 3 To Figure 1 The device performance parameters of the transistor shown are subthreshold swing (SS) and on-current (I). on Simulations were performed.Figure 2 and Figure 3 The simulation results were all obtained with the side tilt angle θ of the InGaAs layer 103 and the P+ type GaAsSb layer 105 fixed at 70°, and the doping concentration of the P+ type GaAsSb layer 105 fixed at 2×10⁻⁶. 19 cm -3 The source-drain voltage Vds = 0.5 V. Simulation results were obtained by changing the In composition of InGaAs layer 103. The material chemical formula of InGaAs layer 103 is In. x Ga 1-x The x value in As varies between 0.48 and 0.62. Simulation results show that the steepest drain current during device turn-on occurs at x = 0.59, while the largest drain current corresponds to a flatter curve. This allows for a lower subthreshold swing (SS) and a larger on-current (If). on ).

[0058] Specifically, such as Figure 4 As shown, Figure 4 To Figure 1 The IV characteristics of the transistor shown were simulated, with the horizontal axis representing the gate voltage and the vertical axis representing the drain current; as shown... Figure 5 As shown, Figure 5 To Figure 1 The device performance parameters of the transistor shown are subthreshold swing (SS) and on-current (I). on Simulations were performed. Figure 4 and Figure 5 The simulation results were obtained by fixing the side tilt angle θ of the InGaAs layer 103 and the P+ type GaAsSb layer 105 to 70°, the In composition x=0.59 in the InGaAs layer 103, and the source-drain voltage Vds=0.5V. The simulation results were obtained by changing the doping concentration of the P+ type GaAsSb layer 105. The doping concentration of the P+ type GaAsSb layer 105 was 1×10⁻⁶. 19 cm -3 ~2.5×10 19 cm -3 The simulation results show that the doping concentration in the P+ type GaAsSb layer 105 varies between 2 × 10⁻⁶ and 2 × 10⁻⁶. 19 cm -3 When the device is turned on, the drain current is steepest, and the drain current is largest when the curve is flat, which can achieve a lower subthreshold swing (SS) and a larger on-current (I). on ).

[0059] Specifically, such as Figure 6 As shown, Figure 6 To Figure 1The IV characteristics of the transistor shown were simulated, with the horizontal axis representing the gate voltage and the vertical axis representing the drain current; as shown... Figure 7 As shown, Figure 7 To Figure 1 The device performance parameters of the transistor shown are subthreshold swing (SS) and on-current (I). on Simulations were performed. Figure 6 and Figure 7 The simulation results are all based on a fixed doping concentration of 1×10⁵ for the P+ type GaAsSb layer 10⁵. 19 cm -3 In the InGaAs layer 103, the In component x=0.59 and the source-drain voltage Vds=0.5 V. Simulation results were obtained by changing the side tilt angle θ of the InGaAs layer 103 and the P+ type GaAsSb layer 105, for example, θ varies between 65° and 80°. The simulation results show that when θ is 70°, the drain current when the device is turned on is the steepest, and the drain current is the largest when the curve is flat. This allows for a lower subthreshold swing (SS) and a larger on-current (I). on ).

[0060] In summary, this disclosure employs GaAsSb / InGaAs heterojunction materials. By adjusting the doping concentration of the P+ type GaAsSb layer and the In composition in the InGaAs layer, the band structure of GaAsSb / InGaAs is more flexibly adjusted, effectively increasing the tunneling probability of charge carriers. Adjusting the side tilt angles of the InGaAs and P+ type GaAsSb layers enhances gate control capability. This multi-dimensional control strategy significantly increases the tunneling probability of charge carriers, improves tunneling current density, and reduces reverse leakage current. Therefore, this disclosure achieves a significant improvement in the device performance of GaAsSb / InGaAs TFETs without increasing the complexity of device fabrication.

[0061] To better understand the preparation method provided in the embodiments of this disclosure, this disclosure uses... Figure 1 Using the transistor shown as an example, the transistor fabrication process will be explained in detail.

[0062] In some embodiments, Figure 1 The fabrication process of the transistor shown may specifically include the following steps:

[0063] Epitaxial growth: Using growth techniques such as MBE, N+ type InGaAs layer, InGaAs layer and P+ type GaAsSb layer are sequentially grown on a semi-insulating InP substrate to form GaAsSb / InGaAs tunnel heterojunction.

[0064] Forming the step structure: define the step pattern on the surface of the epitaxial wafer by photolithography, and realize the step structure of the device by combining the wet or dry etching technology, that is, etching the P+ type GaAsSb layer, the InGaAs layer and the N+ type InGaAs layer, so as to form the step structure on the surface of the N+ type InGaAs layer.

[0065] Depositing the dielectric layer: deposit the dielectric layer material (such as SiO2, Al2O3, etc.) by ALD or PECVD process to form the dielectric layer.

[0066] Preparation of source / drain: photolithography defines the source / drain ohmic contact area, and dry or wet etching is used to remove the dielectric layer material in the contact area. Electron beam evaporation metal (such as Ti / Pt / Au) is used to form the source and drain with low resistance ohmic contact by rapid thermal annealing.

[0067] Preparation of gate: photolithography defines the gate metal area, and electron beam evaporation metal (such as Pt / Au) is used to form the gate.

[0068] Therefore, the transistor shown in the above steps is formed. Figure 1

[0069] Based on the same inventive concept, the electronic device provided by the embodiments of the present disclosure includes the transistor provided by the embodiments of the present disclosure. Since the principle of solving the problem of the electronic device is similar to that of the transistor, the implementation of the electronic device provided by the embodiments of the present disclosure can be referred to the implementation of the transistor provided by the embodiments of the present disclosure, and the repeated parts will not be described here.

[0070] In some embodiments, the electronic device provided by the embodiments of the present disclosure can include but is not limited to: radio frequency amplifier, frequency mixer, radar, satellite, power supply, automobile electronics, energy-saving lamp, household appliance, etc. Of course, the electronic device provided by the present disclosure can include not only the transistor, but also other structures, for example, when the electronic device is a radar, it also includes: transmitter, antenna, receiver and other structures; when the electronic device is a frequency mixer, it also includes: input port and output port and other structures.

[0071] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make further changes and modifications to these embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including all changes and modifications falling within the scope of the present disclosure.

[0072] Obviously, those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.​

Claims

1. A transistor, characterized by, Comprising: an InP substrate; an N+ type InGaAs layer on one side of the InP substrate; the N+ type InGaAs layer has a step structure on the surface away from the InP substrate, the step structure comprising: a step top surface, a step bottom surface on the periphery of the step top surface, and a step inclined surface connecting the step top surface and the step bottom surface; an InGaAs layer on the step top surface, and a drain on the step bottom surface, the drain covering the edge region of the step bottom surface; a P+ type GaAsSb layer on the side of the InGaAs layer away from the InP substrate; the side surface of the InGaAs layer and the P+ type GaAsSb layer has an inclination angle of 65-80°; a source on the side of the P+ type GaAsSb layer away from the InP substrate, the source covering the middle region of the P+ type GaAsSb layer; a dielectric layer covering the region between the source and the drain; the dielectric layer comprising: a first sub-dielectric layer covering the edge region of the top surface of the P+ type GaAsSb layer, a second sub-dielectric layer covering the side surface of the P+ type GaAsSb layer, the side surface of the InGaAs layer, and the step inclined surface, and a third sub-dielectric layer covering part of the step bottom surface; the first sub-dielectric layer, the second sub-dielectric layer, and the third sub-dielectric layer are an integral structure; a gate on the side of the dielectric layer away from the InP substrate, the gate covering part of the first sub-dielectric layer, covering the second sub-dielectric layer, and covering part of the third sub-dielectric layer, so that the gate and the source, the drain are both insulated by the dielectric layer.

2. The transistor of claim 1, wherein The side surface of the InGaAs layer and the P+ type GaAsSb layer has an inclination angle of 70°.

3. The transistor of claim 1, wherein The impurity concentration of the InGaAs layer is 1×10 15 cm -3 ~1×10 16 cm -3 The material chemical formula of the InGaAs layer is In x Ga 1-x As, x=0.49~0.

61.

4. The transistor of claim 3, wherein, The impurity concentration of the InGaAs layer is 1 x 1016 15 cm -3 -3, x = 0.

59.

5. The transistor of claim 1, wherein, The material formula of the P+ type GaAsSb layer is GaAs 0.5 Sb 0.5 The doping concentration of the P+ type GaAsSb layer is 1×10 19 cm -3 ~8×10 19 cm -3 .

6. The transistor of claim 5, wherein, The P+ type GaAsSb layer has a doping concentration of 2 x 1018 19 cm -3 .

7. The transistor of claim 1, wherein The material formula of the N+ type InGaAs layer is In 0.53 Ga 0.47 As, and the doping concentration of the N+ type InGaAs layer is 1x10 19 cm -3 .

8. An electronic device, comprising: A transistor comprising any one of claims 1-7.

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