HTBC battery and production method thereof

Abstract

The invention discloses an HTBC cell and a production method thereof, and relates to the field of solar cells. The production method comprises the following steps: depositing a tunneling oxide layer and a doped polycrystalline silicon layer, carrying out first laser patterning, locally grooving a PSG layer, and etching the doped polycrystalline silicon layer below a grooving region; texturing is carried out; depositing aluminum oxide and silicon nitride; depositing intrinsic and P-type doped microcrystalline silicon layers; second laser patterning: forming a patterned mask on the P-type microcrystalline silicon layer, etching an unmasked area and forming a groove in the P-type hydrogenated microcrystalline silicon after the steps of gluing, soft baking, exposing and developing are sequentially performed through a photoetching process; tCO film deposition is carried out; third-time laser patterning is carried out, a front-layer pattern is aligned through the photoetching technology, and a groove is formed in the TCO film through etching; and electrode formation: preparing a metal electrode on the surface of the battery through screen printing. Through the superposition photoetching patterning technology, thermal damage of a laser technology route in the technological process can be avoided, the patterning precision is synchronously improved, and then the photoelectric conversion efficiency of the cell is improved.

Description

Technical Field

[0001] This invention relates to the field of solar cells, and more specifically to an HTBC cell and its manufacturing method. Background Technology

[0002] Back-contact (BC) crystalline silicon solar cells completely eliminate front-side shading losses by placing all electrodes on the back side, achieving a theoretical efficiency of over 29%. This is a core technological approach to breaking through the efficiency limits of crystalline silicon cells. Currently, high-efficiency BC cells (such as IBC, HBC, and POLO-IBC) generally employ passivated contact structures to suppress back-side recombination.

[0003] However, existing back-contact (BC) crystalline silicon solar cells have the following limitations: Passivation performance bottleneck: While heterojunction back-contact (HBC) cells based on hydrogenated amorphous silicon (a-Si:H) exhibit excellent passivation (i-Voc>740mV), the light absorption loss of the intrinsic amorphous silicon layer and the high resistance of the transparent conductive oxide (TCO) limit the current density. While back-contact structures based on tunneling oxide / polycrystalline silicon (TOPCon) possess high conductivity, the high parasitic absorption (>4mA / cm²) of the polycrystalline silicon layer in the infrared band and the high-temperature processing (>800℃) are incompatible with the amorphous silicon passivation layer. Manufacturing process complexity: Traditional IBC cells require multiple laser grooving steps to achieve alternating isolation of the P / N regions on the back side, resulting in cumbersome process steps. Furthermore, high-temperature phosphorus / boron diffusion easily induces silicon wafer warping. In HJT-IBC cells, the TCO sputtering process easily damages the thin amorphous silicon passivation layer, leading to increased interfacial recombination.

[0004] Meanwhile, during the manufacturing process, laser processing routes often have adverse effects on material damage and processing precision. Specifically, these include: microcracks on the silicon wafer surface. If the laser energy is too high, the pulse width too long, or the scanning speed too slow, localized overheating can cause thermal stress on the silicon wafer, leading to microcracks on the surface. This not only affects the mechanical strength of the battery but may also cause performance degradation during battery use. Excessive damage to the passivation layer. Improper laser energy control or excessive processing times can cause excessive damage to the passivation layer. The passivation layer is crucial for reducing recombination losses on the battery surface and improving open-circuit voltage. Excessive damage to the passivation layer leads to a deterioration in the passivation effect and a reduction in the battery's photoelectric conversion efficiency. Pattern size deviations. Misalignment of the laser equipment's optical path system, wear of the focusing lens, or incorrect laser parameter settings can all cause the size and shape of the emitter pattern, slots, or contact holes to not meet design requirements. This affects the battery's electrical performance and reliability, potentially leading to poor contact or short circuits between electrodes. Inaccurate positioning. Insufficient accuracy of the equipment's positioning system or displacement of the battery cell during processing can cause deviations in the laser-patterned position. For BC batteries, electrode arrangement needs to be carried out with micron-level precision, and the pattern alignment accuracy is required to be less than 5μm. Once a positional deviation occurs, the electrodes are very likely to short-circuit or have poor contact, which directly leads to a significant reduction in battery efficiency and makes it difficult to guarantee the yield.

[0005] There are also issues related to impurities and contamination. Surface residue remains; vaporized substances generated during laser processing may re-condense on the battery surface, or impurities from the processing environment may adhere to the battery, forming surface residue. These residues affect the battery's appearance and performance, and may also introduce other problems in subsequent processes, such as affecting contact quality during metallization. Internal impurities can also be introduced; contamination of the optical components of the laser processing equipment or impurities in the processing gas can cause impurities to enter the battery. These impurities will reduce battery performance, affecting its lifespan and reliability.

[0006] Therefore, the key challenge for the industrialization of back contact batteries is to reduce optical loss, simplify the manufacturing process and achieve low-temperature process compatibility while ensuring the passivation quality of the back side, and at the same time reduce patterning damage and improve patterning accuracy. Summary of the Invention

[0007] (a) Technical problems to be solved To address the shortcomings of existing technologies, this invention provides an HTBC battery and its manufacturing method, solving at least one technical problem mentioned in the background art.

[0008] (II) Technical Solution The technical solution adopted by this invention provides a method for producing HTBC batteries, the preparation method comprising: Step S100: Deposition of tunneling oxide layer and doped polysilicon layer. A tunneling oxide layer and a doped polysilicon layer are sequentially deposited on the back side of an N-type silicon wafer, and a PSG mask is prepared. Step S200: First laser patterning, local trenching of the PSG layer, etching of the polysilicon layer below the trenched area using KOH alkaline solution and additives containing isopropanol; Step S300: Texturing. After the first laser patterning, the front and side surfaces of the N-type silicon wafer are etched and polished. After etching and polishing, an alkaline solution is used to texture the etched areas on the front and back surfaces of the N-type silicon wafer. Step S400: Alumina and silicon nitride deposition. An AlOx film is deposited on the front side of an N-type silicon wafer by ALD, followed by SiNx antireflection film deposition by PECVD. Step S500: Deposition of intrinsic and P-type doped microcrystalline silicon layers. After the deposition of alumina and silicon nitride, the N-type silicon wafer is cleaned. Intrinsic microcrystalline silicon layer and P-type hydrogenated microcrystalline silicon are deposited sequentially on the surface of the polycrystalline silicon layer on the back side of the cleaned N-type silicon wafer. Step S600, second laser patterning, through photolithography, after successively going through the steps of coating, soft baking, exposure and development, a patterned mask is formed on the P-type microcrystalline silicon layer, the unmasked area is etched, and trenches are formed in the P-type hydrogenated microcrystalline silicon. Step S700, TCO film deposition, depositing a TCO film on the back side of the silicon wafer; Step S800, third laser patterning, aligning with the previous layer pattern through photolithography, and etching trenches on the TCO film; Step S900, electrode formation, a metal electrode is prepared on the battery surface by screen printing.

[0009] Preferably, in step S100, the tunneling oxide layer and the doped polycrystalline silicon layer are deposited, the tunneling oxide layer is silicon oxynitride superimposed on aluminum oxide; The doped polysilicon layer is an N-poly layer, employing a double-layer phosphorus doping structure: the bottom layer is lightly doped polysilicon, and the top layer is heavily doped. Doped polycrystalline silicon, with an oxide layer separating the two layers; A 20–40 nm PSG layer was simultaneously generated on the surface of the N-poly layer and then annealed at 800–900 °C.

[0010] Preferably, the first laser patterning in step S200 specifically involves using a 532 nm femtosecond laser to locally groove the PSG layer, with a groove width of 400-700 μm.

[0011] Preferably, step S300 texturing specifically involves: etching and polishing the front and side surfaces of the N-type silicon wafer specifically involves: polishing the front and side surfaces of the N-type silicon wafer using a mixture of HF / HNO3 / H2SO4. Etching and polishing are performed by texturing the front and back etched areas of N-type silicon wafers using a 2-5% KOH solution at 70-80℃. The concentration ratio of HF, HNO3, and H2SO4 in the HF / HNO3 / H2SO4 mixture is 1-3:4-8:1.

[0012] Preferably, step S400, which involves the deposition of alumina and silicon nitride, specifically comprises: An AlOx film with a thickness of 6-12 nm is generated on the front side of an N-type silicon wafer by using an ALD method, which involves reacting trimethylaluminum with water at a concentration ratio of 1-3:1-3 and controlling the temperature at 240-280℃. A SiNx antireflective film with a thickness of 60-75 nm is deposited on the front side of an N-type silicon wafer using PECVD at a temperature of 400-600℃, a pressure of 100-500Pa, and a SiH4:NH3 ratio of 1:3~6.

[0013] Preferably, in step S500, the sequential deposition of an intrinsic microcrystalline silicon layer and a doped microcrystalline silicon layer on the surface of the doped polycrystalline silicon layer on the back side of the cleaned N-type silicon wafer specifically involves: Using a CVD machine, at 200-220℃ and 3000-5000 mtor pressure, SiH4, H2 and B2H6 gases are introduced to deposit an intrinsic microcrystalline silicon layer with a thickness of 4-8 nm and a P-type hydrogenated microcrystalline silicon layer with a thickness of 18-22 nm on the back side of the silicon wafer.

[0014] Preferably, the second laser patterning in step S600 specifically involves: Liquid photoresist is uniformly coated on the surface of an N-type silicon wafer to form a micron / sub-meter level thin film; Baking the N-type silicon wafer removes excess solvent from the photoresist; A latent image of a photomask pattern is formed on a photoresist layer by focusing through an optical system; The N-type silicon wafer is immersed in or sprayed with a developing solution to dissolve and remove the photoresist in the unexposed areas, forming a photoresist pattern on the surface of the N-type silicon wafer that corresponds to the mask. After photoresist development, the N-type silicon wafer is placed in a chain machine, and a mixture of HF, HNO3, and H2SO4 is used as a cleaning solution to etch the back of the N-type silicon wafer, creating a 60-80μm wide trench in the unexposed P-type hydrogenated microcrystalline silicon on the N-poly.

[0015] Preferably, the TCO film deposition in step S700 specifically involves: using a PVD machine at 180-220°C and 0.60-0.75Pa pressure, bombarding a tin-doped indium oxide target with high-energy particles to deposit a TCO film with a thickness of 70-90nm on the back side of an N-type silicon wafer.

[0016] Preferably, the third laser patterning in step S800 specifically involves: using photolithography to align the existing pattern on the N-type silicon wafer with the pattern on the mask, placing the N-type silicon wafer in a chain machine, and using a mixture of HNO3 and HF as a cleaning solution to create a trench with a width of 40-60 μm on the TCO film.

[0017] On the other hand, the present invention also provides an HTBC battery, prepared by any of the above methods, comprising: N-type crystalline silicon substrate; The hybrid passivation layer of the N-type crystalline silicon substrate includes, from the inside out, a tunneling oxide layer and an N-type doped polycrystalline silicon layer. Multifunctional composite layer, including intrinsic microcrystalline silicon layer and P-type microcrystalline silicon layer; Alumina superimposed on silicon nitride as a dielectric protective layer on the front side of an N-type crystalline silicon substrate; The TCO film layer on the back side of the N-type crystalline silicon substrate, and the metal contact gate line penetrating the TCO film layer.

[0018] (III) Beneficial Effects This invention provides an HTBC battery and its manufacturing method, which has the following advantages compared with the prior art: By using a hybrid passivation layer consisting of a tunneling oxide layer and a doped polycrystalline silicon layer, and an intrinsic hydrogenated microcrystalline silicon layer and a p-type microcrystalline silicon layer, the strong field-effect passivation of the tunneling oxide / polycrystalline silicon and the advanced chemical passivation capability of the hydrogenated microcrystalline silicon are combined to achieve extremely low recombination current density and extremely high open-circuit voltage. Both structures aim to achieve efficient selective carrier transport (electrons or holes), reduce contact recombination losses, and by using superimposed photolithography patterning technology, thermal damage during the laser technology process can be avoided, and the patterning accuracy can be improved simultaneously, thereby enhancing the photoelectric conversion efficiency of the battery. Attached Figure Description

[0019] The present invention will be further described below with reference to the accompanying drawings and embodiments: Figure 1 This is a structural diagram of an HTBC battery. Figure 2 This is a production flow chart for HTBC batteries. Specific implementation methods To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention are described clearly and completely. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. like Figure 1 and Figure 2 As shown, the purpose of this invention is to provide an HTBC battery structure and its manufacturing method to solve the problems of difficulty in simultaneously achieving passivation performance and optical / electrical losses, incompatibility between high-temperature processes and low-temperature technology routes, and complex manufacturing processes in existing back-contact batteries. Specifically, a method for manufacturing an HTBC battery is provided, the method comprising: Step S100: Deposition of tunneling oxide layer and doped polysilicon layer. A tunneling oxide layer and a doped polysilicon layer are sequentially deposited on the back side of the N-type silicon wafer, and a PSG mask is prepared. Specifically, before depositing the tunneling oxide layer and the doped polysilicon layer, the N-type silicon wafer needs to be cleaned and polished on both sides to remove the loss layer and surface impurities caused during the cutting process, forming a flat surface to prepare for subsequent thin film deposition. In practice, the N-type silicon wafer needs to be alkaline polished on both sides.

[0020] The tunneling oxide layer is composed of silicon oxynitride superimposed with aluminum oxide. Specifically, a tubular aluminum oxide machine is used to deposit SiONx+Al2O3 on the back side of an N-type silicon wafer. SiONx+Al2O3 can significantly reduce the interface defect density (one order of magnitude lower than SiO2), improve H passivation, effectively block phosphorus diffusion, and enhance open-circuit voltage and long-wavelength response. The thickness of silicon oxynitride is 1-10 nm, and the thickness of aluminum oxide is 1-6 nm. The doped polycrystalline silicon layer is an N-poly layer with a double-layer phosphorus doping structure: the bottom layer is lightly doped polycrystalline silicon, the top layer is heavily doped polycrystalline silicon, and the middle layer is isolated by an oxide layer. A 20–40 nm PSG layer is simultaneously generated on the surface of the N-poly layer and annealed at 800–900℃. The specific method is as follows: the above-mentioned N-type silicon wafer is placed in a PECVD plasma chemical vapor deposition furnace, and silane, phosphine, and hydrogen are excited by radio frequency, and the temperature is controlled at 400–600℃ to generate P-doped polycrystalline silicon for 20–40 minutes, forming an N-poly layer with a thickness of 160–200 μm. The N-poly layer adopts a stacked structure, with a thin oxide layer added in the middle of the poly layer as a barrier layer, and the original single poly-Si phosphorus doping is distributed in a double layer, with the bottom poly-Si lightly doped and the top poly-Si heavily doped; at the same time, a PSG layer with a thickness of 20-40nm is formed on the surface, and then annealed in a furnace tube at 800-900℃ for 20-30min, in which the oxide layer thickness is 1-3nm.

[0021] Step S200 involves the first laser patterning, where a localized trench is created in the PSG layer. A polycrystalline silicon layer below the trenched area is etched using a KOH alkaline solution and an additive containing isopropanol. Specifically, in this embodiment, the first laser patterning uses a 532 nm femtosecond laser with a power of 80 W, a pulse energy of 100 μJ, and a laser scanning speed of 40 m / s to create a localized trench in the PSG layer. The trench width is 400-700 μm, preferably 550 μm. Then, using a KOH alkaline solution and an additive whose main component is isopropanol, the reaction time is controlled at high temperature to etch the polycrystalline silicon below the trenched area. The un-lased PSG area is protected by a mask to prevent reaction with the alkaline solution. In the specific implementation, the KOH to isopropanol volume ratio is 19-20:1, the temperature is controlled at 60-80°C, and the etching time is 8-12 min, etching the polycrystalline silicon layer below the trenched area.

[0022] Step S300: Texturing. After the first laser patterning, the front and sides of the N-type silicon wafer are etched and polished. After etching and polishing, an alkaline solution is used to texturize the etched areas on the front and back of the N-type silicon wafer. Specifically, before texturing, the N-type silicon wafer needs to be acid etched. That is, the N-type silicon wafer after the above treatment is placed in a chain machine, and a mixture of HF / HNO3 / H2SO4 is used as the polishing liquid to polish the front and sides of the N-type silicon wafer. After etching and polishing, a 2-5% KOH solution is used to texturize the etched areas on the front and back of the N-type silicon wafer at 70-80℃. Specifically, in the embodiment process, the concentration ratio of HF, HNO3, and H2SO4 in the above-mentioned HF / HNO3 / H2SO4 mixture is 1-3:4-8:1; The above-mentioned alkaline solution is used to texturize the front and back etched areas of the N-type silicon wafer, forming a micron-scale textured surface structure with a specific morphology on the silicon wafer surface, which significantly reduces the reflectivity of the silicon surface to sunlight, thereby increasing light absorption.

[0023] Step S400, alumina and silicon nitride deposition: An AlOx film is deposited on the front side of an N-type silicon wafer via ALD, followed by SiNx antireflection film deposition via PECVD; in specific implementation, the alumina and silicon nitride deposition is as follows: An AlOx film with a thickness of 6-12 nm is generated on the front side of an N-type silicon wafer by using an ALD method, which involves reacting trimethylaluminum with water at a concentration ratio of 1-3:1-3 and controlling the temperature at 240-280℃. A SiNx antireflective film with a thickness of 60-75 nm is deposited on the front side of an N-type silicon wafer using PECVD at a temperature of 400-600℃, a pressure of 100-500Pa, and a SiH4:NH3 ratio of 1:3~6.

[0024] The passivation layer formed by the deposition of alumina and silicon nitride can passivate the front side and reduce carrier recombination on the front side.

[0025] Step S500: Deposition of intrinsic and P-type doped microcrystalline silicon layers. After the deposition of alumina and silicon nitride, the N-type silicon wafer is cleaned. Intrinsic microcrystalline silicon layer and P-type hydrogenated microcrystalline silicon are deposited sequentially on the surface of the polycrystalline silicon layer on the back side of the cleaned N-type silicon wafer. Specifically, an intrinsic microcrystalline silicon and p-type hydrogenated microcrystalline silicon are deposited on the back side of a silicon wafer using a CVD (CVD) system. A microcrystalline silicon thin film is then formed on the silicon wafer surface using VHF-PECVD technology. Compared to traditional microcrystalline silicon thin films, microcrystalline silicon exhibits superior conductivity and light transmittance, a more significant fill factor advantage, relatively lower current, higher open-circuit voltage, and superior photoelectric conversion efficiency.

[0026] The specific deposition process is as follows: An intrinsic microcrystalline silicon layer and a doped microcrystalline silicon layer are sequentially deposited on the surface of the doped polycrystalline silicon layer on the back side of the cleaned N-type silicon wafer. Specifically: Using a CVD machine, at 200-220℃ and 3000-5000 mtor pressure, SiH4, H2 and B2H6 gases are introduced to deposit an intrinsic microcrystalline silicon layer with a thickness of 4-8 nm and a P-type hydrogenated microcrystalline silicon layer with a thickness of 18-22 nm on the back side of the silicon wafer.

[0027] Step S600, the second laser patterning, involves a photolithography process followed by coating, soft baking, exposure, and development steps to form a patterned mask on the P-type microcrystalline silicon layer. The unmasked areas are then etched to form trenches in the P-type hydrogenated microcrystalline silicon. Specifically, the second laser patterning process includes: Liquid photoresist is uniformly coated on the surface of an N-type silicon wafer to form a micron / sub-meter level thin film; Baking the N-type silicon wafer removes excess solvent from the photoresist; A latent image of a photomask pattern is formed on a photoresist layer by focusing through an optical system; The N-type silicon wafer is immersed in or sprayed with a developing solution to dissolve and remove the photoresist in the unexposed areas, forming a photoresist pattern on the surface of the N-type silicon wafer that corresponds to the mask. After photoresist development, the N-type silicon wafer is placed in a chain machine, and a mixture of HF, HNO3, and H2SO4 is used as a cleaning solution to etch the back of the N-type silicon wafer, creating a 60-80μm wide trench in the unexposed P-type hydrogenated microcrystalline silicon on the N-poly.

[0028] Specifically, liquid photoresist is uniformly coated onto the entire surface of the N-type silicon wafer, forming a very thin (micron- or even submicron-scale) and uniformly thick film. After coating, a soft bake is performed, baking the silicon wafer at a lower temperature to remove most of the solvent from the photoresist, enhancing the adhesion between the photoresist film and the N-type silicon wafer, and making the film more stable. A photomask is then illuminated using a light source of a specific wavelength (through a complex optical system). The light passes through the photomask and onto the photoresist. The transparent areas on the photomask allow light to pass through, causing the photoresist to undergo a photochemical reaction and cure. The opaque areas block the light, preventing the photoresist from undergoing a photochemical reaction and thus curing. The N-type silicon wafer is then immersed in or sprayed with a developing solution to dissolve the uncured photoresist in the unexposed areas. The N-type silicon wafer is then placed in a chain etching machine, and a mixture of HF, HNO3, and H2SO4 is used as a cleaning solution to etch the back side of the N-type silicon wafer, creating a 60-80 μm wide trench in the unexposed P-type hydrogenated microcrystalline silicon on the N-poly.

[0029] Step S700, TCO film deposition: A TCO film is deposited on the back side of the silicon wafer. Specifically, using a PVD machine, a TCO thin film is deposited on the back side of the silicon wafer by bombarding a tin-doped indium oxide target with high-energy particles using DC magnetron sputtering. The TCO film has the characteristics of high conductivity and high optical transmittance, which can effectively reduce the surface resistance of the battery and reduce the loss during carrier transport. In the implementation process, a PVD machine is used at 180-220℃ and 0.60-0.75Pa pressure to deposit a TCO film with a thickness of 70-90nm on the back side of the silicon wafer by bombarding the tin-doped indium oxide target with high-energy particles.

[0030] Step S800, the third laser patterning, involves aligning the previous pattern with the photolithography process and etching a trench on the TCO film. In practice, a precise optical system and markings are used to accurately align the existing pattern on the silicon wafer (the previous photolithography layer) with the new pattern on the mask. The N-type silicon wafer is placed in a chain conveyor, and a mixture of HNO3 and HF is used as the cleaning solution to create a trench with a width of 40-60 μm on the TCO.

[0031] Step S900, electrode formation, a metal electrode is prepared on the battery surface by screen printing.

[0032] like Figure 1 As shown, this embodiment of the invention also provides an HTBC battery, prepared by any of the methods described above, comprising: N-type crystalline silicon substrate; The hybrid passivation layer of the N-type crystalline silicon substrate includes, from the inside out, a tunneling oxide layer and an N-type doped polycrystalline silicon layer. Multifunctional composite layer, including intrinsic microcrystalline silicon layer and P-type microcrystalline silicon layer; Alumina superimposed on silicon nitride as a dielectric protective layer on the front side of an N-type crystalline silicon substrate; The TCO film layer on the back side of the N-type crystalline silicon substrate, and the metal contact gate line penetrating the TCO film layer.

[0033] Among them, the tunneling oxide layer (SiONx+Al2O3, thickness 0.5-3nm) and the N-type doped polycrystalline silicon layer (N-poly, thickness 60-80nm). The multifunctional composite layer contains intrinsic microcrystalline silicon (µc-Si:H, 2-8nm) and p-type microcrystalline silicon (p-µc-Si:H, 6-20nm). In this multifunctional composite layer, the crystallinity of the microcrystalline silicon region is 30%-60%, and the thickness is 10-30nm. Selective carrier transport is achieved through bandgap modulation. The composite layer corresponding to the positive electrode of the battery contains boron-doped microcrystalline silicon, while the negative electrode corresponds to phosphorus-doped polycrystalline silicon. The two are isolated by photolithography.

[0034] At the battery structure level, the TBC battery provided in this embodiment of the invention simultaneously achieves high interface passivation quality, low parasitic optical loss and efficient carrier selective transport; through the synergistic design of material band and thickness, silicon oxynitride superimposed with aluminum oxide as a tunneling oxide layer, the contradiction between chemical passivation and field effect passivation that is difficult to balance in traditional single-layer passivation films is solved.

[0035] The tunneling oxide layer uses silicon oxynitride stacked with alumina instead of the original silicon oxide. SiONx's optical bandgap (5.3–8.9 eV) and refractive index can be tuned by adjusting the oxygen-nitrogen ratio, lowering the tunneling barrier. Nitrogen atoms introduce high-density positive-charge defect states, enhancing the field passivation effect. Al2O3 provides a high negative charge density (~10¹³ cm⁻²), which, together with the positive charge of SiONx, forms a bipolar field effect, suppressing carrier recombination. The SiONx / Al2O3 stack forms a built-in electric field through charge complementarity, repelling minority carriers away from the defect interface and reducing the recombination rate by more than 30%. The lower barrier of SiONx (~5.3 eV) allows carriers to tunnel efficiently in thicker layers (up to 5 nm), widening the process window. Due to gradient bandgap matching, the contact resistivity ρc of SiONx / Al2O3 can be reduced to below 0.3 mΩ·cm².

[0036] At the production method level, the present invention provides a production method for TBC batteries, which develops a low-temperature deposition and patterning process to avoid damage to sensitive passivation layers (such as amorphous silicon) by high-temperature steps, and achieves compatibility with low-temperature technologies such as HJT and thin silicon wafers. BC batteries require precisely interlaced P / N electrodes on the back side. Optimizing the integration and fabrication process of these back-side P / N electrodes is challenging because traditional laser processes struggle to achieve micron-level precision. Photolithography is a technique that transfers patterns from a photomask to a substrate using a photoresist (also known as a photoresist film) under illumination. The main process involves: first, ultraviolet light passes through the photomask and irradiates the substrate surface coated with a photoresist film, causing a chemical reaction in the exposed areas; then, development technology dissolves and removes the photoresist from the exposed or unexposed areas (the former is called positive photoresist, and the latter negative photoresist), allowing the pattern on the photomask to be copied onto the photoresist film; finally, etching technology transfers the pattern onto the substrate. Photolithography, through precise alignment, can achieve interdigitated structures with linewidths ≤10μm, controlling accuracy errors to ≤10μm, significantly reducing leakage risk, and improving short-wavelength light absorption by 5-10%. Photolithography technology can support highly complex interdigitated electrodes and avoid thermal damage from lasers during the process, thus reducing manufacturing costs and breakage rates.

[0037] In the patterning process of the back of BC batteries, photolithography has three significant advantages over laser methods, making it particularly suitable for large-scale mass production: Advantages in precision and yield: Photolithography technology achieves micron-level pattern control (linewidth 190μm±8μm) through mask exposure, with uniformity exceeding 98%, avoiding silicon-based melting damage (such as pyramid textured surface damage) and passivation layer degradation caused by high laser temperatures. Its wet film-forming process has no thermal damage and can achieve a mass production yield of 98%, while the laser route requires additional cleaning due to heat effects, resulting in an initial yield of only 93%-95%.

[0038] Cost and capacity advantages: Equipment investment is reduced by 60%, with the cost of a single GW lithography machine (chain lithography machine) being approximately 14 million yuan, only one-quarter of the cost of a laser solution (50-70 million yuan / GW). Capacity is increased by 2 times, with a full-wafer lithography capacity of 15,500 wafers / hour and a half-wafer 27,000 wafers / hour, compared to only 8,800 wafers / hour for a 200W picosecond laser. Material costs are optimized, reducing wet processing costs.

[0039] Process compatibility and reliability advantages: Adaptable to stacked technology, low-temperature process (≤200℃) compatible with HBC / perovskite stacks, protecting the passivation structure. Improved bifaciality, thinning of the poly-Si layer achieves a bifaciality of 70%+ (laser route ≤65%).

[0040] This invention enables the secondary and tertiary patterning of the back of an HTBC cell by using photolithography technology suitable for patterning photovoltaic cells, thereby manufacturing a high-efficiency, low-cost HTBC photovoltaic cell.

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail.

[0042] Example 1: N-type single-crystal silicon wafers with dimensions of 182.2*182.2mm and a thickness within the range of 130±8μm were selected. The N-type silicon wafers were cleaned and polished using a KOH solution with a concentration of 2-5% at 70-80℃, with the thinning amount controlled between 0.2-0.4g.

[0043] Deposition of tunneling oxide layer and doped polysilicon: A tunneling oxide layer of SiONx+Al2O3 and a doped polysilicon layer are sequentially deposited on the back side of an alkaline-polished N-type silicon wafer. The thickness of the silicon oxynitride is 1-10 nm, and the thickness of the alumina is 1-6 nm. A PSG mask is then prepared. First, a tubular alumina deposition machine is used to deposit SiONx+Al2O3 on the back side of the silicon wafer. SiONx+Al2O3 can significantly reduce the interface defect density (an order of magnitude lower than SiO2) and effectively block phosphorus diffusion, improving open-circuit voltage and long-wavelength response. Then, the silicon wafer is placed in a PECVD plasma chemical vapor deposition furnace. Silane, phosphine, and hydrogen are excited by radio frequency, and the temperature is controlled at 500℃ to generate phosphorus-doped polysilicon, forming an N-poly layer with a thickness of 160-200 μm. The process temperature is 400-600℃, and the process time is 20-40 min. The N-poly layer adopts a stacked structure, with a thin oxide layer added in the middle of the poly layer as a barrier layer. The oxide layer is 1-3 nm thick. The original single poly-Si phosphorus doping is distributed in a double layer, with the bottom poly-Si lightly doped and the top poly-Si heavily doped. At the same time, a PSG layer with a thickness of 20-40 nm is formed on the surface. Then, it is annealed in a furnace tube at 800-900℃ for 20-30 min.

[0044] First patterning: A green femtosecond laser with a wavelength of approximately 532 nm was used to locally groove the PSG layer. The laser power was 80 W, the pulse energy was 100 μJ, and the laser scanning speed was 40 m / s. The groove width was approximately 550 μm. An additive solution of KOH and isopropanol with a volume ratio of 19-20:1 was used, the temperature was controlled at 60-80℃, and the etching time was 8-12 min. A polycrystalline silicon layer was doped below the grooved area to achieve the effect of etching polycrystalline silicon below the grooved area. The un-lased areas were protected by a PSG mask to prevent reaction with the alkaline solution.

[0045] The treated N-type monocrystalline silicon wafers were placed in a chain mill, and a mixture of HF, HNO3, and H2SO4 with a concentration ratio of 1-3:4-8:1 was used as a polishing slurry to etch and polish the front and side surfaces of the N-type monocrystalline silicon wafers. A 2-5% KOH solution was then used to texturize the etched areas on the front and back surfaces of the N-type monocrystalline silicon wafers at a temperature of 70-80℃.

[0046] On the front side of an N-type monocrystalline silicon wafer, an AlOx film with a thickness of 6-12 nm is deposited using ALD (Al₂O₃ Deposition) with a concentration ratio of 1-3:1-3 (trimethylaluminum:water) and controlled temperature of 240-280℃. On the other hand, a SiNx antireflective film with a thickness of 60-75 nm is deposited using PECVD (Pure Chemical Vapor Deposition) at a temperature of 400-600℃, a pressure of 100-500 Pa, and a SiH₄:NH₃ ratio of 1:3 to 1:6.

[0047] The N-type monocrystalline silicon wafers after the above treatment are placed in a chain wet cleaning equipment, the temperature is set to 20-30℃, and HF with a concentration of 4%-10% is used as the cleaning solution to clean and remove the aluminum oxide (Al2O3) and silicon nitride (SiNx) coatings around the edges and back of the silicon wafers.

[0048] Using a CVD machine, at 200-220℃ and 3000-5000 mtor pressure, SiH4, H2 and B2H6 gases are introduced to deposit intrinsic amorphous silicon with a thickness of 4-8 nm and P-type hydrogenated amorphous silicon with a thickness of 18-22 nm on the back side of a silicon wafer.

[0049] Second patterning: Liquid photoresist is uniformly coated onto the entire silicon wafer surface, forming a very thin (micron or submicron) and uniformly thick film. After coating, a soft bake is performed, baking the silicon wafer at 80-120℃ for 60-150 seconds to remove most of the solvent from the photoresist. After soft baking, the solvent ratio is reduced from 10-20% to 6-8%, enhancing the adhesion between the photoresist film and the silicon wafer and making the film more stable. A light source with a wavelength matched to the photoresist is used to illuminate the photomask through an optical system. Light passes through the photomask and onto the photoresist. The transparent areas of the photomask allow light to pass through, causing the photoresist to undergo a photochemical reaction and cure. The opaque areas block light, preventing the photoresist from undergoing a photochemical reaction and thus preventing curing. The silicon wafer is immersed in or sprayed with a developer to dissolve the uncured photoresist in the unexposed areas. The N-type silicon wafer is placed in a chain machine, and a mixture of HF, HNO3, and H2SO4 is used as a cleaning solution to etch the back of the N-type monocrystalline silicon wafer, creating a 60-80 μm wide trench in the unexposed P-type hydrogenated microcrystalline silicon on the N-poly.

[0050] Using a PVD machine, at 180-220℃ and 0.60-0.75Pa pressure, a TCO film with a thickness of 70-90nm is deposited on the back of a silicon wafer by bombarding a tin-doped indium oxide target with high-energy particles.

[0051] The third patterning step involves using photolithography again to uniformly coat the entire silicon wafer surface with liquid photoresist, forming a very thin (micron or submicron) and uniformly thick film. After coating, a soft bake is performed, baking the silicon wafer at 80-120°C for 60-150 seconds to remove most of the solvent from the photoresist. After soft baking, the solvent content is reduced from 10-20% to 6-8%, enhancing the adhesion between the photoresist film and the silicon wafer and making the film more stable. A light source with a wavelength matched to the photoresist is used to illuminate the photomask through an optical system. Light passes through the photomask and onto the photoresist. The transparent areas of the photomask allow light to pass through, causing the photoresist to undergo a photochemical reaction and solidify, while the opaque areas block light, preventing the photoresist from undergoing a photochemical reaction and thus not solidifying. Using an optical system with position recognition, the existing pattern on the silicon wafer (the previous photolithography layer, i.e., the pattern from the second patterning) is precisely aligned with the newly exposed pattern on the photomask. An N-type silicon wafer is placed in a chain machine, and a mixture of HNO3 and HF is used as a cleaning solution to create a groove with a width of 40-60 μm on the TCO film.

[0052] Metal electrodes are formed on the surface of the battery structure created through the above steps using screen printing.

[0053] Comparative example: N-type monocrystalline silicon wafers with a thickness of 130±8 μm and a diameter of 182.2*182.2 mm were selected. The silicon wafers were cleaned and polished with KOH in an alkaline texturing bath at a temperature of 8-12℃. The thinning amount was controlled between 0.2-0.4g to remove the loss layer and surface impurities caused during the cutting process. The silicon wafers were then subjected to alkaline polishing treatment.

[0054] The silicon wafers were subjected to LPCVD equipment. SiH4 was introduced into the LPCVD furnace tube and heated to around 900°C under low pressure to induce a thermal decomposition reaction. A 1-2 nm thick SiOx tunneling oxide layer and an intrinsic polycrystalline silicon layer were deposited on the back side. Then, boron was doped using a high-temperature diffusion method while controlling the furnace tube temperature at 1100°C to form a 190-230 nm thick doped polycrystalline silicon layer. At the same time, a 40-60 nm thick BSG layer was generated on the surface.

[0055] A green femtosecond laser with a wavelength of approximately 532 nm was used to locally etch grooves in the BSG layer, with a power of 80 W, a pulse energy of 100 μJ, and a laser scanning speed of 40 m / s. Grooves of 400-700 μm width were also used to etch grooves in the PSG layer. By using a KOH alkaline solution and an additive primarily composed of isopropanol, the reaction time was precisely controlled under high temperature conditions to achieve the effect of etching the polysilicon beneath the grooved areas. The un-lased areas were protected by a BSG mask to prevent reaction with the alkaline solution.

[0056] The silicon wafer is then placed in a PECVD plasma chemical vapor deposition furnace. Silane, phosphine, and hydrogen are excited by radio frequency, and the temperature is controlled at 500°C. A tunneling oxide layer with a thickness of 1-2 nm and polycrystalline silicon doped with P are deposited on the back side to form an N-poly layer with a thickness of 240-280 nm. At the same time, a PSG layer with a thickness of 20-40 nm is formed on the surface. Subsequently, the back side is annealed at 800-900°C for 20-30 min.

[0057] Then, another 20W green laser was used to locally groove the P region and the adjacent GAP region. The laser power was 20W, the pulse energy was 200μJ, and the groove width was 600-1000μm.

[0058] Because the aforementioned process involves multiple layers of plating on the front side, including tunneling oxide, P-type polysilicon, BSG, N-type amorphous silicon, and PSG, which affect the texturing reaction and uniformity of the front-side surface, polishing is required. A mixture of HF, HNO3, and H2SO4 is used as the polishing solution in a chain-type machine to etch and polish the front side of the silicon wafer. The silicon wafer is then placed in a texturing tank, where alkaline etching is used to texturize the wafer. Simultaneously, the alkaline etching solution etches the polysilicon layer in the laser-grooved area, forming a PN-isolated GAP region. Finally, the silicon wafer passes through a chain-type acid bath to remove the PSG and BSG layers on the back side.

[0059] The front and back sides of the silicon wafer are sequentially treated with ALD (Al₂O₃) technology, which uses trimethylaluminum and water to react and controls the temperature at 260°C to generate AlO₂O₃ films with a thickness of 6-12 nm on the front and back sides of the silicon wafer.

[0060] SiNx passivation and antireflection films with a thickness of 60-75nm were deposited sequentially on the front and back sides of the silicon wafer using PECVD.

[0061] Metal electrodes are formed on the surface of the battery structure created through the above steps using screen printing.

[0062] The electrical performance and efficiency were tested according to the national standard GB / T 6495.1, and the results are compared below: By using a hybrid passivation layer consisting of a tunneling oxide layer and a doped polycrystalline silicon layer, and an intrinsic hydrogenated microcrystalline silicon layer and a p-type microcrystalline silicon layer, the strong field-effect passivation of the tunneling oxide / polycrystalline silicon and the advanced chemical passivation capability of the hydrogenated microcrystalline silicon are combined, potentially achieving extremely low recombination current density and extremely high open-circuit voltage. Both structures aim to achieve efficient selective carrier transport (electrons or holes), reduce contact recombination losses, and by using superimposed photolithography patterning technology, thermal damage during the laser technology process can be avoided, simultaneously improving patterning accuracy and thus enhancing the photoelectric conversion efficiency of the battery.

[0063] It should be noted that, in this document, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0064] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method of producing an HTBC battery, characterized by, The preparation method comprises: Step S100, deposition of a tunnel oxide layer and a doped polysilicon layer, sequentially depositing a tunnel oxide layer and a doped polysilicon layer on the back surface of an N-type silicon wafer, and preparing a PSG mask; Step S200, first laser patterning, locally slotting the PSG layer, etching the doped polysilicon layer under the slotted area through a KOH alkali solution and an additive of isopropyl alcohol; Step S300, texturing, after the first laser patterning, etching and polishing the front surface and the side surface of the N-type silicon wafer, after the etching and polishing, using an alkali solution to perform texturing on the etching area of the front surface and the back surface of the N-type silicon wafer; Step S400, deposition of aluminum oxide and silicon nitride, depositing an AlOx film layer on the front surface of the N-type silicon wafer through ALD, and then depositing a SiNx anti-reflection film through PECVD; Step S500, deposition of intrinsic and P-type doped microcrystalline silicon layers, after the deposition of aluminum oxide and silicon nitride, cleaning the N-type silicon wafer, and sequentially depositing an intrinsic microcrystalline silicon layer and a P-type hydrogenated microcrystalline silicon layer on the surface of the doped polysilicon layer on the back surface of the cleaned N-type silicon wafer; Step S600, second laser patterning, through a photoetch process, after sequentially going through the steps of gluing, soft baking, exposure and development, forming a patterned mask on the P-type microcrystalline silicon layer, etching the area not covered by the mask, and forming a trench in the P-type hydrogenated microcrystalline silicon; Step S700, deposition of a TCO film, depositing a TCO film on the back surface of the silicon wafer; Step S800, third laser patterning, through a photoetch process, aligning the pattern of the previous layer, etching a groove on the TCO film; Step S900, electrode formation, preparing a metal electrode on the surface of the cell through screen printing.

2. The method of producing an HTBC battery according to claim 1, wherein In the step S100 of deposition of a tunnel oxide layer and a doped polysilicon layer, the tunnel oxide layer is silicon oxynitride superimposed with aluminum oxide; The doped polysilicon layer is an N-poly layer, which adopts a double-layer phosphorus doping structure: the bottom layer is lightly doped polysilicon, and the surface layer is heavily doped polysilicon The two layers are separated by an oxide layer; A 20-40 nm PSG layer is synchronously generated on the surface of the N-poly layer, and annealing treatment is performed at 800-900℃.

3. The method of producing an HTBC battery according to claim 1, wherein The first laser patterning of step S200 specifically uses a 532 nm femtosecond laser to locally slot the PSG layer, and the slot width is 400-700 μm.

4. The method of producing a HTBC battery according to claim 1, wherein The texturing of step S300 specifically comprises: etching and polishing the front surface and the side surface of the N-type silicon wafer, which specifically comprises: using an HF / HNO3 / H2SO4 mixed solution to polish the front surface and the side surface of the N-type silicon wafer; Etching and polishing use a 2-5% KOH solution to etch the etching area of the front surface and the back surface of the N-type silicon wafer at 70-80℃; The concentration ratio of HF, HNO3 and H2SO4 in the HF / HNO3 / H2SO4 mixed solution is 1-3:4-8:

1.

5. The method of producing an HTBC battery according to claim 1, wherein The deposition of aluminum oxide and silicon nitride of step S400 specifically comprises: On the front surface of the N-type silicon wafer, an AlOx film layer with a thickness of 6-12 nm is generated by using ALD, reacting trimethylaluminum and water at a concentration ratio of 1-3:1-3, and controlling the temperature at 240-280℃; The SiNx anti-reflective film with a thickness of 60-75nm is deposited on the front surface of the N-type silicon wafer by PECVD method under the conditions of a temperature of 400-600℃, a pressure of 100-500Pa, and a ratio of SiH4:NH3 of 1:3-6.

6. The method of producing an HTBC battery according to claim 1, wherein The step S500 of sequentially depositing the intrinsic microcrystalline silicon layer and the doped microcrystalline silicon layer on the surface of the doped polysilicon layer on the back surface of the cleaned N-type silicon wafer is specifically as follows: The intrinsic microcrystalline silicon layer with a thickness of 4-8nm and the P-type hydrogenated microcrystalline silicon layer with a thickness of 18-22nm are deposited on the back surface of the silicon wafer by using a CVD machine under the conditions of a temperature of 200-220℃, a pressure of 3000-5000mtor, and the input of SiH4, H2 and B2H6 gases.

7. The method of producing an HTBC battery according to claim 1, wherein The second laser patterning of the step S600 is specifically as follows: The liquid photoresist is uniformly coated on the surface of the N-type silicon wafer to form a micron / sub-micron thin film; The N-type silicon wafer is baked to remove the excess solvent in the photoresist; The latent image of the mask pattern is formed on the photoresist layer by focusing through the optical system; The N-type silicon wafer is immersed or sprayed with the developing solution to dissolve and remove the photoresist in the unexposed area, and the photoresist pattern corresponding to the mask is formed on the surface of the N-type silicon wafer; After the photoresist is developed, the N-type silicon wafer is placed in a chain machine, and a mixed solution of HF, HNO3 and H2SO4 is used as the cleaning liquid to etch the back surface of the N-type silicon wafer and open a groove with a width of 60-80μm in the P-type hydrogenated microcrystalline silicon in the unexposed area on the N-poly.

8. The method of producing a HTBC battery according to claim 1, wherein, The TCO film deposition of the step S700 is specifically as follows: a PVD machine is used to deposit a TCO film with a thickness of 70-90nm on the back surface of the N-type silicon wafer by bombarding a tin-doped indium oxide target with high-energy particles under the conditions of a temperature of 180-220℃ and a pressure of 0.60-0.75Pa.

9. The method of producing a HTBC battery according to claim 1, wherein, The third laser patterning of the step S800 is specifically as follows: the existing pattern on the N-type silicon wafer is aligned with the pattern on the mask by using a photolithography process, the N-type silicon wafer is placed in a chain machine, and a mixed solution of HNO3 and HF is used as the cleaning liquid to open a groove with a width of 40-60μm in the TCO film.

10. An HTBC battery characterized by: Prepared by any of the methods of claims 1-9, comprising: an N-type crystalline silicon substrate; a mixed passivation layer of the N-type crystalline silicon substrate, sequentially comprising a tunneling oxide layer and an N-type doped polysilicon layer from inside to outside; a multifunctional composite layer comprising an intrinsic microcrystalline silicon layer and a P-type microcrystalline silicon layer; an alumina and silicon nitride superimposed dielectric protection layer on the front surface of the N-type crystalline silicon substrate; a TCO film layer on the back surface of the N-type crystalline silicon substrate, and a metal contact gate line penetrating through the TCO film layer.

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