TBC battery and preparation method thereof

Abstract

The invention provides a TBC battery and a preparation method thereof. The current density is remarkably improved by adjusting printing and laser patterns, reducing the area of a P region or / and an N region, increasing the area of a gap region, reducing the metal shielding area and improving the photon utilization rate; and compounding of a metal region is reduced, and Voc and passivation performance of the battery piece are improved. By polishing the gap region with the pyramid suede, the reflection of incident light in the silicon substrate can be increased, so that the Isc of the cell is improved, and meanwhile, as the initial gap region is protected by the mask layer and is not damaged by wet corrosion subsequently, the height difference between the gap region and the boron / phosphorus diffusion layer can be reduced, the transverse transmission of carriers in the silicon substrate is facilitated, and the FF is improved. According to the TBC battery prepared by the method, under the condition that the number of partitions on the back surface of the battery is not changed, the areas of the P region and the N region are reduced, so that the area of the gap region is increased, the metal shielding area is reduced, the photon utilization rate is improved, and the current density is obviously improved; and compounding of a metal region is reduced, and Voc and passivation performance of the battery piece are improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of back contact cells, and particularly relates to a TBC cell and a preparation method thereof. BACKGROUND

[0002] The continuous progress of the photovoltaic industry depends on the reduction of the degree of electricity cost and the improvement of efficiency. At present, a new generation of cell technology is rapidly emerging. Among many cell technologies, BC cells are widely recognized by the industry due to their significant efficiency advantage.

[0003] The back contact (BC) concept has been recognized as the main path of high-efficiency photovoltaic cell technology since it was proposed in 1975 through continuous evolution and improvement, because the front surface of the BC structure is not covered by grid lines, thereby increasing the light receiving area and improving the utilization rate of incident light. This has enabled BC to maintain a clear advantage in conversion efficiency over the past 50 years. In terms of process compatibility, the BC process is an open and highly scalable process that can be combined with TOPCon, HJT and other processes to further optimize the passivation structure, fully utilize the front surface and continuously improve the conversion efficiency of the cell. However, with the development of the photovoltaic industry, traditional IBC technology is facing competitive pressure and is constantly seeking innovation and breakthrough. The TBC cell combines the high short-circuit current of IBC and the excellent passivation contact characteristics of TOPCon, improves the conversion efficiency through a good passivation structure, and opens up a new path for the future development of BC cells.

[0004] However, the preparation process of the existing TBC cell is relatively complex. The diffusion of the P region and the N region is carried out in a diffusion furnace, which utilizes the principle of thermal diffusion to make impurity atoms diffuse into the crystalline silicon body under heat. However, the diffusion furnace heats the entire surface of the cell, and cannot heat specified local areas. Therefore, the doping concentration and diffusion depth of the entire plane of the cell are the same, but for the TBC cell, only specific areas need to be doped, and other areas do not need to be doped. Therefore, a complex process is required, which not only takes a long time and has a high cost, but also has serious production capacity defects, which is not conducive to the large-scale industrialization of the TBC cell. SUMMARY

[0005] The purpose of the present application is to provide a TBC cell to solve the above technical problems in the prior art.

[0006] The purpose of the present application is to provide a preparation method of a TBC cell. Based on the structure of the TBC cell, boron paste and phosphorus paste are used for printing instead of high-temperature boron diffusion and phosphorus diffusion to prepare the P region and the N region. At the same time, based on the printing of the boron paste and the phosphorus paste and the doping by laser, the printing and laser patterns are adjusted to reduce the area of the P region and / or the N region (so that the area of the P region / N region is only slightly larger than the area of the metal grid lines), increase the area of the gap region, and reduce the area of the metal shading.

[0007] To this end, the technical solutions provided by the present application are as follows:

[0008] A preparation method of a TBC battery, comprising the following steps:

[0009] Step 1) original silicon polishing: placing an N-type silicon wafer into a tank type alkali solution for polishing;

[0010] Step 2) forming a mask layer: printing a paste on the gap area on the back of the silicon wafer to form a mask layer;

[0011] Step 3) substrate deposition: first depositing an ultra-thin tunneling silicon oxide layer SiOx on the back of the silicon wafer, and then depositing a polysilicon Poly layer;

[0012] Step 4) PN doping source preparation: printing boron paste containing boron elements and phosphorus paste containing phosphorus elements on the polysilicon Poly layer to form a plurality of paste areas, and performing drying after printing is completed;

[0013] Step 5) laser doping: after printing and drying, laser doping is performed, laser doping is performed on the boron paste and phosphorus paste areas by adjusting the laser pattern and laser parameters, and laser opening film is performed on the non-printing area;

[0014] Step 6) cleaning and local etching: cleaning removes impurities and residues on the surfaces of the P area and the N area, and etching the poly layer between the P area and the N area to form a gap area;

[0015] Step 7) annealing treatment: annealing the cleaned substrate to activate the doped areas and realize local P+ and N+ doping;

[0016] Step 8) texturing: texturing the front surface of the silicon wafer to form a pyramid structure on the surface of the single crystal silicon wafer; and removing the mask layer of the gap area with HF;

[0017] Step 9) depositing a passivation layer;

[0018] Step 10) front and back films: depositing a first anti-reflective layer and a second anti-reflective layer on the front and back surfaces, respectively;

[0019] Step 11) screen printing and sintering: preparing a first electrode and a second electrode above the P+ area and the N+ area, respectively, and the first electrode and the second electrode penetrating the passivation layer and the anti-reflective film to connect with the P+ area and the N+ area, respectively.

[0020] Further, the mask layer in step 2) is SiOx, SiNx or SiO X N y .

[0021] Further, the thickness of the ultra-thin tunneling silicon oxide layer SiOx in step 3) is 0.5nm-50nm, and the thickness of the polysilicon layer is 50nm-400nm.

[0022] Further, the green laser with a wavelength of 300nm-680nm is used in the laser doping of step 5).

[0023] Further, the acid solution is used for preliminary cleaning in step 6), and then the cleaning is performed in an ultrasonic cleaning machine, and the cleaning time is 5min-30min.

[0024] Further, the annealing temperature in step 7) is 800℃-1000℃, and the annealing time is 5min-120min.

[0025] Further, the passivation layer in step 9) is an aluminum oxide passivation layer, and the thickness is 1nm-10nm.

[0026] The thickness of the first and second anti-reflective layers in step 10) is 50nm-150nm.

[0027] Further, when the doping area width is greater than 150μm or the single-doped area accounts for more than 16% of the total area, the laser spot size is 50μm-150μm in length.

[0028] When the doping area width is greater than 250μm or the single-doped area accounts for more than 25% of the total area, the laser spot size is 100μm-200μm in length.

[0029] The present application also provides a TBC battery, and the width of the N and P regions is 200μm-300μm.

[0030] Further, the area of the N / P region is only 5%-8% larger than the area of the metal grid line, and the gap region is a polished surface layer.

[0031] The present application has the following advantages:

[0032] The preparation method of the TBC battery provided by the present application can simplify the preparation process, shorten the process time, and reduce the production cost, which is conducive to the large-scale industrialization and popularization of the TBC battery.

[0033] The application adjusts printing and laser patterns, reduces P region or / and N region area (makes P region / N region area only slightly larger than metal grid line area), increases gap region area, reduces metal shielding area, improves photon utilization, significantly improves current density; reduces metal region recombination, improves Voc and passivation performance of the battery piece. By polishing the gap region with a pyramid surface, the reflection of incident light in the silicon substrate can be increased, thereby improving the battery Isc. At the same time, since the initial gap region is protected by the mask layer, it is not damaged by subsequent wet etching, which can reduce the height difference between the gap region and the boron / phosphorus diffusion layer, which is beneficial to the lateral transmission of carriers in the silicon substrate and improves FF.

[0034] The TBC battery prepared by the method of the application has the advantages that, under the condition that the number of partitions on the back of the battery is unchanged, the area of the P region and the N region is reduced, the area of the gap region is increased, the metal shielding area is reduced, the photon utilization is improved, the current density is significantly improved, the metal region recombination is reduced, and the Voc and passivation performance of the battery piece are improved. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 is a schematic structural diagram of an embodiment of the TBC battery of the application;

[0036] Reference signs: 1, P region; 2, N region; 3, gap region; 4, passivation layer; 5, first antireflection layer; 6, second antireflection layer; 7, first electrode; 8, second electrode; 9, N-type silicon wafer. DETAILED DESCRIPTION

[0037] The following specific examples illustrate the embodiments of the application, and those skilled in the art can easily understand other advantages and effects of the application from the disclosure.

[0038] Exemplary embodiments of the application will now be described with reference to the accompanying drawings, however, the application can be implemented in many different forms and is not limited to the embodiments described herein, which are provided to fully and completely disclose the application and to fully convey the scope of the application to those skilled in the art. The terms used in the exemplary embodiments shown in the drawings are not limitations of the application. In the drawings, the same elements / elements are denoted by the same reference numerals.

[0039] Unless otherwise defined, the terms used herein (including technical terms) have the meanings commonly understood by those skilled in the art. In addition, it can be understood that the terms defined in commonly used dictionaries should be understood in the context of the relevant art, and should not be understood in an idealized or overly formal sense.

[0040] The application provides a preparation method of a TBC battery, comprising the following steps:

[0041] Step 1) Polishing of raw silicon: Put the N-type silicon wafer 9 into a tank of alkaline solution for polishing;

[0042] Step 2) Mask layer formation: Print paste on the gap area 3 on the back of the silicon wafer to form a mask layer;

[0043] Further, the mask layer is SiOx, SiNx or SiO X N y；

[0044] Step 3) Substrate deposition: First deposit an ultra-thin tunneling silicon oxide layer SiOx on the back of the silicon wafer, and then deposit a polysilicon Poly layer;

[0045] Further, the thickness of the ultra-thin tunneling silicon oxide layer SiOx is 0.5nm-50nm, and the thickness of the polysilicon Poly layer is 50nm-400nm;

[0046] Step 4) Preparation of PN doping source: Print boron paste containing boron elements and phosphorus paste containing phosphorus elements on the polysilicon Poly layer to form multiple paste areas, and perform drying after printing is completed;

[0047] Step 5) Laser doping: After printing and drying, laser doping is performed, and by adjusting the laser pattern and laser parameters, the boron paste and phosphorus paste areas are laser doped, and the non-printed areas are laser opened;

[0048] Further, the laser doping is performed using a green laser with a wavelength of 300nm-680nm.

[0049] The green nanosecond laser with a wavelength of 532nm has better doping effect; when the laser power is 40-60W, the doping effect is good and damage is not easy to cause;

[0050] When the doping area width is 150μm or more or the single doping area accounts for 16% or more of the total area, the laser spot size is 50μm-150μm in length;

[0051] When the doping area width is 250μm or more or the single doping area accounts for 25% or more of the total area, the laser spot size is 100μm-200μm in length;

[0052] Step 6) Cleaning and local etching: Clean the impurities and residues on the surface of the P region 1 and the N region 2, and etch away the poly layer between the P region 1 and the N region 2 to form the gap area 3;

[0053] Further, first use an acid solution for preliminary cleaning, and then clean in an ultrasonic cleaning machine for 5min-30min.

[0054] At this time, the gap region 3 is protected by a mask, and cleaning only etches away the polysilicon Poly layer;

[0055] Step 7) Annealing treatment: the cleaned substrate is subjected to annealing treatment to activate the doped region and realize local P+ and N+ doping; the polysilicon Poly layer is doped by annealing and the laser damage is repaired at the same time;

[0056] Further, the annealing temperature is 800-1000 DEG C, and the annealing time is 5-120 min.

[0057] Step 8) Texturing: the front surface of the silicon wafer is textured to form a pyramid structure on the surface of the single crystal silicon wafer, thereby enhancing the absorption of sunlight and reducing reflection; at this time, the gap region 3 is protected by a mask, and there is no texturing, and then the mask layer of the gap region 3 is removed by HF;

[0058] Step 9) Deposition of passivation layer 4;

[0059] Further, the passivation layer 4 is an aluminum oxide passivation layer 4 with a thickness of 1-10 nm.

[0060] Step 10) Front and back films: the first anti-reflection layer 5 and the second anti-reflection layer 6 are deposited on the front and back surfaces, respectively.

[0061] Further, the thickness of the first anti-reflection layer 5 and the second anti-reflection layer 6 is 50-150 nm.

[0062] Step 11) Screen printing and sintering: the first electrode 7 and the second electrode 8 are prepared above the P+ region and the N+ region, respectively, and the first electrode 7 and the second electrode 8 penetrate the passivation layer 4 and the anti-reflection film to connect with the P+ region and the N+ region, respectively.

[0063] The preparation method of the application can simplify the preparation process, shorten the process time, and reduce the production cost, which is conducive to the large-scale industrialization and popularization of TBC batteries.

[0064] The application also provides a TBC battery, wherein the width of the N region 2 and the P region 1 is 200-300 μm.

[0065] The TBC battery can increase the area of the gap region 3, reduce the metal blocking area, improve the photon utilization rate, and significantly improve the current density by reducing the area of the P region 1 and the N region 2 without changing the number of partition regions on the back surface of the battery.

[0066] Furthermore, the area of ​​the N region 2 / P region 1 is only 5%~8% larger than the area of ​​the metal grid line, and the gap region 3 is a polished surface layer.

[0067] The goal is to increase the area of ​​gap region 3; polishing gap region 3 can increase the reflection of incident light in the silicon substrate, thereby improving the cell Isc.

[0068] Example 1

[0069] The preparation method of the TBC battery in this embodiment includes the following steps:

[0070] S1. Polishing of raw silicon: The N-type silicon wafer 9 is placed in a tank alkaline solution for polishing;

[0071] S2. Print silicon oxide paste as a mask in the gap area 3 on the back of the silicon wafer;

[0072] S3. Substrate deposition: An ultrathin tunneling silicon oxide layer SiOx is prepared on the back side of the silicon wafer using LPCVD or PECVD technology, and then a polycrystalline silicon Poly layer is deposited. The thickness of the tunneling SiOx is 1.5nm~50nm, and the thickness of the polycrystalline silicon Poly layer is 300nm.

[0073] S4, PN doping source preparation: Boron paste containing boron and phosphorus paste containing phosphorus are printed on poly to form multiple paste regions. After printing, the paste is dried.

[0074] like Figure 1 As shown, in this embodiment, the slurry is divided into three regions: two P regions 1 and one N region 2, each with a width of 270 μm (the area is slightly larger than that of the metal wire grid).

[0075] S5, Laser doping: After printing and drying, a green laser with a wavelength of 532nm is used for laser doping. The laser power is 50W and the spot size is 150μm on each side. By adjusting the laser pattern and laser parameters, laser doping is performed on the boron paste and phosphorus paste areas, and laser film opening is performed on the non-printed areas.

[0076] S6. Cleaning and local etching: Initial cleaning with hydrofluoric acid solution, followed by cleaning in an ultrasonic cleaner for 20 minutes to remove impurities and residues on the surface of the P-type and N-type regions, while etching away the poly layer between P-region 1 and N-region 2 to form gap region 3.

[0077] S7. Annealing treatment: The cleaned substrate is annealed at a temperature of 900℃ for 30 minutes to activate the doped regions and achieve localized P+ and N+ doping.

[0078] S8, Texturing: Texturing is performed on the front surface of the silicon wafer to form a pyramid structure on the surface of the monocrystalline silicon wafer, thereby enhancing the absorption of sunlight and reducing reflection; at this time, the gap region 3 on the back surface is protected by a mask, and there is no texturing, and then the mask is removed by HF;

[0079] S9, ALD: An aluminum oxide passivation layer 4 is deposited, with a thickness of 4 nm;

[0080] S10, Front and back films: A first anti-reflective layer 5 and a second anti-reflective layer 6 are respectively deposited on the front and back surfaces, both with a thickness of 80 nm;

[0081] S11, Screen printing and sintering: A first electrode 7 and a second electrode 8 are prepared above the P+ region and the N+ region, and the electrodes penetrate the passivation layer and the anti-reflective film to connect with the P+ region and the N+ region. As shown in Figure 1

[0082] Example 2

[0083] This example is the same as Example 1 in terms of the preparation process, except that in S4, the width of the N region 2 and the P region 1 is 200 μm.

[0084] Example 3

[0085] This example is the same as Example 1 in terms of the preparation process, except that the width of the N region 2 and the P region 1 is 300 μm.

[0086] Comparative Example 1

[0087] A preparation method of a TBC battery, which is the same as Example 1 in terms of the preparation process, except that in S4, the width of the N region 2 and the P region 1 is 370 μm.

[0088] Comparative Example 2

[0089] A preparation method of a TBC battery, which is the same as Example 1 in terms of the preparation process, except that in S8, the mask layer is removed by acid before texturing, and then texturing is performed to make the gap region 3 have a pyramid texture.

[0090] Comparative Example 3

[0091] A preparation method of a TBC battery, which is the same as Example 1 in terms of the width of the P region 1 and the N region 2, but the entire preparation process is different, including the following steps:

[0092] S1, Original silicon polishing: The N-type silicon wafer 9 is placed in a tank-type alkali solution for polishing;

[0093] S2, Printing silicon oxide slurry as a mask on the gap region 3 on the back surface of the silicon wafer;

[0094] ​S3, first deposition and diffusion: a first tunneling oxide layer and a first polysilicon layer are deposited on the back surface of the silicon substrate in sequence, then boron diffusion is performed to form an overall P+poly layer, and a BSG layer is formed on the surface thereof;

[0095] S4, first laser processing: according to the division of the back surface area of the silicon substrate in the pre-designed pattern, the N area 2 and the gap area 3 of the back surface of the silicon substrate are processed by laser to excavate the N area 2;

[0096] S5, etching treatment: the back surface of the silicon substrate is etched by alkali solution;

[0097] S6, second deposition and diffusion: a second tunneling oxide layer and a second polysilicon layer are deposited on the back surface of the silicon substrate in sequence, then phosphorus diffusion is performed to form an overall N+poly, and a PSG layer is formed on the surface thereof;

[0098] S7, second laser processing: the P area 1 and the gap area 3 of the back surface of the silicon substrate are processed by laser to excavate the P area 1 and the gap area 3;

[0099] S8, texturing: the front surface of the silicon wafer is textured to form a pyramid structure on the surface of the single crystal silicon wafer to enhance the absorption of sunlight and reduce reflection; at this time, the gap area 3 on the back surface is protected by a mask and is not textured, and then the mask is removed by HF;

[0100] S9, ALD: an aluminum oxide passivation layer 4 with a thickness of 4 nm is deposited;

[0101] S10, front and back films: a first anti-reflective layer 5 and a second anti-reflective layer 6 are deposited on the front and back surfaces respectively, both with a thickness of 80 nm;

[0102] S11, screen printing and sintering: a first electrode 7 and a second electrode 8 are prepared above the P+ area and the N+ area, and the electrodes penetrate the passivation layer and the anti-reflective film to connect with the P+ area and the N+ area.

[0103] In order to further illustrate the effects of the present application, the TBC cells prepared in Examples 1-3 and Comparative Examples 1-3 were subjected to electrical performance tests, and the results are shown in Table 1.

[0104] Table 1: Performance test of the cells of Example 1 and each comparative example

[0105] Group Conversion efficiency Eta (%) Open circuit voltage Voc (mV) Short circuit current Jsc(mA / cm 2 )]]> Fill factor FF (%) Example 1 26.61 744.6 16.06 85.11 Example 2 26.53 744.2 16.039 85.02 Example 3 26.56 744.3 15.991 85.01 Comparative Example 1 26.29 740.1 15.99 84.98 Comparative Example 2 26.49 744.1 16.02 85.02 Comparative Example 3 26.44 744 15.989 85.02

[0106] As can be seen from the comparison of Example 1, Example 2 and Example 3 in Table 1, the width of the N area and the P area in Example 2 is smaller than that in Example 1, which may cause electrical leakage due to the overlap of the metal grid lines, and the efficiency is slightly reduced; the width of the N area and the P area in Example 3 is larger than that in Example 1, and the metal shielding area and the metal area are slightly larger, which slightly affects the cell efficiency.

[0107] From the test results of the embodiment 1 and the comparative example 1 of the present application, it can be seen that the test results of the embodiment 1 are better than those of the comparative example 1, because the area of the gap region 3 is increased, the metal shielding area is reduced, the photon utilization rate is improved, the short-circuit current is increased, and the metal region recombination is reduced, the Voc and passivation performance of the battery piece are improved.

[0108] From the test results of the embodiment 1 and the comparative example 2 of the present application, it can be seen that the test results of the embodiment 1 are better than those of the comparative example 2, which is mainly because the gap region 3 with the pyramid surface is polished, the reflection of the incident light in the silicon substrate is increased, and the battery Isc is increased; at the same time, the initial isolation region is protected by the mask layer, and is not damaged by the subsequent wet etching, the height difference between the isolation region and the boron / phosphorus diffusion layer is reduced, which is beneficial to the lateral transmission of the carriers in the silicon substrate, and the FF is increased.

[0109] Compared with the comparative example 3 of the embodiment 1 of the present application, the process steps are greatly simplified, the process difficulty is reduced, and the production efficiency is improved. Although the P region 1 and the N region 2 in the comparative example and the embodiment 1 have the same width, due to the problems such as thermal damage (high-temperature process may introduce lattice defects, increase surface recombination loss), difficulty in controlling the doping concentration (full-area doping leads to Auger recombination in high-concentration regions, limiting the open-circuit voltage improvement), and the like, the battery efficiency is reduced.

[0110] The above examples are only examples of the application and do not constitute a limitation on the protection scope of the application. Any design identical or similar to the application falls within the protection scope of the application.

Claims

1. A method of making a TBC battery, characterized by: The method comprises the following steps: Step 1) original silicon polishing: put the N-type silicon wafer into a tank type alkali solution for polishing; Step 2) forming a mask layer: printing paste on the gap area of the back of the silicon wafer to form a mask layer; Step 3) substrate deposition: first depositing an ultra-thin tunneling silicon oxide layer SiOx on the back of the silicon wafer, and then depositing a polysilicon Poly layer; Step 4) PN doping source preparation: printing boron paste containing boron elements and phosphorus paste containing phosphorus elements on the polysilicon Poly layer to form multiple paste areas, and drying after printing; Step 5) laser doping: after printing and drying, laser doping is carried out, and by adjusting the laser pattern and laser parameters, the boron paste and phosphorus paste areas are laser doped, and the non-printing area is laser opened; Step 6) cleaning and local etching: cleaning removes impurities and residues on the surface of the P and N areas, and etching the poly layer between the P and N areas to form a gap area; Step 7) annealing treatment: annealing the cleaned substrate to activate the doped area and realize local P+ and N+ doping; Step 8) texturing: texturing the front surface of the silicon wafer to form a pyramid structure on the surface of the single crystal silicon wafer; removing the mask layer of the gap area with HF; Step 9) deposition of passivation layer; Step 10) front and back film: depositing a first anti-reflective layer and a second anti-reflective layer on the front and back respectively; Step 11) screen printing and sintering: preparing a first electrode and a second electrode above the P+ area and the N+ area respectively, and the first electrode and the second electrode penetrate the passivation layer and the anti-reflective film to connect with the P+ area and the N+ area respectively.

2. The method of claim 1, wherein: The mask layer in step 2) is SiOx, SiNx or SiO X N y .

3. The method of claim 1, wherein: The thickness of the ultra-thin tunneling silicon oxide layer SiOx in step 3) is 0.5nm-50nm, and the thickness of the polysilicon Poly layer is 50nm-400nm.

4. The method of claim 1, wherein: The wavelength of the green laser used in step 5) laser doping is 300nm-680nm.

5. The method of claim 1, wherein: The cleaning and local etching in step 6) is first cleaned with an acid solution, and then cleaned in an ultrasonic cleaning machine for 5min-30min.

6. The method of claim 1, wherein: The annealing temperature in step 7) is 800℃-1000℃, and the annealing time is 5min-120min.

7. The method of claim 1, wherein: The passivation layer in step 9) is an aluminum oxide passivation layer with a thickness of 1nm-10nm; The thickness of the first anti-reflective layer and the second anti-reflective layer in step 10) is 50nm-150nm.

8. The method of claim 1, wherein: When the doping area width is more than 150μm or the single doping area accounts for more than 16% of the total area, the spot size of the laser is 50μm-150μm in length; When the doping area width is more than 250μm or the single doping area accounts for more than 25% of the total area, the spot size of the laser is 100μm-200μm in length.

9. A TBC cell prepared by the method of any one of claims 1 to 8. The width of the N area and the P area is 200μm-300μm.

10. A TBC cell according to claim 9, wherein: The area of the N area / P area is only 5%-8% larger than the area of the metal gate line, and the gap area is a polished surface layer.

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