An operational amplifier circuit with low noise and high gain-bandwidth product

Abstract

The application discloses a kind of low noise and high gain bandwidth product operational amplifier circuit, it is related to the technical field of electronic circuit, it solves the technical problem of the low noise and high gain bandwidth product operational amplifier circuit urgently needed at present.The circuit includes input stage, bias stage and output stage connected in turn;The output stage is push-pull structure, the bias stage is used to provide bias for the output stage;Feedback loop is arranged between the bias stage and the output stage, for determining the current of the output stage;Phase compensation stage is arranged between the feedback loop and the output stage, for providing phase compensation for output stage.The application not only can reduce the noise of circuit output stage, but also can improve the gain bandwidth product of operational amplifier.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and more particularly to an operational amplifier circuit with low noise and high gain-bandwidth product. Background Technology

[0002] Operational amplifiers (op-amps) are the basic units of analog circuits, widely used in signal chain electronic products such as analog filters, digital-to-analog / analog-to-digital converters, and gain amplifiers. To achieve a higher signal-to-noise ratio in the signal chain, op-amp circuits with lower noise are required. With the increase in communication bandwidth, low-noise op-amps with higher gain-bandwidth products are also needed.

[0003] like Figure 1 The diagram shows a conventional op-amp circuit structure (differential form). The op-amp noise is generally measured by the input reference noise, primarily contributed by the noise of the input stage. The output stage noise, divided by the input stage gain, contributes to the op-amp's input reference noise. Therefore, a higher input stage gain is needed to further reduce output stage noise, typically achieved by increasing the size of the components in the op-amp's input stage (e.g., in...). Figure 1 In this process, the device size of MOSFETs M100~M400 is increased to reduce their flicker noise and the input gain is increased to better suppress the noise of the output stage.

[0004] However, larger input stages result in larger parasitic capacitances, limiting the op-amp's ability to achieve a high gain-bandwidth product. Currently, a cascode structure is used in the input stage to reduce noise; the common-gate transistor contributes very little to noise and can be designed to be small, resulting in smaller parasitic capacitance at the first-stage output node of the op-amp and thus achieving a higher gain-bandwidth product. However, current CMOS processes make the operating voltage of this structure too low, making it difficult to implement.

[0005] Furthermore, to achieve a higher gain-bandwidth product, the op-amp output stage requires a larger transconductance to push the secondary point to a higher frequency, but this consumes more current. To save current, a push-pull structure can be used for the second stage of the op-amp. The bias circuit of the push-pull structure is a key design consideration, especially in advanced CMOS processes where the operating voltage is lower. Currently, there are generally two ways to provide bias: one is to use capacitive coupling, but this requires a large coupling capacitor area, and the parasitic capacitance of the coupling capacitor to ground will limit the gain-bandwidth product of the op-amp; the other is to provide bias through current mirroring, but this method also results in a large parasitic capacitance in the device, which will also limit the gain-bandwidth product of the op-amp.

[0006] In the process of realizing this invention, the inventors discovered at least the following problems in the prior art:

[0007] There is an urgent need for an operational amplifier circuit with low noise and high gain-bandwidth product. Summary of the Invention

[0008] The purpose of this invention is to provide an operational amplifier circuit with low noise and high gain-bandwidth product, so as to solve the technical problem that there is an urgent need for an operational amplifier circuit with low noise and high gain-bandwidth product in the prior art.

[0009] The preferred technical solutions among the many technical solutions provided by this invention can produce a variety of technical effects, which are described in detail below.

[0010] To achieve the above objectives, the present invention provides the following technical solution:

[0011] This invention provides a low-noise and high-gain-bandwidth operational amplifier circuit, comprising an input stage, a bias stage, and an output stage connected in sequence; the bias stage is used to provide bias for the output stage; the output stage has a push-pull structure; a feedback loop is provided between the bias stage and the output stage to determine the current of the output stage; a phase compensation stage is provided between the feedback loop and the output stage to provide phase compensation for the output stage.

[0012] The bias stage includes MOSFETs M1, M2, M3, and M4; the gate of MOSFET M1 is connected to the gate of MOSFET M2; the drains of MOSFET M1 and M2 are both connected to the output stage; the sources of MOSFET M1 and M2 are both connected to a reference voltage; the gate of MOSFET M3 is connected to the gate of MOSFET M4; the sources of MOSFETs M3 and M4 are connected to the input stage, and the drains of MOSFETs M3 and M4 are both connected to the output stage.

[0013] The bias stage also includes a current source I; the first end of the current source I is connected to the source of the MOS transistor M3 and the source of the MOS transistor M4, and the second end is grounded.

[0014] Optionally, the feedback loop consists of a non-inverting amplifier and an inverting amplifier; the outputs of the non-inverting amplifier and the inverting amplifier are added together and connected to the gate of the MOS transistor M3; the input terminals of the non-inverting amplifier and the inverting amplifier are both connected to the output stage.

[0015] Optionally, the feedback loop includes MOSFETs M7, M8, M9, M10, and M11; the gate of MOSFET M7 is connected to the gate of MOSFET M3, its drain is connected to the drains of MOSFETs M9 and M10, and its source is connected to ground; the gate of MOSFET M7 is also connected to its own drain; the gate of MOSFET M8 is connected to the output stage, its drain is connected to the drain of MOSFET M11, and its source is grounded; the gate of MOSFET M9 is connected to the output stage, and its source is connected to a reference voltage; the gate of MOSFET M10 is connected to the gate of MOSFET M11, and its source is connected to the reference voltage; the source of MOSFET M11 is connected to the reference voltage; the gate of MOSFET M11 is also connected to its own drain.

[0016] Optionally, the output stage includes MOSFET M5 and MOSFET M6; the gate of MOSFET M5 is connected to the drain of MOSFET M2, the drain of MOSFET M4, and the input terminal of the inverting amplifier in the feedback loop, the source is connected to the reference voltage, and the drain is connected to the output terminal of the operational amplifier circuit; the gate of MOSFET M6 is connected to the drain of MOSFET M1, the drain of MOSFET M3, and the input terminal of the non-inverting amplifier in the feedback loop, the source is grounded, and the drain is connected to the output terminal of the operational amplifier circuit.

[0017] Optionally, MOSFET M9 serves as the inverting amplifier between MOSFETs M3 and M5; MOSFETs M8, M10, and M11 serve as the non-inverting amplifier between MOSFETs M3 and M6; the output currents of the inverting amplifier and the non-inverting amplifier are summed on MOSFET M7 and used as the gate input of MOSFET M3.

[0018] Optionally, the gate of MOSFET M5 is connected to the gate of MOSFET M9; the gate of MOSFET M6 is connected to the gate of MOSFET M8.

[0019] Optionally, the phase compensation stage includes a first phase compensation circuit and a second phase compensation circuit; the input terminal of the first phase compensation circuit is connected to the gate of the MOS transistor M9, and the output terminal is connected to the output terminal of the operational amplifier circuit; the input terminal of the second phase compensation circuit is connected to the gate of the MOS transistor M8, and the output terminal is connected to the output terminal of the operational amplifier circuit.

[0020] Optionally, the operational amplifier circuit is a differential circuit; the input stage is a differential input stage with symmetrical differential outputs: a first differential signal VP1 and a second differential signal VN1; the bias stage includes a first bias unit and a second bias unit with symmetrical structure; the output stage includes a first output unit and a second output unit with symmetrical structure; the feedback loop includes a first feedback unit and a second feedback unit with symmetrical structure; the first differential signal VP1 is connected to the input terminal of the first bias unit; the output terminal of the first bias unit is connected to the first output unit; the first feedback unit is disposed between the first bias unit and the first output unit; the second differential signal VN1 is connected to the input terminal of the second bias unit; the output terminal of the second bias unit is connected to the second output unit; the second feedback unit is disposed between the second bias unit and the second output unit.

[0021] Implementing one of the above-described technical solutions of the present invention has the following advantages or beneficial effects:

[0022] The operational amplifier circuit with low noise and high gain-bandwidth product provided by this invention reduces the noise of the output stage by setting a bias stage. In CMOS technology, the input stage and the bias stage are set on the same level to form a folded cascode structure. This not only overcomes the problem of difficulty in implementation in CMOS technology due to the low operating voltage, but also enables the operational amplifier circuit to obtain higher gain. In addition, the design of the bias stage of this invention can also provide bias for the output stage of the push-pull structure without introducing unnecessary parasitic capacitance, further improving the gain-bandwidth product of the operational amplifier. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0024] Figure 1 This is a circuit diagram of an existing operational amplifier circuit;

[0025] Figure 2 This is a circuit diagram of the operational amplifier circuit according to an embodiment of the present invention;

[0026] Figure 3 This is an overall circuit diagram of the operational amplifier circuit in an embodiment of the present invention;

[0027] Figure 4 This is a circuit diagram of a differential operational amplifier circuit according to an embodiment of the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the present invention clearer, various exemplary embodiments described below will be referenced to the accompanying drawings, which form part of the exemplary embodiments, illustrating various exemplary embodiments that may be used to implement the present invention. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. It should be understood that they are merely examples of processes, methods, and apparatuses consistent with some aspects of the present invention disclosed as detailed in the appended claims, and other embodiments may be used, or structural and functional modifications may be made to the embodiments listed herein without departing from the scope and spirit of the present invention.

[0029] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," etc., indicate the orientation or positional relationship based on the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the referred element must have a specific orientation, or be constructed and operated in a specific orientation. The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. The term "a plurality" means two or more. The terms "connected" and "linked" should be interpreted broadly, for example, they can refer to fixed connections, detachable connections, integral connections, mechanical connections, electrical connections, communication connections, direct connections, indirect connections through an intermediate medium, and can refer to the internal communication of two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more of the related listed items. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0030] To illustrate the technical solution described in this invention, specific embodiments are described below, showing only the parts related to the embodiments of this invention.

[0031] Example 1:

[0032] like Figure 2As shown, this invention provides an operational amplifier circuit with low noise and a high gain-bandwidth product, including an input stage, a bias stage, and an output stage connected in sequence. The input stage and the bias stage are located on the same level. The output stage is a push-pull structure, and the bias stage is used to provide bias for the output stage. In CMOS technology, placing both the input stage and the bias stage in the first stage forms a folded cascode structure to achieve higher gain while avoiding the problem of difficult implementation of the cascode structure and input stage design due to excessively low operating voltage. Furthermore, by providing bias for the push-pull output stage, the gain-bandwidth product can be further improved while maintaining low noise. A feedback loop is provided between the bias stage and the output stage to determine the current of the output stage.

[0033] Specifically, taking a single-ended output configuration as an example, the bias stage includes MOSFETs M1, M2, M3, and M4. MOSFETs M1 and M2 have a common-source, common-gate structure, with the drains of both MOSFETs connected to the output stage. MOSFETs M3 and M4 also have a common-source, common-gate structure (both MOSFETs M3 and M4 output a common fixed bias VBN; to distinguish them in the feedback loop, the fixed bias of MOSFET M3 is denoted as VBN1). The common-source terminals of MOSFETs M3 and M4 are connected to the input stage, and the drains of both MOSFETs M3 and M4 are connected to the output stage. It should be noted that, to improve the anti-interference capability of the op-amp circuit signal chain, the op-amp circuit in this embodiment can also be configured with differential output.

[0034] The operational amplifier circuit with low noise and high gain-bandwidth product provided by this invention reduces the noise of the output stage by setting a bias stage. In CMOS technology, the input stage and the bias stage are set on the same level to form a folded cascode structure. This not only overcomes the problem of difficulty in implementation in CMOS technology due to the low operating voltage, but also enables the operational amplifier circuit to obtain higher gain. In addition, the design of this bias stage can also provide bias for the push-pull structure output stage without introducing unnecessary parasitic capacitance, further improving the gain-bandwidth product of the operational amplifier.

[0035] As an alternative implementation method, such as Figure 2 As shown, the input stage includes an operational amplifier; the non-inverting and inverting input terminals of the operational amplifier are connected to the first differential signal and the second differential signal, respectively, and the output terminal is connected to the source of MOSFET M3 and the source of MOSFET M4. The structure of this operational amplifier is similar to that shown below. Figure 1The output stage of the circuit shown is similar, including MOSFETs M10, M20, M30, and M40. The gate of MOSFET M10 serves as the non-inverting input of the operational amplifier, connected to the first differential signal IN-P, and its source is connected to the reference voltage. The gate of MOSFET M20 serves as the inverting input of the operational amplifier, connected to the second differential signal IN-N, and its source is connected to the reference voltage. The drains of MOSFETs M30 and M12 are connected to each other, as are the drains of MOSFETs M4 and M15. The gates of MOSFETs M30 and M40 are connected to the common-mode feedback voltage VCMBF, and the sources of both MOSFETs M30 and M40 are grounded. The drains of MOSFETs M10, M20, M30, and M40 serve as the outputs of the operational amplifier, connected to the common-mode stage. In the output stage, MOSFETs M1 through M4 contribute current thermal noise and flicker noise. To reduce flicker noise, the device dimensions of MOSFETs M1 through M4 can be increased; to reduce current thermal noise, the current of current source I0 and the width-to-length ratio of MOSFETs M1 and M2 can be increased. For example, if the length of MOSFETs M1 and M2 is increased by a times (a>1), and the current of current source I0 is increased by a times (b>1), then the width should be increased by a. Amplifying the capacitance by a factor of b will reduce input-referenced flicker noise and current thermal noise. However, this will also increase the drain parasitic capacitance of MOSFETs M1 to M4 by a. a The gain-bandwidth product of the op-amp will be severely limited by a factor of b.

[0036] Therefore, in this embodiment, a bias stage is set between the input unit and the output unit. The MOS transistors (MOS transistors M1 to M4) in the bias stage are all small in size, so that there is a smaller parasitic capacitance at the output node of the input stage, thereby obtaining a larger gain-bandwidth product. On the other hand, MOS transistors M1 to M4 increase the gain of the input stage, which can suppress the noise of the output stage.

[0037] As an alternative implementation, the output stage includes MOSFETs M5 and M6. The gate of MOSFET M5 is connected to the drains of MOSFETs M2 and M4, as well as the input of the inverting amplifier in the feedback loop. Its source is connected to the reference voltage, and its drain is connected to the output of the operational amplifier circuit. The gate of MOSFET M6 is connected to the drains of MOSFETs M1 and M3, as well as the input of the non-inverting amplifier in the feedback loop. Its source is grounded, and its drain is connected to the output of the operational amplifier circuit. Setting the output stage as a push-pull structure can achieve a larger gain-bandwidth product. A bias stage is then used to provide bias for the output stage to ensure that the push-pull structure can operate normally.

[0038] As an alternative implementation, the feedback loop consists of a non-inverting amplifier and an inverting amplifier; the outputs of the non-inverting and inverting amplifiers are summed and connected to the gate of MOSFET M3; the inputs of both the non-inverting and inverting amplifiers are connected to the output stage. By setting a feedback loop between the bias stage and the output stage, the current of the output stage can be further determined.

[0039] Specifically, the feedback loop includes MOSFETs M7, M8, M9, M10, and M11. The gate of MOSFET M7 is connected to the gate of MOSFET M3, its drain is connected to the drains of MOSFETs M9 and M10, and its source is grounded. The gate of MOSFET M7 is also connected to its own drain. The gate of MOSFET M8 is connected to the output stage, its drain is connected to the drain of MOSFET M11, and its source is grounded. The gate of MOSFET M6 is connected to the gate of MOSFET M8. The gate of MOSFET M9 is connected to the output stage, and its source is connected to the reference voltage. The gate of MOSFET M5 is connected to the gate of MOSFET M9. The gate of MOSFET M10 is connected to the gate of MOSFET M11, and its source is connected to the reference voltage. The source of MOSFET M11 is connected to the reference voltage, and its gate is also connected to its own drain. MOSFET M9 acts as an inverting amplifier between MOSFETs M3 and M5; MOSFETs M8, M10, and M11 act as non-inverting amplifiers between MOSFETs M3 and M6; the output currents of the inverting and non-inverting amplifiers are summed on MOSFET M7 and used as the gate input of MOSFET M3.

[0040] By using the two output voltages (VGP and VGN) of the bias stage to drive the non-inverting amplifier and the inverting amplifier respectively, and summing their outputs, the signal feedback from one output voltage VP1 to voltage VGN is interrupted. The signal from VP1 is then amplified normally to VGN through MOSFET M3. Furthermore, if MOSFETs M3 and M4 are set to have the same dimensions and bias current, the gains from VP1 to VGP and VGN will be essentially the same, allowing MOSFETs M5 and M6 to operate as a normal push-pull output stage.

[0041] like Figure 3As shown, MOSFET M9 acts as the inverting amplifier from VGP to VBN1, while MOSFETs M8, M10, and M11 act as the non-inverting amplifiers from VGN to VBN1. The output currents of the two amplifiers are summed across MOSFET M7 (connected to a diode), and this sum is used as the gate input of MOSFET M3. The currents of MOSFETs M3 and M4 are equal, equal to I / 2. The current of MOSFET M17 is determined by a certain ratio. MOSFETs M19, M20, and M21 are identical in size and have equal currents; therefore, the current of MOSFET M18 is equal to half the current of M17. MOSFETs M18 and M8 have the same gate voltage. The current of MOSFET M8 is determined by the aspect ratio of the two transistors, thus determining the current of the push-pull output stage.

[0042] As an alternative implementation, the first bias stage further includes current sources I1 and I2; the first terminal of current source I1 is connected to a reference voltage, and the second terminal is connected to the source of MOSFET M9 and the source of MOSFET M10; the first terminal of current source I2 is connected to the source of MOSFET M11 and the source of MOSFET M12, and the second terminal is grounded. The second bias stage further includes current sources I3 and I4; the first terminal of current source I3 is connected to a reference voltage, and the second terminal is connected to the source of MOSFET M13 and the source of MOSFET M14; the first terminal of current source I4 is connected to the source of MOSFET M15 and the source of MOSFET M16, and the second terminal is grounded. By setting current sources, the circuit current is stabilized, ensuring that the circuit can operate stably under predetermined current conditions, and the current information of the circuit can be obtained through the current sources to facilitate circuit management and maintenance adjustments.

[0043] The embodiment is merely a specific example and does not indicate that this is the only way to implement the present invention.

[0044] The above description is merely a preferred embodiment of the present invention. Those skilled in the art will understand that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the present invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. An operational amplifier circuit with low noise and high gain-bandwidth product, characterized in that, It includes an input stage, a bias stage, and an output stage connected in sequence; the bias stage is used to provide bias for the output stage; the output stage has a push-pull structure; a feedback loop is provided between the bias stage and the output stage to determine the current of the output stage; a phase compensation stage is provided between the feedback loop and the output stage to provide phase compensation for the output stage. The bias stage includes MOSFETs M1, M2, M3, and M4; the gate of MOSFET M1 is connected to the gate of MOSFET M2; the drains of MOSFET M1 and M2 are both connected to the output stage; the sources of MOSFET M1 and M2 are both connected to a reference voltage; the gate of MOSFET M3 is connected to the gate of MOSFET M4; the sources of MOSFETs M3 and M4 are connected to the input stage, and the drains of MOSFETs M3 and M4 are both connected to the output stage. The bias stage further includes a current source I; the first end of the current source I is connected to the source of the MOS transistor M3 and the source of the MOS transistor M4, and the second end is grounded; The feedback loop consists of a non-inverting amplifier and an inverting amplifier; the outputs of the non-inverting amplifier and the inverting amplifier are added together and connected to the gate of the MOS transistor M3; the input terminals of the non-inverting amplifier and the inverting amplifier are both connected to the output stage; The output stage includes MOSFETs M5 and M6. The gate of MOSFET M5 is connected to the drain of MOSFET M2, the drain of MOSFET M4, and the input terminal of the inverting amplifier in the feedback loop. The source is connected to the reference voltage, and the drain is connected to the output terminal of the operational amplifier circuit. The gate of MOSFET M6 is connected to the drain of MOSFET M1, the drain of MOSFET M3, and the input terminal of the non-inverting amplifier in the feedback loop. The source is grounded, and the drain is connected to the output terminal of the operational amplifier circuit.

2. The operational amplifier circuit with low noise and high gain-bandwidth product according to claim 1, characterized in that, The feedback loop includes MOSFETs M7, M8, M9, M10, and M11. The gate of MOSFET M7 is connected to the gate of MOSFET M3, its drain is connected to the drains of MOSFETs M9 and M10, and its source is grounded. The gate of MOSFET M7 is also connected to its own drain. The gate of MOSFET M8 is connected to the output stage, its drain is connected to the drain of MOSFET M11, and its source is grounded. The gate of MOSFET M9 is connected to the output stage, and its source is connected to a reference voltage. The gate of MOSFET M10 is connected to the gate of MOSFET M11, and its source is connected to the reference voltage. The source of MOSFET M11 is connected to the reference voltage, and its gate is also connected to its own drain. The gate of MOS transistor M5 is connected to the gate of MOS transistor M9; the gate of MOS transistor M6 is connected to the gate of MOS transistor M8.

3. The operational amplifier circuit with low noise and high gain-bandwidth product according to claim 2, characterized in that, The MOS transistor M9 serves as the inverting amplifier between the MOS transistors M3 and M5; the MOS transistors M8, M10, and M11 serve as the non-inverting amplifier between the MOS transistors M3 and M6; the output currents of the inverting amplifier and the non-inverting amplifier are summed on the MOS transistor M7, and this summation is used as the gate input of the MOS transistor M3.

4. The operational amplifier circuit with low noise and high gain-bandwidth product according to claim 2, characterized in that, The phase compensation stage includes a first phase compensation circuit and a second phase compensation circuit; the input terminal of the first phase compensation circuit is connected to the gate of the MOS transistor M9, and the output terminal is connected to the output terminal of the operational amplifier circuit; the input terminal of the second phase compensation circuit is connected to the gate of the MOS transistor M8, and the output terminal is connected to the output terminal of the operational amplifier circuit.

5. The operational amplifier circuit with low noise and high gain-bandwidth product according to claim 1, characterized in that, The operational amplifier circuit is a differential circuit; the input stage is a differential input stage with symmetrical differential outputs: a first differential signal VP1 and a second differential signal VN1; the bias stage includes a first bias unit and a second bias unit with symmetrical structure; the output stage includes a first output unit and a second output unit with symmetrical structure; the feedback loop includes a first feedback unit and a second feedback unit with symmetrical structure; the first differential signal VP1 is connected to the input terminal of the first bias unit; the output terminal of the first bias unit is connected to the first output unit; the first feedback unit is located between the first bias unit and the first output unit; the second differential signal VN1 is connected to the input terminal of the second bias unit; the output terminal of the second bias unit is connected to the second output unit; the second feedback unit is located between the second bias unit and the second output unit.

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