Chip internal conducted interference coupling path test method and system and computer equipment

Abstract

The invention relates to a chip internal conducted interference coupling path testing method and system and computer equipment. The method comprises the following steps: electrifying a to-be-tested chip placed in the infrared phase-locked thermal imaging equipment, and controlling the to-be-tested chip to enter a preset working mode; performing signal synchronization on the voltage excitation signal output by the infrared phase-locked thermal imaging equipment and the electromagnetic interference signal, injecting the synchronized interference signal into the to-be-tested chip, and obtaining an infrared phase-locked hot spot distribution diagram of the to-be-tested chip in a preset working mode through the infrared phase-locked thermal imaging equipment; according to the infrared phase-locked hot spot distribution diagram, internal interference test results of the chip to be tested in the preset working mode are determined, and the internal interference test results comprise a coupling path test result and a sensitive unit test result. And high-precision and visual positioning and analysis of a conducted interference coupling path in the chip and a chip sensitive unit can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip testing, in particular to a chip internal conducted interference coupling path testing method and system and computer equipment. BACKGROUND

[0002] With the continuous development of semiconductor technology towards high frequency, high integration and low voltage, the working frequency of the chip is increased to GHz level, and the power consumption and signal swing are continuously reduced, which leads to a sharp rise in its sensitivity to electromagnetic interference. In high-frequency and high-density application scenarios such as 5G communication, autonomous driving, and Internet of Things, the noise generated by the power supply network, clock circuit, high-speed interface and other modules in the chip is extremely easy to interfere with the adjacent circuits through the conduction or radiation path, and even cause system-level failure. For example, the radio frequency transmission noise of a mobile phone baseband chip may be coupled to the power supply network, resulting in a decrease in the accuracy of the analog-to-digital converter (ADC); if the high-speed switching noise of the processor in the vehicle-mounted SoC is transmitted to the sensor interface through the common impedance, it may cause misjudgment. These challenges force electronic product design to shift from "system-level rectification" to "chip-level optimization", and chip-level electromagnetic compatibility (EMC) testing has thus become an important link to ensure reliability.

[0003] The traditional conducted interference immunity testing method generally directly injects interference signals into the chip through external ports and coupling / decoupling networks, which can effectively evaluate the conducted immunity of the chip, but its core limitation is that it cannot directly detect the chip internal noise coupling path and sensitive units. SUMMARY

[0004] Therefore, it is necessary to provide a chip internal conducted interference coupling path testing method, system, computer equipment, computer readable storage medium and computer program product to realize high-precision, visual positioning and analysis of the chip internal conducted interference coupling path and the chip sensitive unit.

[0005] In a first aspect, the present application provides a chip internal conducted interference coupling path testing method, comprising:

[0006] Powering on the to-be-tested chip placed in the infrared phase-locked thermal imaging device, and controlling the to-be-tested chip to enter a preset working mode;

[0007] Synchronizing the voltage excitation signal output by the infrared phase-locked thermal imaging device with the electromagnetic interference signal, injecting the synchronized interference signal into the to-be-tested chip, and acquiring an infrared phase-locked thermal spot distribution map of the to-be-tested chip in the preset working mode through the infrared phase-locked thermal imaging device;

[0008] According to the infrared phase-locked hot spot distribution map, the internal interference test result of the to-be-tested chip under the preset working mode is determined, and the internal interference test result includes a coupling path test result and a sensitive unit test result.

[0009] In one of the embodiments, according to the infrared phase-locked hot spot distribution map, the internal interference test result of the to-be-tested chip under the preset working mode is determined, including:

[0010] A reference infrared phase-locked map of the to-be-tested chip under the preset working mode is acquired.

[0011] According to the reference infrared phase-locked map and the infrared phase-locked hot spot distribution map, the internal interference test result of the to-be-tested chip under the preset working mode is determined.

[0012] In one of the embodiments, the reference infrared phase-locked map includes a reference amplitude map; the infrared phase-locked hot spot distribution map includes an amplitude distribution map; according to the reference infrared phase-locked map and the infrared phase-locked hot spot distribution map, the internal interference test result of the to-be-tested chip under the preset working mode is determined, including:

[0013] In the case that there is a continuously distributed abnormal high-temperature region in the amplitude distribution map, the amplitude condition of the reference amplitude map and the amplitude distribution map in the abnormal high-temperature region and the injection condition of the radio frequency interference injection point are determined; in the case that the amplitude condition indicates that the amplitude increment at more than a preset number of pixel points reaches a preset threshold, the injection condition indicates that the radio frequency interference injection point is located within the abnormal high-temperature region, and extends along the circuit wiring direction or the power ground plane, it is determined that the abnormal high-temperature region is a radio frequency interference conducted coupling path of the to-be-tested chip under the preset working mode.

[0014] In the case that there is a module unit with an amplitude increment exceeding a preset threshold in the amplitude distribution map, a topological difference evaluation result between the reference amplitude map and the amplitude distribution map is determined; in the case that the topological difference evaluation result exceeds a preset value, the module unit is determined to be a sensitive unit of the to-be-tested chip under the preset working mode.

[0015] In one of the embodiments, the reference infrared phase-locked map includes a reference phase map; the infrared phase-locked hot spot distribution map includes a phase distribution map; according to the reference infrared phase-locked map and the infrared phase-locked hot spot distribution map, the internal interference test result of the to-be-tested chip under the preset working mode is determined, including:

[0016] In the case that there is a continuously distributed closed region in the phase distribution map, the phase delay value of the reference phase map and the phase distribution map in the closed region and the injection condition of the radio frequency interference injection point are determined; in the case that the deviation of the phase delay value exceeds a preset deviation, and the injection condition indicates that the radio frequency interference injection point is located within the closed region, and extends along the circuit wiring direction or the power ground plane, it is determined that the closed region is a radio frequency interference conducted coupling path of the to-be-tested chip under the preset working mode.

[0017] In the case that there is a module unit with a phase change exceeding a preset change amount in the phase distribution map, a topological difference evaluation result between the reference phase map and the phase distribution map is determined; and in the case that the topological difference evaluation result exceeds a preset value, the module unit is determined as a sensitive unit of the chip under test under the preset working mode.

[0018] In one of the embodiments, the reference infrared lock-in map acquisition step comprises:

[0019] The chip under test placed in the infrared lock-in thermal imaging device is powered on, and the chip under test is controlled to enter a preset working mode.

[0020] The reference amplitude map or the reference phase map of the chip under test under the preset working mode is acquired by the infrared lock-in thermal imaging device, and is taken as the reference infrared lock-in map.

[0021] In one of the embodiments, the signal synchronization between the voltage excitation signal output by the infrared lock-in thermal imaging device and the electromagnetic interference signal comprises:

[0022] According to the phase of the voltage excitation signal output by the infrared lock-in thermal imaging device, the signal synchronization device is used to adjust the phase offset of the electromagnetic interference signal to obtain the synchronized interference signal.

[0023] In a second aspect, the application further provides a chip internal conduction interference coupling path test system, comprising:

[0024] a chip under test;

[0025] an infrared lock-in thermal imaging device for acquiring an infrared lock-in thermal point distribution map of the chip under test placed in the infrared lock-in thermal imaging device;

[0026] an electromagnetic interference source connected with the chip under test for outputting an electromagnetic interference signal;

[0027] a signal synchronization device for synchronizing the voltage excitation signal output by the infrared lock-in thermal imaging device with the electromagnetic interference signal, so that the synchronized interference signal is injected into the chip under test;

[0028] a power supply for powering on the chip under test;

[0029] The computer device is used for controlling a power supply to power on a chip under test and controlling the chip under test to enter a preset working mode; a voltage excitation signal output by an infrared lock-in thermal imaging device is synchronized with an electromagnetic interference signal, the synchronized interference signal is injected into the chip under test, and an infrared lock-in thermal spot distribution map of the chip under test under the preset working mode is acquired through the infrared lock-in thermal imaging device; and internal interference test results of the chip under test under the preset working mode are determined according to the infrared lock-in thermal spot distribution map, wherein the internal interference test results include coupling path test results and sensitive unit test results.

[0030] In a third aspect, the present application further provides a computer device, comprising a memory and a processor, the memory storing a computer program, and the processor realizing the following steps when executing the computer program:

[0031] powering on a chip under test placed in an infrared lock-in thermal imaging device and controlling the chip under test to enter a preset working mode;

[0032] synchronizing a voltage excitation signal output by the infrared lock-in thermal imaging device with an electromagnetic interference signal, injecting the synchronized interference signal into the chip under test, and acquiring an infrared lock-in thermal spot distribution map of the chip under test under the preset working mode through the infrared lock-in thermal imaging device;

[0033] determining internal interference test results of the chip under test under the preset working mode according to the infrared lock-in thermal spot distribution map, wherein the internal interference test results include coupling path test results and sensitive unit test results.

[0034] In a fourth aspect, the present application further provides a computer readable storage medium, which stores a computer program, and the computer program realizes the following steps when executed by a processor:

[0035] powering on a chip under test placed in an infrared lock-in thermal imaging device and controlling the chip under test to enter a preset working mode;

[0036] synchronizing a voltage excitation signal output by the infrared lock-in thermal imaging device with an electromagnetic interference signal, injecting the synchronized interference signal into the chip under test, and acquiring an infrared lock-in thermal spot distribution map of the chip under test under the preset working mode through the infrared lock-in thermal imaging device;

[0037] determining internal interference test results of the chip under test under the preset working mode according to the infrared lock-in thermal spot distribution map, wherein the internal interference test results include coupling path test results and sensitive unit test results.

[0038] In a fifth aspect, the present application further provides a computer program product, comprising a computer program, and the computer program realizes the following steps when executed by a processor:

[0039] Power on the to-be-tested chip placed in the infrared lock-in thermal imaging device, and control the to-be-tested chip to enter a preset working mode;

[0040] Synchronize the voltage excitation signal output by the infrared lock-in thermal imaging device with the electromagnetic interference signal, inject the synchronized interference signal into the to-be-tested chip, and acquire an infrared lock-in thermal spot distribution map of the to-be-tested chip in the preset working mode through the infrared lock-in thermal imaging device;

[0041] According to the infrared lock-in thermal spot distribution map, determine the internal interference test result of the to-be-tested chip in the preset working mode, and the internal interference test result includes a coupling path test result and a sensitive unit test result.

[0042] The chip internal conduction interference coupling path test method, system, computer device, computer readable storage medium, and computer program product, by powering on the to-be-tested chip placed in the infrared lock-in thermal imaging device, and controlling the to-be-tested chip to enter a preset working mode, synchronizing the voltage excitation signal output by the infrared lock-in thermal imaging device with the electromagnetic interference signal, injecting the synchronized interference signal into the to-be-tested chip, can accurately control the frequency, phase, and intensity of the interference signal, avoid interference errors caused by asynchronous signals, and make the interference test result more repeatable and reliable. Through the infrared lock-in thermal imaging device, an infrared lock-in thermal spot distribution map of the to-be-tested chip in the preset working mode is acquired, the lock-in amplification effect of the infrared lock-in thermal imaging device is used to filter out background noise, which is conducive to extracting thermal response characteristics related to the interference signal and realizing high-resolution capture of the internal thermal interference effect of the chip. The infrared lock-in thermal spot distribution map can directly display the conduction path and abnormal temperature rise area of the interference signal in the chip. According to the infrared lock-in thermal spot distribution map, the internal interference test result of the to-be-tested chip in the preset working mode is determined, and the internal interference test result includes a coupling path test result and a sensitive unit test result. This thermal-electric collaborative detection method that fuses infrared thermal imaging and conduction interference immunity test realizes high-precision, visual positioning and analysis of the chip internal conduction interference coupling path and the chip sensitive unit. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the drawings needed to be used in the description of the embodiments of the present application or the related art will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other related drawings without creative labor.

[0044] Figure 1 An application environment diagram of the chip internal conduction interference coupling path test method in one embodiment;

[0045] Figure 2 A flow chart of a method for testing a conducted interference coupling path inside a chip in an embodiment

[0046] Figure 3 A schematic diagram of an amplitude distribution in some embodiments of an embodiment Figure 1

[0047] Figure 4 A schematic diagram of an amplitude distribution in some embodiments of an embodiment Figure 2

[0048] Figure 5 A schematic diagram of an amplitude distribution in some embodiments of an embodiment Figure 3

[0049] Figure 6 A schematic diagram of a phase distribution in some embodiments of an embodiment

[0050] Figure 7 A schematic diagram of a reference amplitude graph in some embodiments of an embodiment

[0051] Figure 8 An internal structure diagram of a computer device in an embodiment DETAILED DESCRIPTION

[0052] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0053] It should be noted that the terms "first", "second" and the like used in the present application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "include" and "have" and any variations thereof used in the present application are intended to cover non-exclusive inclusion. The term "a plurality of" used in the present application means two or more. The term "and / or" used in the present application means one of the options or any combination of a plurality of options.

[0054] The chip internal conducted interference coupling path test method provided by the embodiments of the present application can be applied to, for example Figure 1 ​​​The application environment is shown. Among them, the chip internal conduction interference coupling path test system 100 includes: a chip under test 101, an infrared phase-locked thermal imaging device 102, an electromagnetic interference source 103, a signal synchronization device 104, a power supply 105 and a computer device 106. The infrared phase-locked thermal imaging device 102 is used to obtain the infrared phase-locked thermal spot distribution map of the chip under test 101 placed in the infrared phase-locked thermal imaging device 102; the electromagnetic interference source 103 is connected with the chip under test 101, and is used to output an electromagnetic interference signal; the signal synchronization device 104 is used to synchronize the voltage excitation signal output by the infrared phase-locked thermal imaging device 102 with the electromagnetic interference signal, so that the synchronized interference signal is injected into the chip under test 101; the power supply 105 is used to power on the chip under test 101; the computer device 106 is used to control the power supply 105 to power on the chip under test 101, and control the chip under test 101 to enter a preset working mode; the voltage excitation signal output by the infrared phase-locked thermal imaging device 102 is synchronized with the electromagnetic interference signal output by the electromagnetic interference source 103, the synchronized interference signal is injected into the chip under test 101, and the infrared phase-locked thermal spot distribution map of the chip under test 101 in the preset working mode is obtained through the infrared phase-locked thermal imaging device 102; according to the infrared phase-locked thermal spot distribution map, the internal interference test result of the chip under test 101 in the preset working mode is determined, and the internal interference test result includes the coupling path test result and the sensitive unit test result. In some embodiments, the chip internal conduction interference coupling path test system 100 further includes a state monitoring device 107, which is used to monitor the working state of the chip under test 101, and judge whether the chip under test 101 fails in the disturbed state or not. The computer device 106 can be connected with the chip under test 101, the infrared phase-locked thermal imaging device 102, the electromagnetic interference source 103, the signal synchronization device 104, the power supply 105 and the state monitoring device 107 respectively.

[0055] In an exemplary embodiment, as shown in Figure 2 , a chip internal conduction interference coupling path test method is provided, which is applied to the chip internal conduction interference coupling path test system 100 in Figure 1 for example, including the following steps 202 to 206. Among them:

[0056] Step 202, power on the chip under test placed in the infrared phase-locked thermal imaging device, and control the chip under test to enter a preset working mode.

[0057] The to-be-tested chip refers to a chip that needs to be tested for internal conduction interference coupling paths. The infrared phase-locked thermal imaging device is a high-sensitivity thermal detection device combining infrared thermal imaging and phase-locked amplification technology. By applying a periodic thermal excitation to the to-be-tested chip, a thermal response signal of the same frequency as the excitation signal is extracted using phase-locked technology to suppress background noise, and high-resolution thermal distribution detection is achieved.

[0058] In some embodiments, the to-be-tested chip needs to be opened and the opened sample is welded to the test board. The test board is placed in the infrared phase-locked thermal imaging device, and the test board is powered on through the connected power supply.

[0059] The preset working mode refers to the running state of the chip that is set in advance according to the test requirements. The to-be-tested chip is connected to the computer device, and the running state of the to-be-tested chip is controlled through the computer device. The preset working mode can also be a combination of multiple running states, such as a combination of any one or more of parameters such as power consumption mode (such as high load, low power consumption), clock frequency, data throughput, and working temperature range.

[0060] The to-be-tested chip can be in different working modes. The sensitive units and coupling paths inside the to-be-tested chip can be different in different working modes. Therefore, the computer device controls the to-be-tested chip to work in the preset working mode, so as to detect the to-be-tested chip in the preset working mode. Exemplarily, the to-be-tested chip is a CAN bus chip, and the preset working mode can include normal mode, sleep mode, etc. The preset working mode can be selected according to the test requirements.

[0061] In step 204, the voltage excitation signal output by the infrared phase-locked thermal imaging device is synchronized with the electromagnetic interference signal, the synchronized interference signal is injected into the to-be-tested chip, and the infrared phase-locked thermal spot distribution map of the to-be-tested chip in the preset working mode is obtained through the infrared phase-locked thermal imaging device.

[0062] The voltage excitation signal refers to a periodic voltage signal generated by the infrared phase-locked thermal imaging device, which is used to apply controllable thermal excitation to the to-be-tested chip. By changing the voltage amplitude, frequency, and other parameters, periodic power consumption changes can be generated inside the chip, and then detectable thermal signals can be generated.

[0063] The electromagnetic interference signal refers to an electromagnetic signal output by an electromagnetic interference source, which covers different frequencies, intensities, and waveforms (such as sine wave, pulse wave), and is used to simulate the interference that the chip may suffer in a complex electromagnetic environment. Different electromagnetic interference sources may be used for different conduction anti-interference test projects. The electromagnetic interference source can include a radio frequency signal generator, an electric fast transient burst generator, a surge generator, etc. Through the coupling / decoupling network of the test board, the electromagnetic interference signal can be injected into the power supply, ground, and I / O port of the to-be-tested chip in time-sharing or simultaneously.

[0064] Signal synchronization refers to keeping the voltage excitation signal and the electromagnetic interference signal consistent or in a specific corresponding relationship in frequency and phase through a signal synchronization device to realize the output of the phase-controllable electromagnetic interference signal. Exemplarily, the signal synchronization device can be a device using phase locking, timing calibration, etc.

[0065] The synchronized interference signal is the signal after the signal synchronization processing of the electromagnetic interference signal.

[0066] The infrared phase-locked hot spot distribution diagram refers to the image output by the infrared phase-locked thermal imaging device. The infrared phase-locked hot spot distribution diagram directly shows the thermal response distribution of each region on the surface of the to-be-tested chip. The infrared phase-locked hot spot distribution diagram can include an amplitude distribution diagram and a phase distribution diagram. Exemplarily, the infrared phase-locked hot spot distribution diagram can be displayed as a pseudo-color image, different colors correspond to different thermal signal intensities or phase values, and quantitative analysis of the thermal distribution is supported. For example, Figure 3 , for example, Figure 4 , for example, Figure 5 The amplitude distribution diagram in some embodiments is shown in FIG. 1. Wherein, Figure 3 is the amplitude distribution diagram generated after a 100 MHz, 0 dbm radio frequency interference signal is injected into the to-be-tested chip, Figure 4 is the amplitude distribution diagram generated after a 1 GHz, 0 dbm radio frequency interference signal is injected into the to-be-tested chip, Figure 5 is the amplitude distribution diagram generated after a 2 GHz, 0 dbm radio frequency interference signal is injected into the to-be-tested chip.

[0067] Step 206, according to the infrared phase-locked hot spot distribution diagram, determine the internal interference test result of the to-be-tested chip in the preset working mode, the internal interference test result includes the coupling path test result and the sensitive unit test result.

[0068] Since the infrared phase-locked hot spot distribution diagram shows the thermal response distribution of each region on the surface of the to-be-tested chip, according to the infrared phase-locked hot spot distribution diagram, the internal interference test result of the to-be-tested chip in the preset working mode can be determined to quantify the influence of the electromagnetic interference signal on the to-be-tested chip.

[0069] The internal interference test result includes the coupling path test result and the sensitive unit test result, the coupling path test result indicates the transmission path of the electromagnetic interference signal in the to-be-tested chip, for example, the transmission track through the metal wire, the substrate, or the packaging material. In some embodiments, the path of the signal extension can be determined as the coupling path from the interference injection point of the infrared phase-locked hot spot distribution diagram, that is, the coupling path test result.

[0070] The sensitive unit test result indicates an internal device or circuit module in the chip under test that is sensitive to the electromagnetic interference signal. In some embodiments, an abnormally high temperature region can be determined from the infrared phase-locked hotspot distribution map, thereby determining the sensitive unit in the chip under test, and serving as the sensitive unit test result.

[0071] In the above-mentioned chip internal conduction interference coupling path test method, the chip under test is powered on in the infrared phase-locked thermal imaging device, and the chip under test is controlled to enter a preset working mode. The voltage excitation signal output by the infrared phase-locked thermal imaging device is synchronized with the electromagnetic interference signal, and the synchronized interference signal is injected into the chip under test. The frequency, phase and intensity of the interference signal can be accurately controlled, the interference error caused by asynchronous signals is avoided, and the interference test result is more repeatable and reliable. The infrared phase-locked thermal imaging device is used to obtain the infrared phase-locked hotspot distribution map of the chip under test in the preset working mode. The phase-locked amplification effect of the infrared phase-locked thermal imaging device filters out background noise, which is beneficial to extract the thermal response characteristics related to the interference signal, and realizes high-resolution capture of the internal thermal interference effect of the chip. The infrared phase-locked hotspot distribution map can directly display the conduction path and abnormal temperature rise region of the interference signal inside the chip. According to the infrared phase-locked hotspot distribution map, the internal interference test result of the chip under test in the preset working mode is determined. The internal interference test result includes the coupling path test result and the sensitive unit test result. This thermal-electric cooperative detection method by fusing infrared thermal imaging and conduction interference immunity test realizes high-precision, visual positioning and analysis of the chip internal conduction interference coupling path and the chip sensitive unit.

[0072] In one exemplary embodiment, according to the infrared phase-locked hotspot distribution map, the internal interference test result of the chip under test in the preset working mode is determined, including: obtaining a reference infrared phase-locked map of the chip under test in the preset working mode; and determining the internal interference test result of the chip under test in the preset working mode according to the reference infrared phase-locked map and the infrared phase-locked hotspot distribution map.

[0073] The reference infrared phase-locked map refers to a thermal distribution reference image obtained by the infrared phase-locked thermal imaging device when the chip under test is in the preset working mode and no external electromagnetic interference is applied, reflecting the thermal response of the chip under test in the normal working state.

[0074] The reference infrared phase-locked map is used as a reference to compare and analyze the thermal distribution changes of the chip under test after interference injection, thereby identifying the thermal response difference caused by interference injection.

[0075] In some embodiments, the reference infrared phase-locked map and the infrared phase-locked hotspot distribution map need to be collected under the same optical resolution and thermal sensitivity conditions.

[0076] In the embodiment, the reference infrared lock-in image is a thermal distribution map of the to-be-tested chip without interference injection, and by comparing the reference infrared lock-in image and the infrared lock-in hot spot distribution map, subtle changes in the heat conduction path are identified, which is conducive to high-precision, visual positioning and analysis of the internal conduction interference coupling path of the to-be-tested chip and the sensitive unit of the chip.

[0077] In an exemplary embodiment, the reference infrared lock-in image includes a reference amplitude map, and the infrared lock-in hot spot distribution map includes an amplitude distribution map; and the internal interference test result of the to-be-tested chip under the preset working mode is determined according to the reference infrared lock-in image and the infrared lock-in hot spot distribution map, including: in the case that there is a continuously distributed abnormal high temperature region in the amplitude distribution map, the amplitude conditions of the reference amplitude map and the amplitude distribution map in the abnormal high temperature region and the injection conditions of the radio frequency interference injection point are determined; in the case that the amplitude conditions indicate that the amplitude increment at more than a preset number of pixel points reaches a preset threshold, the injection conditions indicate that the radio frequency interference injection point is located within the abnormal high temperature region, and extends along the circuit wiring direction or the power ground plane, it is determined that the abnormal high temperature region is a radio frequency interference conduction coupling path of the to-be-tested chip under the preset working mode; in the case that there is a module unit with an amplitude increment exceeding a preset threshold in the amplitude distribution map, a topological difference evaluation result between the reference amplitude map and the amplitude distribution map is determined; and in the case that the topological difference evaluation result exceeds a preset value, the module unit is determined to be a sensitive unit of the to-be-tested chip under the preset working mode.

[0078] In the embodiment, the reference infrared lock-in image includes a reference amplitude map and a reference phase map, and the infrared lock-in hot spot distribution map includes an amplitude distribution map and a phase distribution map.

[0079] The abnormal high temperature region refers to a region in the amplitude distribution map that is significantly higher in temperature than the surrounding region and is continuously distributed. For example, a region in the amplitude distribution map that has a temperature difference exceeding a preset temperature difference from the surrounding region and is continuously distributed can be determined as an abnormal high temperature region.

[0080] The radio frequency interference injection point refers to a specific position where the electromagnetic interference source injects the synchronized interference signal into the to-be-tested chip, for example, a chip power supply, a ground wire, and an I / O port.

[0081] The coupling path is generally manifested as a hotspot spreading along a line or a plane from an interference injection point. The RFI conduction coupling path refers to a physical path through which an RF signal is transmitted from an RF injection point to other regions inside a chip, possibly through metal wiring, parasitic capacitance, electromagnetic induction, etc. Determining the path helps to understand the propagation law of the interference and provides a direction for suppressing the interference. When the amplitude increment of an abnormal high-temperature region, the RF injection point position, and the conduction direction all meet certain conditions, the abnormal high-temperature region can be determined as the RF conduction coupling path, i.e., the coupling path test result.

[0082] The sensitive unit of the chip under test refers to a functional module that is prone to abnormal response or performance degradation under the action of RF interference. When the chip under test is subjected to RF interference, the sensitive unit will exhibit abnormal hotspot characteristics. The topology difference evaluation result refers to a comparative analysis of the thermal signal distribution topology of the module unit in the reference amplitude map and the amplitude distribution map, and a numerical result reflecting the difference between the two. The evaluation method includes calculating the amplitude difference, the change of hotspot distribution, etc. When the amplitude increment of the module unit and the topology difference evaluation result both meet certain conditions, the module unit can be determined as the sensitive unit of the chip under test, i.e., the sensitive unit test result.

[0083] In this embodiment, by comparing the reference amplitude map and the amplitude distribution map, and combining the RF injection point and the conduction direction, the conduction coupling path of the interference inside the chip can be quickly and accurately determined, blind troubleshooting is avoided, and the fault diagnosis time is greatly shortened. According to the topology difference evaluation result, the chip module unit sensitive to RF interference can be accurately identified.

[0084] In one exemplary embodiment, the reference infrared lock-in map includes a reference phase map; the infrared lock-in hotspot distribution map includes a phase distribution map; and the internal interference test result of the chip under test in the preset working mode is determined according to the reference infrared lock-in map and the infrared lock-in hotspot distribution map, including: in the case that there is a continuously distributed closed region in the phase distribution map, the phase delay value of the reference phase map and the phase distribution map in the closed region and the injection condition of the RF injection point are determined; in the case that the deviation of the phase delay value exceeds a preset deviation, and the injection condition indicates that the RF injection point is located in the closed region and extends along the circuit wiring direction or the power ground plane, the closed region is determined as the RF conduction coupling path of the chip under test in the preset working mode; in the case that there is a module unit with a phase change exceeding a preset change in the phase distribution map, the topology difference evaluation result between the reference phase map and the phase distribution map is determined; and in the case that the topology difference evaluation result exceeds a preset value, the module unit is determined as the sensitive unit of the chip under test in the preset working mode.

[0085] For example, the reference infrared lock-in image includes a reference phase image, and the infrared lock-in hotspot distribution image includes a phase distribution image. Figure 6 FIG. 4 shows a schematic diagram of a phase distribution image in some embodiments.

[0086] The closed region refers to a region in the phase distribution image in which the phase delay of the thermal signal presents continuous change and forms a closed boundary. The radio frequency interference injection point refers to a specific location at which the electromagnetic interference source injects the synchronized interference signal into the chip under test, such as a chip power supply, a ground wire, and an I / O port. The phase delay value reflects the time required for the heat conduction of the interference signal from the radio frequency interference injection point to the detection point, and can be used to analyze the heat conduction path and efficiency. The deviation of the phase delay value refers to the difference between the phase delay value of the reference phase image in the closed region and the phase delay value of the phase distribution image in the closed region.

[0087] The radio frequency interference conduction coupling path helps to understand the propagation law of the radio frequency interference and provides a direction for suppressing the interference. When the deviation of the phase delay value in the closed region, the radio frequency interference injection point location, and the conduction direction all satisfy certain conditions, the closed region can be determined as the radio frequency interference conduction coupling path, i.e., the coupling path test result.

[0088] The topology difference evaluation result refers to the comparative analysis of the thermal signal distribution topologies of the module units in the reference phase image and the phase distribution image, and the numerical result obtained for reflecting the difference between the two. The evaluation method includes calculating the phase delay change, the phase distribution shape change, and other indicators. When the phase change of the module unit and the topology difference evaluation result both satisfy certain conditions, the module unit can be determined as the sensitive unit of the chip under test, i.e., the sensitive unit test result.

[0089] In this embodiment, by using the continuous closed region in the phase distribution image, combining the phase delay value deviation and the radio frequency interference injection point information, the conduction coupling path of the radio frequency interference inside the chip can be accurately located, blind troubleshooting can be avoided, and the fault diagnosis time can be greatly shortened; by comparing the reference phase image and the phase distribution image, according to the topology difference evaluation result, the chip module unit sensitive to the radio frequency interference can be accurately identified.

[0090] In one exemplary embodiment, the obtaining step of the reference infrared lock-in image includes: powering on the chip under test placed in the infrared lock-in thermal imaging device, and controlling the chip under test to enter a preset working mode; and obtaining, by the infrared lock-in thermal imaging device, a reference amplitude image or a reference phase image of the chip under test in the preset working mode, and taking the reference amplitude image or the reference phase image as the reference infrared lock-in image.

[0091] In this embodiment, the reference infrared lock-in image of the chip under test is recorded by the infrared lock-in thermal imaging device when the chip under test is powered on and in the preset working mode. The reference infrared lock-in image includes at least one of the reference amplitude image or the reference phase image.

[0092] The reference amplitude map is used to reflect the temperature distribution of each region of the to-be-tested chip in a normal working state. Figure 7 Fig. 2 shows a schematic diagram of a reference amplitude map in some embodiments.

[0093] The reference phase map is used to reflect the phase distribution of each region of the to-be-tested information in a normal working state. The phase reflects the time delay characteristic of heat conduction, and can be used to analyze the heat conduction path and efficiency.

[0094] In this embodiment, the to-be-tested chip is controlled to be in a preset working mode to simulate the actual application scenario of the to-be-tested chip, so that the test result is closer to the real use condition. Meanwhile, the acquisition of the reference infrared phase-locked map can provide a unified standard for multiple tests or comparison of different chips, and ensure the horizontal comparability of data.

[0095] In one exemplary embodiment, the voltage excitation signal output by the infrared phase-locked thermal imaging device is signal-synchronized with the electromagnetic interference signal, including: according to the phase of the voltage excitation signal output by the infrared phase-locked thermal imaging device, adjusting the phase offset of the electromagnetic interference signal by using a signal synchronization device to obtain a synchronized interference signal.

[0096] The signal synchronization device can obtain the synchronized interference signal by adjusting the phase offset of the electromagnetic interference signal. The synchronized interference signal and the voltage excitation signal maintain a fixed phase relationship, and the phase-controllable electromagnetic interference signal output is realized.

[0097] In this embodiment, through signal synchronization, the sampling window of infrared thermal imaging and the pulse rising edge / falling edge of the electromagnetic interference signal can be completely aligned, and the time misalignment of the thermal distribution map and the radio frequency interference response caused by time sequence deviation can be avoided.

[0098] To describe the chip internal conduction interference coupling path test method in this scheme in detail, a most detailed embodiment is described below:

[0099] The chip internal conduction interference coupling path test method is applied to a chip internal conduction interference coupling path test system. The system includes a to-be-tested chip, an infrared phase-locked thermal imaging device, an electromagnetic interference source, a signal synchronization device, a power supply, a state monitoring device, and a computer device.

[0100] Infrared phase-locked thermal imaging device: (for example, temperature measurement range 0 ℃~300 Celsius, temperature resolution 0.01 ℃, phase-locked frequency 0.03 Hz~30 Hz, can output periodic voltage excitation signal), using phase-locked amplification technology to extract the periodic temperature rise signal caused by the periodic radio frequency interference on the surface and inside of the chip to be tested, and to locate the electromagnetic conduction interference coupling path and the chip sensitive unit. Electromagnetic interference source: used to generate electromagnetic interference signals, different interference sources are used for different conduction immunity test projects, and the interference source can be: radio frequency signal generator, electric fast transient burst generator, surge generator, etc. Through the coupling / decoupling network of the test board, the interference signal is injected into the chip power supply, ground and I / O port in time sharing or simultaneously. Signal synchronization device: used to adjust the amplitude, phase and rise time of the periodic voltage excitation signal output by the infrared phase-locked thermal imaging device, so as to synchronize the infrared phase-locked thermal imaging device with the interference source using the adjusted pulse signal to realize the output of phase-controllable electromagnetic interference signal. State monitoring device: used to monitor the working state of the chip and judge whether the chip fails under the disturbed state. Power supply: 0.3V~24V, 0.1~3A, used to apply external voltage to the chip to be tested to simulate the working state of the chip under voltage. Computer equipment: used to program and control the functions of the test system and the chip to be tested, and to display the real-time running conditions of various devices and to carry out data analysis of test results.

[0101] The chip internal conduction interference coupling path test method specifically includes the following steps:

[0102] (1) The sample to be tested is opened and treated, and the opened sample is welded to the test board;

[0103] (2) The test board is placed in the infrared phase-locked thermal imaging device and connected with the power supply and the electromagnetic interference source;

[0104] (3) The periodic voltage excitation signal output by the infrared phase-locked thermal imaging device is synchronized with the electromagnetic interference source through the signal synchronization device;

[0105] (4) The chip to be tested is powered on, the working state of the chip to be tested is controlled by the computer equipment, the working state of the chip to be tested is monitored by the signal monitoring device, and the reference infrared phase-locked diagram of the chip to be tested in the normal working state is obtained by the infrared phase-locked thermal imaging device, including the reference amplitude diagram and the reference phase diagram;

[0106] (5) The output frequency and amplitude of the radio frequency interference source are set, the synchronized interference signal is injected into the chip to be tested through the coaxial cable and the radio frequency connector, and the infrared phase-locked thermal imaging device is used to obtain the infrared phase-locked hot spot distribution diagram of the chip to be tested under electromagnetic interference, including the amplitude distribution diagram and the phase distribution diagram;

[0107] (6) Comparing the amplitude distribution diagram or the phase distribution diagram of the to-be-tested chip under the normal working state and the disturbed state, analyzing the coupling path of electromagnetic interference in the to-be-tested chip and the sensitive unit of the to-be-tested chip.

[0108] The above-mentioned chip internal conduction interference coupling path test method can precisely control the frequency, phase and intensity of the interference signal by powering the to-be-tested chip placed in the infrared phase-locked thermal imaging device, controlling the to-be-tested chip to enter a preset working mode, synchronizing the voltage excitation signal and the electromagnetic interference signal output by the infrared phase-locked thermal imaging device, injecting the synchronized interference signal into the to-be-tested chip, avoiding interference errors caused by asynchronous signals, and making the interference test results more repeatable and reliable. The infrared phase-locked thermal imaging device is used to obtain the infrared phase-locked thermal spot distribution diagram of the to-be-tested chip under the preset working mode, the phase-locked amplification effect of the infrared phase-locked thermal imaging device is used to filter out background noise, which is conducive to extracting thermal response characteristics related to the interference signal and realizing high-resolution capture of the internal thermal interference effect of the chip. The infrared phase-locked thermal spot distribution diagram can directly display the conduction path and abnormal temperature rise area of the interference signal in the chip. According to the infrared phase-locked thermal spot distribution diagram, the internal interference test result of the to-be-tested chip under the preset working mode is determined. The internal interference test result includes the coupling path test result and the sensitive unit test result. This thermal-electric cooperative detection method that combines infrared thermal imaging and conduction interference immunity test realizes high-precision, visual positioning and analysis of the chip internal conduction interference coupling path and the chip sensitive unit. In addition, the infrared phase-locked thermal imaging device and the electromagnetic interference source are integrated to realize thermal-electric dual-physical-field synchronous detection of the chip internal conduction interference coupling path. The precise phase control of the signal synchronization device ensures that the sampling window of the infrared thermal imaging and the pulse rising edge / falling edge of the electromagnetic interference signal are completely aligned, avoiding the time misalignment of the thermal distribution diagram and the radio frequency interference response caused by time sequence deviation. The internal coupling path and the sensitive unit are precisely positioned through thermal-electric dual-field comparative analysis (thermal spot distribution diagram under normal and disturbed states). This method breaks through the limitation of traditional electromagnetic compatibility test methods that cannot locate the chip internal coupling path and the chip sensitive unit, and uses the spatial resolution capability of infrared thermal imaging to visualize the local temperature rise and energy dissipation caused by interference.

[0109] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are shown in sequence according to the arrows, the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the execution of the steps is not strictly limited in sequence, and the steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts involved in the above-described embodiments can include multiple steps or multiple stages, which are not necessarily executed at the same time but can be executed at different times, and the execution of the steps or stages is not necessarily sequential but can be performed alternately or alternately with at least some of the other steps or steps or stages in other steps. It can be understood that the steps in different embodiments can be freely combined as needed, and various non-contradictory schemes formed by the combination are within the scope of protection of the present application.

[0110] In an exemplary embodiment, a computer device, which can be a terminal, has an internal structure diagram as shown in Figure 8 The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. The processor, the memory, and the input / output interface are connected through a system bus, and the communication interface, the display unit, and the input device are connected to the system bus through the input / output interface. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The input / output interface of the computer device is configured to exchange information between the processor and external devices. The communication interface of the computer device is configured to communicate with external terminals in a wired or wireless manner. The wireless manner can be achieved through WIFI, mobile cellular network, Near Field Communication (NFC), or other technologies. The computer program is executed by the processor to implement a chip internal conduction interference coupling path test method. The display unit of the computer device is configured to form a visually visible picture, which can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer overlaid on the display screen, or can be a key, trackball, or touchpad arranged on the shell of the computer device, or can be an external keyboard, touchpad, or mouse, etc.

[0111] Those skilled in the art can understand, Figure 8The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0112] In an exemplary embodiment, a computer device is provided, including a memory and a processor, the memory storing a computer program, and the processor implementing the steps in the above method embodiments when executing the computer program.

[0113] In an embodiment, a computer readable storage medium is provided, storing a computer program, and the computer program implementing the steps in the above method embodiments when executed by a processor.

[0114] In an embodiment, a computer program product is provided, including a computer program, and the computer program implementing the steps in the above method embodiments when executed by a processor.

[0115] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant regulations.

[0116] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when executed, can include the processes of the above-mentioned embodiment methods. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. The non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. The volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, the RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., without being limited thereto.

[0117] The technical features of the above embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present application.

[0118] The above-described embodiments are merely illustrative of several embodiments of the present application, and the description is relatively specific and detailed, but should not be understood as a limitation on the scope of the patent. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims.

Claims

1. A method of testing a conductive interference coupling path inside a chip, characterized by, The method comprises: Power on a to-be-tested chip placed in an infrared lock-in thermal imaging device, and control the to-be-tested chip to enter a preset working mode; Synchronize a voltage excitation signal output by the infrared lock-in thermal imaging device with an electromagnetic interference signal, inject the synchronized interference signal into the to-be-tested chip, and acquire an infrared lock-in thermal spot distribution map of the to-be-tested chip in the preset working mode through the infrared lock-in thermal imaging device; Determine an internal interference test result of the to-be-tested chip in the preset working mode according to the infrared lock-in thermal spot distribution map, wherein the internal interference test result comprises a coupling path test result and a sensitive unit test result.

2. The method of claim 1, wherein, The method comprises: Acquire a reference infrared lock-in map of the to-be-tested chip in the preset working mode; Determine the internal interference test result of the to-be-tested chip in the preset working mode according to the reference infrared lock-in map and the infrared lock-in thermal spot distribution map.

3. The method of claim 2, wherein, The reference infrared lock-in map comprises a reference amplitude map; the infrared lock-in thermal spot distribution map comprises an amplitude distribution map; and the method comprises: In a case where there is a continuously distributed abnormally high temperature region in the amplitude distribution map, determine an amplitude condition of the abnormally high temperature region in the reference amplitude map and the amplitude distribution map respectively and an injection condition of a radio frequency interference injection point, and in a case where the amplitude condition indicates that an amplitude increment at a preset number of pixel points reaches a preset threshold value, the injection condition indicates that the radio frequency interference injection point is located in the abnormally high temperature region and extends along a circuit wiring direction or a power ground plane, determine that the abnormally high temperature region is a radio frequency interference conduction coupling path of the to-be-tested chip in the preset working mode; In a case where there is a module unit with an amplitude increment exceeding a preset threshold value in the amplitude distribution map, determine a topological difference evaluation result between the reference amplitude map and the amplitude distribution map; and in a case where the topological difference evaluation result exceeds a preset value, determine that the module unit is a sensitive unit of the to-be-tested chip in the preset working mode.

4. The method of claim 2, wherein, The reference infrared lock-in map comprises a reference phase map; the infrared lock-in thermal spot distribution map comprises a phase distribution map; and the method comprises: In a case where there is a closed region with continuous distribution in the phase distribution map, phase delay values of the reference phase map and the phase distribution map in the closed region and injection conditions of radio frequency interference injection points are determined, in a case where deviation of the phase delay values exceeds a preset deviation and the injection conditions indicate that the radio frequency interference injection points are located within the closed region and extend along a circuit wiring direction or a power ground plane, the closed region is determined as a radio frequency interference conducted coupling path of the chip under test in a preset working mode; In a case where there is a module unit with phase variation exceeding a preset variation amount in the phase distribution map, a topological difference evaluation result between the reference phase map and the phase distribution map is determined, and in a case where the topological difference evaluation result exceeds a preset value, the module unit is determined as a sensitive unit of the chip under test in a preset working mode.

5. The method of claim 2, wherein, The reference infrared lock-in phase map is obtained by: powering on the chip under test placed in the infrared lock-in thermal imaging device, and controlling the chip under test to enter a preset working mode; obtaining a reference amplitude map or a reference phase map of the chip under test in the preset working mode by the infrared lock-in thermal imaging device, and taking the reference amplitude map or the reference phase map as the reference infrared lock-in phase map.

6. The method of claim 1, wherein, The signal synchronization between the voltage excitation signal output by the infrared lock-in thermal imaging device and the electromagnetic interference signal includes: adjusting the phase offset of the electromagnetic interference signal by a signal synchronization device according to the phase of the voltage excitation signal output by the infrared lock-in thermal imaging device to obtain a synchronized interference signal.

7. An on-chip conducted interference coupling path test system, comprising: The system includes: a chip under test; an infrared lock-in thermal imaging device for obtaining an infrared lock-in thermal point distribution map of the chip under test placed in the infrared lock-in thermal imaging device; an electromagnetic interference source connected to the chip under test for outputting an electromagnetic interference signal; a signal synchronization device for synchronizing the voltage excitation signal output by the infrared lock-in thermal imaging device with the electromagnetic interference signal so that the synchronized interference signal is injected into the chip under test; a power supply for powering on the chip under test; a computer device for controlling the power supply to power on the chip under test and controlling the chip under test to enter a preset working mode; synchronizing the voltage excitation signal output by the infrared lock-in thermal imaging device with the electromagnetic interference signal, injecting the synchronized interference signal into the chip under test, and obtaining an infrared lock-in thermal point distribution map of the chip under test in the preset working mode by the infrared lock-in thermal imaging device; determining an internal interference test result of the chip under test in the preset working mode according to the infrared lock-in thermal point distribution map, wherein the internal interference test result includes a coupling path test result and a sensitive unit test result.

8. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that, The processor executes the computer program to implement the steps of the method of any one of claims 1 to 6.

9. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method of any one of claims 1 to 6.

10. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method of any one of claims 1 to 6.

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