Operational amplifier for operational amplifier shared high-speed pipeline analog-to-digital converter
By employing a combination of a first main operational amplifier and a second main operational amplifier in a pipelined analog-to-digital converter, along with an adaptive bias circuit and a compensation capacitor, the contradiction between high precision and high-speed performance of operational amplifiers is resolved, achieving a high-gain, wide-bandwidth, and low-power operational amplifier design.
Patent Information
- Application Number
- CN202511125990.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-12
- Publication Date
- 2025-12-05
AI Technical Summary
In traditional pipelined analog-to-digital converters, the design of operational amplifiers faces the challenge of balancing high precision and high-speed performance. In particular, the increase in the characteristic frequency of MOSFETs leads to a decrease in gain and an increase in parasitic capacitance, which affects bandwidth and accuracy.
A combination structure of a first main operational amplifier and a second main operational amplifier is adopted, combined with an adaptive bias circuit and a compensation capacitor. High gain and high slew rate are achieved through Cascode compensation, and a positive feedback circuit is introduced to improve closed-loop stability.
It significantly improves the accuracy and bandwidth of operational amplifiers, solves the requirements for high gain and large slew rate in high-speed, high-precision pipelined analog-to-digital converters, and overcomes the low-frequency zero problem in the right half-plane of ordinary Miller capacitor compensation schemes, thereby enhancing the stability and efficiency of operational amplifiers.
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Figure CN121077417A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of circuits, and particularly relates to an operational amplifier for sharing an operational amplifier of a high-speed pipeline analog-to-digital converter. BACKGROUND
[0002] With the development of CMOS technology, the feature size of MOS transistors is continuously reduced, and the feature frequency is continuously improved, which also leads to the continuous decrease of the intrinsic gain of MOS transistors. The operational amplifier in the sample-and-hold circuit in the pipeline analog-to-digital converter is extremely harsh, which makes the design of a high-precision high-speed pipeline ADC particularly difficult.
[0003] The conventional pipeline analog-to-digital converter sample-and-hold operational amplifier and each stage of residual operational amplifier are usually implemented by using a closed-loop high-performance amplifier. This structure improves the output impedance and the open-loop gain by adding an auxiliary operational amplifier, but the added auxiliary operational amplifier introduces new parasitic capacitances, thereby increasing the poles and reducing the bandwidth of the entire operational amplifier. The bandwidth of the comparator, the noise on the sampling capacitance, and the load capacitance of each stage all affect the precision of the pipeline. SUMMARY
[0004] In order to solve the above problems in the prior art, the application provides an operational amplifier for sharing an operational amplifier of a high-speed pipeline analog-to-digital converter.
[0005] The technical problem to be solved by the application is solved by the following technical scheme: An operational amplifier for sharing an operational amplifier of a high-speed pipeline analog-to-digital converter, comprising: a first main operational amplifier, a second main operational amplifier, and an adaptive biasing circuit. The input end of the first main operational amplifier receives an input signal, and the output end is connected to the input end of the second main operational amplifier. The output end of the second main operational amplifier outputs an amplified signal, and is connected to the Cascode node of the first main operational amplifier through a pair of compensation capacitors. The first main operational amplifier is a folded common-source and common-gate amplifier, and the adaptive biasing circuit provides direct current biasing for the tail current source and common-gate transistor of the first main operational amplifier.
[0006] Optionally, the adaptive biasing circuit comprises a positive feedback circuit and an auxiliary operational amplifier. The first main operational amplifier comprises: a first tail current P-type transistor MP5, a first channel switching P-type transistor MP6, a second channel switching P-type transistor MP7, a first common source P-type transistor pair MP1 and MP2, a second common source P-type transistor pair MP3 and MP4, a first tail current N-type transistor pair MN1 and MN2, a first common source common gate N-type transistor pair MN3 and MN4, a first common source common gate P-type transistor pair MP8 and MP9, and a second common source common gate P-type transistor pair MP 10 , 11 ; The source of the first tail current P-type transistor MP5 is connected to a power supply voltage, and the gate is connected to a first bias voltage; the sources of the first channel switching P-type transistor MP6 and the second channel switching P-type transistor MP7 and the drain of the first tail current P-type transistor MP5 are connected; the gate of the first channel switching P-type transistor MP6 is connected to a first clock, and the gate of the second channel switching P-type transistor MP7 is connected to a second clock; the first clock and the second clock are two-phase non-overlapping clocks provided by the analog-to-digital converter; the drain of the first channel switching P-type transistor MP6 is connected to the sources of the first common source P-type transistor pair MP1 and MP2; the drain of the second channel switching P-type transistor MP7 is connected to the sources of the second common source P-type transistor pair MP3 and MP4; the gates of the first common source P-type transistor pair MP1 and MP2 and the second common source P-type transistor pair MP3 and MP4 are connected to a four-way input signal; the drains of the first common source P-type transistor pair MP1 and MP2, the drains of the first tail current N-type transistor pair MN1 and MN2, and the sources of the first common source common gate N-type transistor pair MN3 and MN4 are connected in correspondence, forming two Cascode nodes, and the two Cascode nodes are connected to the positive feedback circuit; the gates of the first tail current N-type transistor pair MN1 and MN2 are connected to a fourth bias voltage, and the sources are connected to ground; the gates of the first common source common gate N-type transistor pair MN3 and MN4 are connected to a third bias voltage, and the drains are connected in correspondence to the drains of the second common source common gate P-type transistor pair MP 10 , 11 , which constitute two output terminals of the first operational amplifier, and the two output terminals are connected to the positive feedback circuit; the gates of the second common source common gate P-type transistor pair MP 10 , 11 are connected to the input of the auxiliary operational amplifier, and the output of the auxiliary operational amplifier is connected to the sources of the second common source common gate P-type transistor pair MP 10 , 11 and the drains of the first common source common gate P-type transistor pair MP8 and MP9; the sources of the first common source common gate P-type transistor pair MP8 and MP9 are connected to a power supply voltage, and the gates are connected to a first bias voltage.
[0007] Optionally, the positive feedback circuit comprises: a first positive feedback N-type transistor pair MN6, MN7 and a second common source-gate N-type transistor pair MN5, MN8; wherein, the gates of the first positive feedback N-type transistor pair MN6, MN7 are cross-connected to the two output terminals connected to the drains of the first common source-gate N-type transistor pair MN3, MN4; the drains of the first positive feedback N-type transistor pair MN6, MN7 are connected to the two Cascode nodes connected to the sources of the first common source-gate N-type transistor pair MN3, MN4, and the sources of the first positive feedback N-type transistor pair MN6, MN7 are grounded; the gates of the second common source-gate N-type transistor pair MN5, MN8 are connected to the two output terminals connected to the drains of the first common source-gate N-type transistor pair MN3, MN4; the drains of the second common source-gate N-type transistor pair MN5, MN8 are connected to the two Cascode nodes connected to the sources of the first common source-gate N-type transistor pair MN3, MN4, and the sources of the second common source-gate N-type transistor pair MN5, MN8 are grounded.
[0008] Optionally, the second main operational amplifier comprises: a third common source-gate P-type transistor pair MP 12 , MP 13 , a fourth common source-gate P-type transistor pair MP 14 , MP 15 , and a first common source N-type transistor pair MN 10 . wherein, the gates of the first common source N-type transistor pair MN 10 are connected to the two output terminals connected to the drains of the first common source-gate N-type transistor pair MN3, MN4, the drains of the first common source N-type transistor pair MN 10 are connected to the two Cascode nodes connected to the drains of the first common source P-type transistor pair MP1, MP2 through the pair of compensation capacitors, and the sources of the first common source N-type transistor pair MN 10 are grounded; the drains of the fourth common source-gate P-type transistor pair MP 14 , MP 15 are connected to the drains of the first common source N-type transistor pair MN 10 , the gates are connected to a second bias voltage, and the sources of the fourth common source-gate P-type transistor pair MP 14 , MP 15 are connected to the drains of the third common source-gate P-type transistor pair MP 12 , MP 13 ; the drains of the third common source-gate P-type transistor pair MP 12 , MP 13The source of the fourth common-source and common-gate P-type transistor pair MP 14 , MP 15 The drain of the fourth common-source and common-gate P-type transistor pair MP 10 and the drain of the first common-source N-type transistor pair MN9, MN 12 The node connected with the drain of the fourth common-source and common-gate P-type transistor pair MP 13 and the drain of the first common-source N-type transistor pair MN9, MN 10 is the two output terminals of the operational amplifier, which output the amplification signal.
[0009] Optionally, the auxiliary operational amplifier comprises: a fifth common-source and common-gate P-type transistor pair MAP 12 , MAP 13 , a sixth common-source and common-gate P-type transistor pair MAP 10 , MAP 11 , a third common-source and common-gate N-type transistor pair MAP6, MAP7, a fourth common-source and common-gate N-type transistor pair MAP8, MAP9, a second common-source N-type transistor pair MAP1, MAP2, a fifth common-source and common-gate N-type transistor MAP4, a sixth common-source and common-gate N-type transistor MAP5, a second common-source N-type transistor pair MAP1, MAP2 and an input common-mode clamping MOS transistor MAP3. The drain of the input common-mode clamping MOS transistor MAP3, the fifth common-source and common-gate P-type transistor pair MAP 12 , MAP 13 The source of the fifth common-source and common-gate P-type transistor pair MAP 12 , MAP 13 The gate of the input common-mode clamping MOS transistor MAP3 is connected with a special bias voltage, the source of the input common-mode clamping MOS transistor MAP3, the source of the second common-source N-type transistor pair MAP1, MAP2 and the drain of the fifth common-source and common-gate N-type transistor MAP4 are connected; the gate of the second common-source N-type transistor pair MAP1, MAP2 constitutes two input ports of the auxiliary operational amplifier; the drain of the second common-source N-type transistor pair MAP1, MAP2 is cross-connected with the drain of the fifth common-source and common-gate P-type transistor pair MAP 12 , MAP 13 ; the gate of the fifth common-source and common-gate N-type transistor MAP4 is connected with a third bias voltage, and the source is connected with the drain of the sixth common-source and common-gate N-type transistor MAP5; the gate of the sixth common-source and common-gate N-type transistor MAP5 is connected with a fourth bias voltage, and the source is grounded; the gate of the fifth common-source and common-gate P-type transistor pair MAP 12 , MAP 13 is connected with a first bias voltage, and the drain is connected with the source of the sixth common-source and common-gate P-type transistor pair MAP 10 , MAP 11 ; the gate of the sixth common-source and common-gate P-type transistor pair MAP 10 , MAP 11The gate of the sixth cascode P-type transistor pair MAP10 and MAP11 is connected with a second bias voltage, and the drain is connected with the drain of the third cascode N-type transistor pair MAP6 and MAP7. 10 、MAP 11 The two nodes corresponding to the drain of the sixth cascode P-type transistor pair MAP10 and MAP11 and the drain of the fourth cascode N-type transistor pair MAP8 and MAP9 constitute two output ports of the auxiliary operational amplifier.
[0010] Optionally, the operational amplifier for sharing an operational amplifier of a high-speed pipeline analog-to-digital converter provided by the application further comprises a first switch S1 and a second switch S2. The first switch S1 is connected between the two output ends of the first main operational amplifier, and the second switch S2 is connected between the two output ends of the operational amplifier.
[0011] In the operational amplifier for sharing an operational amplifier of a high-speed pipeline analog-to-digital converter provided by the application, the first main operational amplifier is responsible for realizing high gain and high voltage slew rate, and the second main operational amplifier is responsible for realizing high output swing and further improving gain, so that the operational amplifier can normally work under closed-loop negative feedback through Cascode compensation of a compensation capacitor. Since the compensation capacitor is connected between the output end of the second main operational amplifier and the Cascode node of the first main operational amplifier instead of being connected to the output end of the first main operational amplifier, the compensation capacitor is connected to a low-impedance node, the right-half-plane zero point is moved to the left-half-plane, and the main pole is further pushed in, thereby improving the closed-loop stability of the operational amplifier. Meanwhile, an adaptive bias circuit is introduced to provide DC bias for the tail current source and the cascode transistor of the first main operational amplifier, so that the bias current can be increased when the voltage slew rate is limited to make the amplifier quickly get rid of the voltage slew rate limited time. Not only is the large voltage slew rate demand and high gain of the operational amplifier in a high-speed high-precision pipeline analog-to-digital converter solved, but also the right-half-plane low-frequency zero point problem of the ordinary Miller capacitor compensation scheme is solved, and the left-half-plane zero point is increased to increase the unit gain bandwidth, thereby significantly improving the precision of the operational amplifier.
[0012] The application will be further described in detail below with reference to the accompanying drawings and the application. BRIEF DESCRIPTION OF DRAWINGS
[0013] Figure 1 is a circuit diagram of an operational amplifier for sharing an operational amplifier of a high-speed pipeline analog-to-digital converter provided by the application. Figure 2 is Figure 1 the circuit diagram of the auxiliary operational amplifier in the operational amplifier shown in the figure; Figure 3 is a set of clock signal timing diagrams provided by the application for the operational amplifier input of the operational amplifier sharing high-speed pipeline analog-to-digital converter, which enables continuous operation at low power consumption. DETAILED DESCRIPTION
[0014] The application will be further described in detail below in combination with specific embodiments, but the embodiments of the application are not limited thereto.
[0015] In order to significantly improve the precision of the operational amplifier, the application provides an operational amplifier for the operational amplifier sharing high-speed pipeline analog-to-digital converter, comprising: a first main operational amplifier, a second main operational amplifier and an adaptive bias circuit.
[0016] Among them, the input end of the first main operational amplifier receives an input signal, and the output end is connected to the input end of the second main operational amplifier; the output end of the second main operational amplifier outputs an amplified signal, and is connected to the Cascode node of the first main operational amplifier through a pair of compensation capacitors; the first main operational amplifier is a folded common-source and common-gate amplifier, and the adaptive bias circuit provides DC bias for the tail current source and common-gate tube of the first main operational amplifier.
[0017] It can be understood that the two-stage operational amplifier structure can provide high output swing while further improving the gain, so that the overall operational amplifier can drive a larger load capacitor and provide a larger voltage swing, and has a gain of more than 90dB and a unit gain bandwidth of 800MHz.
[0018] Specifically, the adaptive bias circuit comprises a positive feedback circuit and an auxiliary operational amplifier; referring to Figure 1 , the first main operational amplifier comprises: a first tail current P-type transistor MP5, a first channel switching P-type transistor MP6, a second channel switching P-type transistor MP7, a first common-source P-type transistor pair MP1, MP2, a second common-source P-type transistor pair MP3, MP4, a first tail current N-type transistor pair MN1, MN2, a first common-source and common-gate N-type transistor pair MN3, MN4, a first common-source and common-gate P-type transistor pair MP8, MP9 and a second common-source and common-gate P-type transistor pair MP 10 , MP 11 ; Among them, the source of the first tail current P-type transistor MP5 is connected to the power supply voltage VDD, and the gate is connected to the first bias voltage V B1The source of the first channel switching P-type transistor MP6 and the second channel switching P-type transistor MP7 and the drain of the first tail current P-type transistor MP5 are connected; the gate of the first channel switching P-type transistor MP6 is connected with the first clock CLK1, and the gate of the second channel switching P-type transistor MP7 is connected with the second clock CLK2; the first clock CLK1 and the second clock CLK2 are two-phase non-overlapping clocks provided by an analog-to-digital converter; the drain of the first channel switching P-type transistor MP6 is connected with the source of the first common-source P-type transistor pair MP1, MP2; the drain of the second channel switching P-type transistor MP7 is connected with the source of the second common-source P-type transistor pair MP3, MP4; the gates of the first common-source P-type transistor pair MP1, MP2 and the second common-source P-type transistor pair MP3, MP4 are connected with the four-way input signal (V Figure 1 IN1 IN2 IP1 IP2 ); the drain of the first common-source P-type transistor pair MP1, MP2, the drain of the first tail current N-type transistor pair MN1, MN2 and the source of the first common-source common-gate N-type transistor pair MN3, MN4 are connected correspondingly, to form two Cascode nodes, and the two Cascode nodes are connected with a positive feedback circuit; the gate of the first tail current N-type transistor pair MN1, MN2 is connected with the fourth bias voltage V B4 , and the source is grounded GND; the gate of the first common-source common-gate N-type transistor pair MN3, MN4 is connected with the third bias voltage V B3 , and the drain is connected with the drain of the second common-source common-gate P-type transistor pair MP 10 , MP 11 to form two output ends V ON1 , V OP1 of the first operational amplifier, and the two output ends V ON1 , V OP1 are connected with the positive feedback circuit; the gate of the second common-source common-gate P-type transistor pair MP 10 , MP 11 is connected with the input of an auxiliary operational amplifier, and the output of the auxiliary operational amplifier is connected with the source of the second common-source common-gate P-type transistor pair MP 10 , MP 11 and the drain of the first common-source common-gate P-type transistor pair MP8, MP9; the source of the first common-source common-gate P-type transistor pair MP8, MP9 is connected with the power supply voltage VDD, and the gate is connected with the first bias voltage V B1 .
[0019] Referring to Figure 1 , the positive feedback circuit comprises: a first positive feedback N-type transistor pair MN6, MN7 and a second common-source common-gate N-type transistor pair MN5, MN8; The gate of the first positive feedback N-type transistor pair MN6, MN7 is cross-connected to two output terminals V ON1 , V OP1 of the first main operational amplifier to which the drain of the first common-source and common-gate N-type transistor pair MN3, MN4 is connected; the drain of the first positive feedback N-type transistor pair MN6, MN7 is connected to two Cascode nodes of the first main operational amplifier to which the source of the first common-source and common-gate N-type transistor pair MN3, MN4 is connected, and the source of the first positive feedback N-type transistor pair MN6, MN7 is connected to the ground GND; the gate of the second common-source and common-gate N-type transistor pair MN5, MN8 is cross-connected to two output terminals V ON1 , V OP1 of the first main operational amplifier to which the drain of the first common-source and common-gate N-type transistor pair MN3, MN4 is connected; the drain of the second common-source and common-gate N-type transistor pair MN5, MN8 is connected to two Cascode nodes of the first main operational amplifier to which the source of the first common-source and common-gate N-type transistor pair MN3, MN4 is connected, and the source of the second common-source and common-gate N-type transistor pair MN5, MN8 is connected to the ground GND.
[0020] Here, the first positive feedback N-type transistor pair MN6, MN7 can stabilize the output common mode of the first main operational amplifier and reduce the power consumption of the common mode feedback by one stage.
[0021] Referring to Figure 2 , the auxiliary operational amplifier comprises: a fifth common-source and common-gate P-type transistor pair MAP 12 , MAP 13 , a sixth common-source and common-gate P-type transistor pair MAP 10 , MAP 11 , a third common-source and common-gate N-type transistor pair MAP6, MAP7, a fourth common-source and common-gate N-type transistor pair MAP8, MAP9, a second common-source N-type transistor pair MAP1, MAP2, a fifth common-source and common-gate N-type transistor MAP4, a sixth common-source and common-gate N-type transistor MAP5, the second common-source N-type transistor pair MAP1, MAP2 and an input common-mode clamping MOS transistor MAP3. Here, the drain of the input common-mode clamping MOS transistor MAP3, the source of the fifth common-source and common-gate P-type transistor pair MAP 12 , MAP 13 are connected to a power supply voltage VDD; the gate of the input common-mode clamping MOS transistor MAP3 is connected to a special bias voltage V BAP (provided by a bias circuit), the source of the input common-mode clamping MOS transistor MAP3, the source of the second common-source N-type transistor pair MAP1, MAP2 and the drain of the fifth common-source and common-gate N-type transistor MAP4 are connected; the gates of the second common-source N-type transistor pair MAP1, MAP2 constitute two input ports V AP+, V AP- ; the drain of the second pair of common-source N-type transistors MAP1, MAP2 is cross-connected to the fifth pair of common-source and common-gate P-type transistors MAP 12 ; the drain of the fifth pair of common-source and common-gate P-type transistors MAP 13 ; the gate of the fifth pair of common-source and common-gate N-type transistors MAP4 is connected to the third bias voltage V B3 ; the source is connected to the drain of the sixth pair of common-source and common-gate N-type transistors MAP5; the gate of the sixth pair of common-source and common-gate N-type transistors MAP5 is connected to the fourth bias voltage V B4 ; the source is grounded; the gate of the fifth pair of common-source and common-gate P-type transistors MAP 12 ; the drain is connected to the source of the sixth pair of common-source and common-gate P-type transistors MAP 13 ; the gate is connected to the first bias voltage V B1 ; the drain is connected to the drain of the fourth pair of common-source and common-gate N-type transistors MAP8, MAP9; the gate of the fourth pair of common-source and common-gate N-type transistors MAP8, MAP9 is connected to the third bias voltage V 10 ; the source is connected to the drain of the third pair of common-source and common-gate N-type transistors MAP6, MAP7; the gate of the third pair of common-source and common-gate N-type transistors MAP6, MAP7 is connected to the fourth bias voltage V 11 ; the source is grounded; the gate of the sixth pair of common-source and common-gate P-type transistors MAP 10 ; the drain is connected to the drain of the fourth pair of common-source and common-gate N-type transistors MAP8, MAP9; the gate of the fourth pair of common-source and common-gate N-type transistors MAP8, MAP9 is connected to the third bias voltage V 11 ; the source is connected to the drain of the third pair of common-source and common-gate N-type transistors MAP6, MAP7; the gate of the third pair of common-source and common-gate N-type transistors MAP6, MAP7 is connected to the fourth bias voltage V B2 ; the source is grounded; wherein the two nodes corresponding to the drain of the sixth pair of common-source and common-gate P-type transistors MAP B3 ; and the drain of the fourth pair of common-source and common-gate N-type transistors MAP8, MAP9 constitute two output ports V B4 , V 10 .
[0022] The auxiliary operational amplifier adopts a fully differential folded common-source and common-gate structure, and simultaneously increases an input common-mode clamping MOS transistor MAP3. Through the MOS transistor and an external auxiliary operational amplifier, a direct current bias is provided, which can have a gain of more than 40 dB and a unity gain bandwidth of more than 1 GHz. Thus, through the auxiliary operational amplifier, the output impedance of the P-type transistors MP 11 and MP OA+ of the first main operational amplifier is improved, and is higher than the output impedance of the N-type transistors. Similarly, in the second main operational amplifier, the output impedance of the P-type transistors MP OA- , MP 10 , MP 11 , MP 12 , MP 13 , MP 14 , MP 15, the P-type transistor end output impedance is improved.
[0023] Referring to Figure 1 , the second main operational amplifier comprises: a third common-gate P-type transistor pair MP 12 , MP 13 , a fourth common-gate P-type transistor pair MP 14 , MP 15 , and a first common-N transistor pair MN9, MN 10 ; , the gate of the first common-N transistor pair MN9, MN 10 is connected to the two output ends V ON1 , V OP1 of the first main operational amplifier to which the drains of the first common-gate N-type transistor pair MN3, MN4 are connected, the drains of the first common-N transistor pair MN9, MN 10 are connected to a pair of compensation capacitors C C , the two Cascode nodes of the first main operational amplifier to which the drains of the first common-gate P-type transistor pair MP1, MP2 are connected, and the sources of the first common-N transistor pair MN9, MN 10 are grounded; the drains of the fourth common-gate P-type transistor pair MP 14 , MP 15 are connected to the drains of the first common-N transistor pair MN9, MN 10 , the gates are connected to the second bias voltage V B2 , the sources of the fourth common-gate P-type transistor pair MP 14 , MP 15 are connected to the drains of the third common-gate P-type transistor pair MP 12 , MP 13 , the sources of the third common-gate P-type transistor pair MP 12 , MP 13 are connected to the power supply voltage VDD, the gates are connected to the common-mode feedback voltage V CMFB provided by an external switched-capacitor common-mode feedback circuit, the external switched-capacitor common-mode feedback circuit outputs the common-mode feedback voltage V B1 based on an amplified signal output by the operational amplifier (i.e., the operational amplifier provided by the application for use in an operational amplifier sharing a high-speed pipeline analog-to-digital converter) and the first bias voltage V CMFB ; wherein the node to which the drains of the fourth common-gate P-type transistor pair MP 14 , MP 15 and the drains of the first common-N transistor pair MN9, MN 10 are connected is the two output ends V OP , V ON of the operational amplifier, and the two output ends V OP, V ON output an amplified signal.
[0024] The application provides an operational amplifier for sharing a high-speed pipeline analog-to-digital converter, a first main operational amplifier is responsible for realizing high gain and high voltage slew rate, a second main operational amplifier is responsible for realizing high output swing and further improving gain, and the whole operational amplifier can normally work under closed-loop negative feedback through Cascode compensation of a compensation capacitor. Since the compensation capacitor is connected between the output end of the second main operational amplifier and the Cascode node of the first main operational amplifier instead of being connected to the output end of the first main operational amplifier, the compensation capacitor is connected to a low-impedance node, a right-half-plane zero point is moved to a left-half-plane, and a main pole is further pushed in, thereby improving the closed-loop stability of the operational amplifier. Meanwhile, an adaptive bias circuit (specifically, a positive feedback circuit) is introduced to provide DC bias for the tail current source and the common-gate tube of the first main operational amplifier, bias current can be increased when the voltage slew rate is limited to make the amplifier quickly get rid of the voltage slew rate limited time. Not only the large voltage slew rate requirement and high gain of the operational amplifier in the high-speed high-precision pipeline analog-to-digital converter are solved, but also the problem of the right-half-plane low-frequency zero point in the ordinary Miller capacitor compensation scheme is solved, and a left-half-plane zero point is added to increase the unit gain bandwidth (a larger input tube MP1, MP2, MP3 and MP4 transconductance g m1 , g m2 , g m3 , g m4 and a smaller compensation capacitor Cc can realize high unit gain bandwidth), thereby significantly improving the precision of the operational amplifier.
[0025] Optionally, in an implementation manner, referring to Figure 1 The application provides an operational amplifier for sharing a high-speed pipeline analog-to-digital converter, which further comprises a first switch S1 and a second switch S2. The first switch S1 is connected between two output ends V ON1 , V OP1 of the first main operational amplifier; the second switch S2 is connected between two output ends V OP , V ON of the operational amplifier; and the opening and closing of the first switch S1 and the second switch S2 are controlled by an external reset clock RES.
[0026] It can be understood that for high-speed high-precision pipeline analog-to-digital converters, an effective way to increase the sampling rate is to realize multiple sampling rates through time domain interleaving technology and multiple channels, but this will bring a multiple increase in power consumption. Among them, the power consumption of the single-channel high-speed high-precision pipeline analog-to-digital converter first-stage sample-and-hold amplifier generally accounts for 1 / 3~1 / 2 of the entire pipeline analog-to-digital converter power consumption, so for a multi-channel time domain interleaving high-speed high-precision pipeline analog-to-digital converter, how to reduce the operational amplifier power consumption of the sample-and-hold circuit, thereby effectively reducing the overall power consumption of the pipeline analog-to-digital converter, is a problem worth studying. In order to solve this problem, the application additionally introduces a pair of input pairs of tubes (first switch S1 and second switch S2), and cooperates with a pair of channel switching switches (first channel switching P-type transistor MP6, second channel switching P-type transistor MP7) to enable the operational amplifier to work effectively in different working periods of the operational amplifier sharing high-speed pipeline analog-to-digital converter, thereby effectively saving the power consumption of the operational amplifier.
[0027] In one comprehensive embodiment, based on the complete circuit structure shown in Figure 1 , by providing the circuit with different two-phase non-overlapping working clocks CLK1 and CLK2 in a period, such as Figure 3 , so that the operational amplifier of the application is realized by the first and second common-source P-type transistor pairs and the first and second channel switching P-type transistors to work continuously with low power consumption; and the memory charge existing in the operational amplifier is reset by the reset clock RES (such as Figure 3 ), so as to realize the purpose of using the operational amplifier with high energy efficiency in the application of high-speed and high-precision operational amplifier sharing high-speed pipeline analog-to-digital converter, and has a precision of 16 bits in the sample-and-hold circuit of the operational amplifier sharing time domain interleaving pipeline analog-to-digital converter with a sampling rate of 200MSPS.
[0028] In summary, the application can be used as an operational amplifier in an operational amplifier sharing high-speed pipeline analog-to-digital converter, and can work effectively and maintain normal amplification function in two working clocks in a period, and can drive a larger load capacitor while maintaining gain and precision.
[0029] It should be noted that the terms "first", "second", and the like are used to distinguish similar objects, and are not necessarily used to describe a particular order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the application. Rather, they are merely examples of devices and methods consistent with some aspects of the application.
[0030] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the description of the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any appropriate manner in one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in the specification.
[0031] Although the present application is described herein in conjunction with various embodiments, those skilled in the art, with the benefit of the description and drawings presented herein, can understand and appreciate other variations of the disclosed embodiments. In the description of the present application, the word "comprising" does not exclude other components or steps, "a" or "one" does not exclude a plurality, and "multiple" means two or more, unless otherwise explicitly specified and limited. In addition, some measures are described in different embodiments, but this does not mean that these measures cannot be combined to produce good results.
[0032] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection", "fixing" and the like should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0033] The above is a further detailed description of the present application in conjunction with specific preferred embodiments, and the specific implementation of the present application cannot be limited to these descriptions. For those skilled in the art, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be considered as falling within the scope of protection of the present application.
Claims
1. An operational amplifier for use in a shared high-speed pipeline analog-to-digital converter, the operational amplifier comprising: The application relates to an adaptive biasing circuit for a folded cascode amplifier. The application relates to an adaptive biasing circuit for a folded cascode amplifier. The adaptive biasing circuit comprises a positive feedback circuit and an auxiliary operational amplifier.
2. The operational amplifier for use in a shared high-speed pipeline analog-to-digital converter of claim 1, wherein, The positive feedback circuit comprises a first positive feedback N-type transistor pair (MN6, MN7) and a second cascode N-type transistor pair (MN5, MN8). The first main operational amplifier comprises a first tail current P-type transistor (MP5), a first channel switching P-type transistor (MP6), a second channel switching P-type transistor (MP7), a first common source P-type transistor pair (MP1, MP2), a second common source P-type transistor pair (MP3, MP4), a first tail current N-type transistor pair (MN1, MN2), a first common source common gate N-type transistor pair (MN3, MN4), a first common source common gate P-type transistor pair (MP8, MP9), and a second common source common gate P-type transistor pair (MP 10 , MP 11 ). The source of the first tail current P-type transistor (MP5) is connected with a power supply voltage, and the gate is connected with a first bias voltage; the sources of the first channel switching P-type transistor (MP6) and the second channel switching P-type transistor (MP7) and the drain of the first tail current P-type transistor (MP5) are connected; the gate of the first channel switching P-type transistor (MP6) is connected with a first clock, and the gate of the second channel switching P-type transistor (MP7) is connected with a second clock; the first clock and the second clock are two-phase non-overlapping clocks provided by the analog-to-digital converter; the drain of the first channel switching P-type transistor (MP6) is connected with the source of the first common-source P-type transistor pair (MP1, MP2); the drain of the second channel switching P-type transistor (MP7) is connected with the source of the second common-source P-type transistor pair (MP3, MP4); the gates of the first common-source P-type transistor pair (MP1, MP2) and the second common-source P-type transistor pair (MP3, MP4) are connected with a four-way input signal; the drain of the first common-source P-type transistor pair (MP1, MP2), the drain of the first tail current N-type transistor pair (MN1, MN2) and the source of the first common-source common-gate N-type transistor pair (MN3, MN4) are connected correspondingly to form two Cascode nodes, and the two Cascode nodes are connected with the positive feedback circuit; the gate of the first tail current N-type transistor pair (MN1, MN2) is connected with a fourth bias voltage, and the source is connected with the ground; the gate of the first common-source common-gate N-type transistor pair (MN3, MN4) is connected with a third bias voltage, and the drain is connected with the drain of the second common-source common-gate P-type transistor pair (MP 10 , MP 11 ) to form two output terminals of the first operational amplifier, and the two output terminals are connected with the positive feedback circuit; the gates of the second common-source common-gate P-type transistor pair (MP 10 , MP 11 ) are connected with the input of the auxiliary operational amplifier, the output of the auxiliary operational amplifier is connected with the source of the second common-source common-gate P-type transistor pair (MP 10 , MP 11 ) and the drain of the first common-source common-gate P-type transistor pair (MP8, MP9); and the source of the first common-source common-gate P-type transistor pair (MP8, MP9) is connected with a power supply voltage, and the gate is connected with a first bias voltage.
3. The operational amplifier for use in a shared high-speed pipeline analog-to-digital converter of claim 2, wherein, The gate of the first positive feedback N-type transistor pair (MN6, MN7) is cross-connected with the two output ends connected with the drain of the first cascode N-type transistor pair (MN3, MN4); the drain of the first positive feedback N-type transistor pair (MN6, MN7) is connected with the two Cascode nodes connected with the source of the first cascode N-type transistor pair (MN3, MN4), and the source of the first positive feedback N-type transistor pair (MN6, MN7) is grounded; the gate of the second cascode N-type transistor pair (MN5, MN8) is connected with the two output ends connected with the drain of the first cascode N-type transistor pair (MN3, MN4); the drain of the second cascode N-type transistor pair (MN5, MN8) is connected with the two Cascode nodes connected with the source of the first cascode N-type transistor pair (MN3, MN4), and the source of the second cascode N-type transistor pair (MN5, MN8) is grounded. The application further relates to a folded cascode amplifier.
4. The operational amplifier for sharing high speed pipeline analog-to-digital converter of claim 2, wherein, The second main operational amplifier comprises a third common-source and common-gate P-type transistor pair (MP 12 , MP 13 ), a fourth common-source and common-gate P-type transistor pair (MP 14 , MP 15 ), and a first common-source N-type transistor pair (MN9, MN 10 ). The gate of the first common-source N-type transistor pair (MN9, MN 10 ) is connected to the two output terminals connected to the drains of the first common-source common-gate N-type transistor pair (MN3, MN4), the drains of the first common-source N-type transistor pair (MN9, MN 10 ) are connected to the two Cascode nodes connected to the drains of the first common-source P-type transistor pair (MP1, MP2) through the pair of compensation capacitors, and the sources of the first common-source N-type transistor pair (MN9, MN 10 ) are grounded. The drains of the fourth common-source common-gate P-type transistor pair (MP 14 , MP 15 ) are connected to the drains of the first common-source N-type transistor pair (MN9, MN 10 ), the gates are connected to the second bias voltage, the sources of the fourth common-source common-gate P-type transistor pair (MP 14 , MP 15 ) are connected to the drains of the third common-source common-gate P-type transistor pair (MP 12 , MP 13 ), the sources of the third common-source common-gate P-type transistor pair (MP 12 , MP 13 ) are connected to the power supply voltage, and the gates are connected to the common-mode feedback voltage provided by an external switched-capacitor common-mode feedback circuit, which outputs the common-mode feedback voltage based on the amplified signal and the first bias voltage; wherein the node connected to the drains of the fourth common-source common-gate P-type transistor pair (MP 14 , MP 15 ) and the first common-source N-type transistor pair (MN9, MN 10 ) is the two output terminals of the operational amplifier, which output the amplified signal.
5. The operational amplifier for sharing high speed pipeline analog-to-digital converter of claim 2, wherein, The auxiliary operational amplifier includes: a fifth common-source common-gate P-type transistor pair (MAP 12 , MAP 13 ), a sixth common-source common-gate P-type transistor pair (MAP 10 , MAP 11 ), a third common-source common-gate N-type transistor pair (MAP6, MAP7), a fourth common-source common-gate N-type transistor pair (MAP8, MAP9), a second common-source N-type transistor pair (MAP1, MAP2), a fifth common-source common-gate N-type transistor (MAP4), a sixth common-source common-gate N-type transistor (MAP5), a second common-source N-type transistor pair (MAP1, MAP2), and an input common-mode clamping MOS transistor (MAP3); The drain of the input common-mode clamping MOS transistor (MAP3), the source of the fifth common-source and common-gate P-type transistor pair (MAP 12 , MAP 13 ) are connected to the power supply voltage; the gate of the input common-mode clamping MOS transistor (MAP3) is connected to a special bias voltage, and the source of the input common-mode clamping MOS transistor (MAP3), the source of the second common-source N-type transistor pair (MAP1, MAP2) and the drain of the fifth common-source and common-gate N-type transistor (MAP4) are connected; the gates of the second common-source N-type transistor pair (MAP1, MAP2) constitute two input ports of the auxiliary operational amplifier; the drains of the second common-source N-type transistor pair (MAP1, MAP2) are cross-connected to the drains of the fifth common-source and common-gate P-type transistor pair (MAP 12 , MAP 13 ); the gate of the fifth common-source and common-gate N-type transistor (MAP4) is connected to a third bias voltage, and the source is connected to the drain of the sixth common-source and common-gate N-type transistor (MAP5); the gate of the sixth common-source and common-gate N-type transistor (MAP5) is connected to a fourth bias voltage, and the source is grounded; the gates of the fifth common-source and common-gate P-type transistor pair (MAP 12 , MAP 13 ) are connected to a first bias voltage, and the drains are connected to the sources of the sixth common-source and common-gate P-type transistor pair (MAP 10 , MAP 11 ); the gates of the sixth common-source and common-gate P-type transistor pair (MAP 10 , MAP 11 ) are connected to a second bias voltage, and the drains are connected to the drains of the fourth common-source and common-gate N-type transistor pair (MAP8, MAP9); the gates of the fourth common-source and common-gate N-type transistor pair (MAP8, MAP9) are connected to a third bias voltage, and the sources are connected to the drains of the third common-source and common-gate N-type transistor pair (MAP6, MAP7); the gates of the third common-source and common-gate N-type transistor pair (MAP6, MAP7) are connected to a fourth bias voltage, and the sources are grounded; wherein the two nodes corresponding to the drains of the sixth common-source and common-gate P-type transistor pair (MAP 10 , MAP 11 ) and the fourth common-source and common-gate N-type transistor pair (MAP8, MAP9) constitute two output ports of the auxiliary operational amplifier.
6. The operational amplifier for use in a shared high-speed pipeline analog-to-digital converter of claim 4, wherein, The application further relates to a folded cascode amplifier. The first switch (S1) is connected between the two output ends of the first main operational amplifier; the second switch (S2) is connected between the two output ends of the main operational amplifier; and the opening and closing of the first switch (S1) and the second switch (S2) are controlled by an external reset clock.