Semiconductor device and preparation method thereof

Abstract

According to the semiconductor device and the preparation method thereof, a plurality of first conductive plugs are arranged in an isolation structure, gradient voltage is applied to the first conductive plugs, and a gradient electric field is formed in an area below the isolation structure, so that dynamic modulation of carrier concentration distribution is realized; therefore, the problem of mutual restriction between the on-resistance and the breakdown voltage in the traditional static doping design is solved. The gradient electric field modulation enables the device to adjust the performance parameters according to different working conditions, improves the breakdown voltage and reduces the leakage current in a high-voltage region through enhancing the carrier depletion, and reduces the on resistance and improves the current conduction capability in a low-voltage region through increasing the carrier concentration. And therefore, a single device structure can adapt to various working condition requirements.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor device and its fabrication method. Background Technology

[0002] Laterally diffused metal-oxide-semiconductor (LDMOS) devices are key power devices in power management chips and are widely used in circuits such as DC-DC converters and power amplifiers. Their performance is mainly measured by breakdown voltage, on-resistance, and reliability. Among these, on-resistance per unit area is an important parameter for evaluating the device's conduction performance, directly affecting power loss and chip area efficiency.

[0003] Traditional lateral double-diffused metal-oxide-semiconductor (MOSFET) devices use static doping distribution methods to control on-resistance per unit area, reducing on-resistance by adjusting the doping concentration and distribution of junction field-effect transistors. The industry has also developed advanced structures such as superjunction technology and trench gate technology to improve device performance. These technologies, to some extent, alleviate the trade-off between on-resistance and breakdown voltage.

[0004] However, existing technical solutions have certain limitations, mainly in that they cannot adapt to different working conditions, static doping design causes device performance to be fixed, and although advanced structure technology can improve performance, the process is complex and costly.

[0005] Therefore, there is an urgent need to provide new solutions to address the aforementioned problems. Summary of the Invention

[0006] The purpose of this application is to provide a semiconductor device and its fabrication method to solve the problems of existing technologies that cannot adapt to different working conditions, static doping design causes device performance to be fixed, and existing processes are complex and costly.

[0007] According to a first aspect of this application, one embodiment of this application provides a semiconductor device comprising: a substrate; a device structure located on the substrate, the device structure including a source region, a drain region, and a gate located on the substrate between the source region and the drain region; an isolation structure located in the substrate between the drain region and the gate; a plurality of first conductive plugs located within the isolation structure, the plurality of first conductive plugs being spaced apart along the drain region toward the gate direction, each of the first conductive plugs being electrically connected to the substrate; the plurality of first conductive plugs being used to couple a gradient voltage to form a gradient electric field in a region below the isolation structure.

[0008] According to a second aspect of this application, one embodiment of this application provides a method for fabricating a semiconductor device, comprising the following steps: providing a substrate; forming a device structure on the substrate, the device structure including a source region, a drain region, and a gate located on the substrate between the source region and the drain region; forming an isolation structure in the substrate between the drain region and the gate; and disposing a plurality of first conductive plugs electrically connected to the substrate within the isolation structure along the drain region toward the gate direction; the plurality of first conductive plugs being used to couple a gradient voltage to form a gradient electric field in a region below the isolation structure.

[0009] This application provides a semiconductor device that dynamically modulates the carrier concentration distribution by placing multiple first conductive plugs within an isolation structure and applying a gradient voltage to them. This creates a gradient electric field in the region below the isolation structure, thereby resolving the mutual constraint between on-resistance and breakdown voltage in traditional static doping designs. The gradient electric field modulation of this application allows the device to adjust its performance parameters according to different operating conditions. In the high-voltage region, it enhances carrier depletion to increase breakdown voltage and reduce leakage current, while in the low-voltage region, it increases carrier concentration to reduce on-resistance and improve current conduction capability. This allows a single device structure to adapt to various operating conditions.

[0010] Furthermore, the first conductive plug in this application can penetrate the isolation structure and directly contact the silicon substrate, or the distance between its bottom and the lower surface of the isolation structure can be controlled within 50 nanometers, ensuring that the gradient electric field can effectively penetrate into the substrate and achieve modulation of the charge carriers, thus guaranteeing the electrical connection between the first conductive plug and the silicon substrate. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of this application.

[0013] Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application.

[0014] Figure 3 This is a flowchart illustrating the sub-steps of step S200 in this application.

[0015] Figures 4A to 4F This is a process flow diagram of the semiconductor device fabrication method of this application. Detailed Implementation

[0016] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] In semiconductor devices, laterally diffused metal-oxide-semiconductor (LDMOS) devices are crucial components of power management chips, and their performance is primarily evaluated through three key indicators: breakdown voltage, on-resistance, and reliability. In the device structure, a well region, drift region, source region, drain region, and gate are sequentially formed on the substrate, and electrical isolation between devices is achieved through a shallow trench isolation (STI) structure. During actual operation, when a turn-on voltage is applied to the gate, a carrier conduction path is formed in the channel between the source and drain regions, and current flows from the source region to the drain region. At this time, the on-resistance of the device is mainly determined by the drift region resistance, which directly affects the device's power loss and conduction performance.

[0018] Existing methods for reducing the on-resistance of LDMOS devices have various shortcomings in practical applications. While traditional doping methods can reduce on-resistance to some extent by adjusting the doping concentration in the drift region, this static doping approach cannot meet the changing performance requirements of the device under different operating voltages, currents, and temperatures. At high voltages, a lower doping concentration is needed to ensure sufficient breakdown voltage, but this increases on-resistance. Conversely, at low voltages, a higher doping concentration can reduce on-resistance, but this sacrifices the device's breakdown voltage. The root cause of this trade-off is that fixed doping cannot simultaneously achieve high conductivity and depletionability in the drift region. When operating conditions change, it is impossible to dynamically adjust the carrier concentration to compensate for the effects of different operating voltages, currents, and temperatures on carrier mobility.

[0019] While employing advanced structures such as superjunction technology or trench gate technology to improve device performance can alleviate the conflict between on-resistance and breakdown voltage to some extent, these solutions suffer from structural complexity, high manufacturing difficulty, and high production costs. More importantly, once these structures are manufactured, their performance parameters are fixed and cannot be dynamically adjusted according to actual operating conditions. In practical applications such as power management, devices need to adapt to varying operating conditions, but existing static doping designs result in fixed device performance parameters that cannot be dynamically adjusted based on operating conditions.

[0020] Furthermore, temperature variations also affect device performance. As operating temperature increases, carrier mobility decreases, leading to increased on-resistance; conversely, while decreasing temperature improves mobility, it may affect the device's turn-on characteristics. Traditional solutions cannot compensate for temperature variations, resulting in poor performance consistency across different temperature conditions and thus affecting the device's stable operation across the entire temperature range.

[0021] The researchers in this application discovered that the problem with existing techniques lies in their use of static doping profile design. Once the device is manufactured, its carrier concentration distribution is fixed and cannot be dynamically adjusted according to actual operating conditions. Because the carrier concentration distribution is fixed, the device must make trade-offs between different performance indicators, making it impossible to achieve optimal performance under all operating conditions. Traditional doping profiles can only make compromises under known constraints and cannot solve the limitations of static doping.

[0022] To address the problems existing in the prior art, this application proposes a semiconductor device structure with dynamic resistance regulation. By setting multiple first conductive plugs within an isolation structure and applying gradient voltages to different plugs, a controllable gradient electric field is formed in the region below the isolation structure, thereby achieving dynamic modulation of the carrier concentration distribution and overcoming the limitations of traditional static doping.

[0023] The semiconductor device of this application may include a substrate, a device structure on the substrate, and an isolation structure in the substrate. The device structure may include a source region, a drain region, a gate region, and a body region. The isolation structure has a plurality of first conductive plugs electrically connected to the substrate. By applying different voltage values ​​to different first conductive plugs, a gradient electric field is formed in the region below the isolation structure, thereby modulating the carrier concentration distribution in the region.

[0024] See Figure 1 As shown, the semiconductor device provided in this application may include a substrate 110, a device structure located on the substrate 110, and an isolation structure 150.

[0025] In this embodiment, the substrate 110 can be a silicon substrate. In other embodiments, the substrate 110 can also be other substrates, and this application does not limit this.

[0026] In this embodiment, the device structure may include a source region 160, a drain region 170, and a gate region 190.

[0027] The source region 160 and the drain region 170 are located on the surface regions of the substrate 110, and the surfaces of the source region 160 and the drain region 170 are flush with the substrate surface. The gate 190 is located on the substrate surface between the source region 160 and the drain region 170.

[0028] In this embodiment, the device structure may further include a body region 180, which is located on the side of the source region 160 away from the gate structure. The body region 180 is used to provide channel control and body contact.

[0029] In this embodiment, the source region 160 is formed by N+ ion implantation as an N+ source region, the drain region 170 is formed by N+ ion implantation (phosphorus (P), antimony (Sb) or arsenic (As)) as an N+ drain region, and the body region 180 is formed by P+ ion implantation (e.g. boron (B), gallium (Ga) or indium (In)) as a P+ body region.

[0030] In one specific embodiment, the device structure is a laterally double-diffused metal-oxide-semiconductor device structure. The substrate 110 is a P-type silicon substrate. Deep well region 120 (deep N-well in this embodiment), P-well 130, and N-well 140 are formed in the silicon substrate through a doping process. P-well 130 and N-well 140 are located within deep well region 120. The region between P-well 130 and N-well 140 serves as the drift region S1 of the device, which withstands a high voltage from the source region to the drain region.

[0031] In this embodiment, the source region 160 and the body region 180 are located within the P-well 130, and the drain region 170 is located within the N-well 140.

[0032] In this embodiment, the isolation structure 150 is a shallow trench isolation structure (STI) used to achieve electrical isolation between adjacent devices.

[0033] In this embodiment, the isolation structure 150 is provided with a plurality of contact holes 220 (e.g., Figure 4C As shown, each contact hole 220 contains a first conductive plug 400 (including a diffusion barrier 240 and a filling metal layer 250), and each first conductive plug 400 is electrically connected to the silicon substrate. By applying different voltage values ​​to different conductive plugs 400, a gradient electric field can be formed in the region S2 below the isolation structure 150, thereby modulating the carrier concentration distribution in the region S2. The electric field application method used in this application is a vertical back gate electrode structure, which is different from the side electrode or planar top gate method. By adopting a vertical back gate structure, a vertical electric field component can be formed in the region S2 below the isolation structure 150. The electric field intensity can directly act on the bottom of the device channel, achieving efficient modulation of the carrier concentration and avoiding the lateral electric field interference problem that may be caused by the side electrode. In order to ensure that the first conductive plug 400 can effectively modulate the carrier concentration distribution, in this embodiment, the first conductive plug 400 does not completely penetrate the isolation structure 150, and the distance between the bottom of the first conductive plug 400 and the lower surface of the shallow trench isolation structure is within 50 nanometers, for example, it can be 10 nanometers, 30 nanometers or 50 nanometers.

[0034] In another embodiment, the first conductive plug 400 may also penetrate the isolation structure 150 and make direct contact with the silicon substrate.

[0035] It should be noted that, theoretically, the ideal state for achieving electrical connection is for the first conductive plug 400 to penetrate the isolation structure 150 and directly contact the silicon substrate. However, in actual manufacturing processes, complete penetration of the isolation structure 150 may be technically challenging due to limitations in the aspect ratio of the contact hole etching process and the influence of process control precision. Therefore, when the distance between the bottom of the first conductive plug 400 and the lower surface of the isolation structure 150 is controlled within 50 nanometers, an effective electrical connection between the first conductive plug 400 and the silicon substrate can still be achieved through tunneling and electric field coupling. In this case, the voltage applied to the first conductive plug 400 can effectively penetrate to the silicon substrate, forming the required electric field strength on the surface of the silicon substrate, thereby achieving the desired carrier modulation effect.

[0036] In one embodiment, the distance between the center of the first conductive plug 400 and the boundary of the shallow trench isolation structure is greater than or equal to 50 nanometers. It should be noted that this distance parameter primarily considers process reliability requirements, as the range of 0 to 30 nanometers from the boundary of the shallow trench isolation structure is a high-risk area. If etching is performed within this area, anisotropic etching may expose the sidewall silicon, easily leading to leakage problems. In this embodiment, by controlling the center position of the first conductive plug 400 within a safe range of more than 50 nanometers from the boundary, structural damage during the process can be effectively avoided.

[0037] In one embodiment, the diameter of the first conductive plug 400 is D, and the depth of the isolation structure 150 is H. The two satisfy the following relationship: 0.5H≤D≤H. For example, when the depth of the shallow trench isolation structure is 1 micrometer, the diameter of the first conductive plug 400 can be 0.5 micrometers, 0.8 micrometers, or 1 micrometer. This ensures both the feasibility of the etching process and that the first conductive plug 400 has a sufficient cross-sectional area to carry the working current.

[0038] In one embodiment, an insulating layer 230 is provided on the sidewall of the first conductive plug 400, the insulating layer 230 being located between the first conductive plug 400 and the isolation structure 150.

[0039] Specifically, the thickness of the insulating layer 230 is controlled within the range of 5 to 20 nanometers, for example, it can be 8 nanometers, 15 nanometers or 20 nanometers, but is not limited to this.

[0040] Furthermore, the material of the insulating layer 230 may include a high dielectric constant material. In other embodiments, the material of the insulating layer 230 may also include silicon nitride or aluminum oxide, etc.

[0041] In the above embodiments, the insulating layer 230 serves a dual purpose: firstly, it confines the current path to the bottom region of the first conductive plug 400, preventing lateral short circuits caused by current leakage through the sidewalls; secondly, it effectively suppresses the diffusion of metal ions from the first conductive plug 400 to the sidewalls of the contact hole 220, avoiding metal contamination from affecting device performance. It is noteworthy that regardless of whether the bottom of the first conductive plug 400 is in direct contact with the silicon substrate, or whether there is a gap of no more than 50 nanometers between its bottom and the lower surface of the isolation structure 150, the electric field can be effectively transferred to the silicon substrate surface, achieving the desired carrier modulation effect.

[0042] In one embodiment, the first conductive plug 400 is a composite structure, which may specifically include a diffusion barrier layer 240 and a filler metal layer 250.

[0043] The diffusion barrier layer 240 may be made of titanium / titanium nitride, and its thickness may be in the range of 10 to 50 nanometers, for example, 15 nanometers, 25 nanometers, or 40 nanometers, but is not limited thereto. The titanium layer has good contact characteristics with the semiconductor material, while the titanium nitride layer provides better diffusion barrier performance.

[0044] In this embodiment, the material of the filler metal layer 250 of the first conductive plug 400 may include tungsten (W). Tungsten material has advantages such as low resistivity, high melting point, and good process compatibility, which can meet the requirements of high current density and high temperature operating environments. In other embodiments, the material of the filler metal layer 250 may also include copper or aluminum.

[0045] In one embodiment, a plurality of first conductive plugs 400 are distributed along the drift region S1 direction of the device structure, that is, they are spaced apart along the drain region toward the gate.

[0046] In this embodiment, the number of first conductive plugs 400 is determined based on the area of ​​the isolation structure 150 and the plug diameter.

[0047] Specifically, the number of the first conductive plugs 400 satisfies N ≤ A_sti / (3D). 2 The relationship is as follows: A_sti is the area of ​​the isolation structure 150 region, D is the diameter of the first conductive plug 400, and N is the number of first conductive plugs 400. In practical applications, the number of first conductive plugs 400 is controlled within the range of 3 to 8. Figure 1 In the embodiment shown, there are three first conductive plugs 400.

[0048] In one embodiment, the semiconductor device may further include an interlayer dielectric layer 310 located on the substrate 110, the first conductive plug 400 penetrating the interlayer dielectric layer 310; and a plurality of second conductive plugs 500 located within and penetrating the interlayer dielectric layer 310, the plurality of second conductive plugs 500 being electrically connected to the source region 160, the drain region 170, and the gate region 190, respectively.

[0049] In this embodiment, the material of the interlayer dielectric layer 310 may include silicon oxide.

[0050] In this embodiment, the semiconductor device described in this application applies different voltage values ​​to different first conductive plugs 400 to form a gradient electric field in the region S2 below the isolation structure 150, thereby modulating the carrier concentration distribution in the region S2.

[0051] In one embodiment, multiple first conductive plugs 400 can be connected to an external gradient voltage source via device pins. The external gradient voltage source uses a resistor divider circuit to provide gradient voltages to different first conductive plugs 400. For example, voltages of 30V, 20V, and 10V are applied respectively. The source region 160, drain region 170, body region 180, and gate 190 are connected to an external circuit (e.g., a voltage source circuit) via second conductive plugs. A 40V operating voltage is applied to the drain region 170, the source region 160 is grounded (0V), the body region 180 is grounded (0V), and a corresponding control voltage is applied to the gate 190. Through the above voltage configuration, a voltage gradient distribution from the drain region to the source region is formed, ensuring the effective establishment of the gradient electric field.

[0052] By combining the above distribution method with gradient electric field control of gradient voltage, the carrier concentration in the drift region S1 can be effectively modulated. When different voltages are applied to the first conductive plug 400 at different locations, a gradient electric field is formed in the drift region S1. This gradient electric field causes the carrier concentration to decrease in the high-voltage region and increase in the low-voltage region. It is worth noting that regardless of whether the first conductive plug 400 completely penetrates the isolation structure 150, as long as the electrical connection conditions are met (i.e., direct contact or a spacing of no more than 50 nanometers), an effective electric field modulation effect can be achieved. The electric field transfer efficiency is highest when the first conductive plug 400 is in direct contact with the silicon substrate; when there is a thin layer gap between the bottom of the first conductive plug 400 and the lower surface of the isolation structure 150, the electric field can still effectively act on the carriers on the silicon substrate surface through tunneling effect and electrostatic coupling. When a gradient voltage is applied, different locations of the device can be in a depletion, inversion, or accumulation state. For example, the drain region 170 (high voltage region) achieves deep depletion to improve the breakdown voltage, and the source region 160 (low voltage region) forms a strong inversion layer to reduce resistance. By dynamically adjusting the carrier concentration, the strong exponential relationship between the original on-resistance and breakdown voltage is transformed into an adjustable relationship.

[0053] This application also provides a method for fabricating a semiconductor device, in conjunction with reference to [reference needed]. Figure 2 , Figure 3 as well as Figures 4A to 4F As shown, this method is used to prepare the semiconductor device described in the foregoing embodiments, and may specifically include the following steps:

[0054] Step S100: Provide a substrate 110 and form a device structure on the substrate 110. The device structure may include a source region 160, a drain region 170, a body region 180 and a gate 190 on the substrate between the source region 160 and the drain region 170. An isolation structure 150 is formed in the substrate 110.

[0055] In step S100, P-type silicon is used as the substrate material 110, and basic structural units of the device, such as a deep well region 120, a source region 160, a drain region 170, a body region 180, and a gate region 190, are sequentially formed on the substrate. Furthermore, a shallow trench isolation process is used to form an isolation structure 150 in the substrate. The depth of the isolation structure 150 is designed according to the device's voltage withstand requirements and can range from several hundred nanometers to several micrometers, for example, 500 nanometers, 1 micrometer, or 2 micrometers.

[0056] Step S200: Along the drain region toward the gate direction, a plurality of first conductive plugs 400 electrically connected to the substrate 110 are disposed within the isolation structure 150. These first conductive plugs 400 are used to couple gradient voltages to form a gradient electric field in the region below the isolation structure. In other words, this step provides an electrode structure for subsequent electric field modulation by fabricating the first conductive plugs 400 inside the isolation structure 150.

[0057] In this embodiment, before setting the first conductive plug 400, an interlayer dielectric layer can be pre-formed on the surface of the substrate, the interlayer dielectric layer covering the device structure and the surface of the isolation structure.

[0058] In one specific embodiment, setting the first conductive plug in step S200 may include:

[0059] See Figure 3 As shown, step S201: Photolithography is performed on the isolation structure 150 to form the contact hole 220 pattern.

[0060] In this embodiment, photoresist 210 is first coated on the surface of the isolation structure. Then, a photomask is used for exposure, and the pattern on the photomask is transferred to the photoresist through a development process to form the photoresist pattern of the contact holes 220. It should be noted that the photomask used needs to take into account parameters such as the position, size, and number of the contact holes 220 to ensure that it meets the requirements of subsequent processes.

[0061] Step S202: Based on the contact hole pattern, a contact hole 220 is formed in the isolation structure 150 by dry etching.

[0062] Specifically, when forming the contact hole 220 in the isolation structure 150 by dry etching, the contact hole 220 can be formed by multiple etching processes.

[0063] For example, the isolation structure 150 can be first dry-etched, and after etching to the isolation structure and a preset depth (such as two-thirds of the depth of the isolation structure), a second dry etching can be performed.

[0064] In this embodiment, the etching rate of the first dry etching method is greater than that of the second dry etching method. This allows the initial contact hole to be formed quickly through the faster first dry etching method, and the initial contact hole can be etched through the slower second dry etching method to form the contact hole. This avoids over-etching of the contact hole, which could damage the substrate and affect the device performance.

[0065] In this embodiment, dry etching is used to remove oxides in areas not covered by photoresist, thereby forming contact holes 220 within the isolation structure 150. The control of etching process parameters directly affects the shape and depth of the contact holes 220. Ideally, the etching depth should allow the contact holes 220 to penetrate the entire isolation structure 150, enabling the subsequently formed first conductive plug 400 to directly contact the silicon substrate. Considering the aspect ratio limitations of the contact holes 220, complete penetration may result in poor sidewall morphology or difficulty in controlling the etching stop layer when the isolation structure 150 is thick. In this case, the etching depth is controlled to maintain a gap of no more than 50 nanometers between the bottom of the contact holes 220 and the lower surface of the isolation structure 150. This ensures process controllability and reproducibility while achieving electrical connection between the first conductive plug 400 and the substrate through tunneling.

[0066] As mentioned above, an interlayer dielectric layer is also formed on the substrate surface. Photoresist 210 can be formed on the surface of the interlayer dielectric layer. When forming contact holes 220 in the isolation structure 150 by dry etching, the interlayer dielectric layer and the isolation structure can be etched sequentially to form contact holes 220.

[0067] To further improve the electrical performance and reliability of the device, in one embodiment, the following may be included before step S203:

[0068] Step S203A: An insulating layer 230 is formed on the inner surface of the contact hole 220 by atomic layer deposition.

[0069] In this embodiment, atomic layer deposition technology is used to form an insulating layer 230 with uniform thickness and good density on the inner surface of the contact hole 220.

[0070] In one embodiment, an interlayer dielectric layer is formed on the substrate surface, and an insulating layer 230 may also be formed on the surface of the interlayer dielectric layer.

[0071] In one embodiment, the insulating layer 230 may be made of a high dielectric constant material such as alumina (Al2O3) or silicon nitride (Si3N4).

[0072] Furthermore, the thickness of the insulating layer 230 is controlled within the range of 5 to 20 nanometers.

[0073] Step S203B: Remove the insulating layer 230 at the bottom of the contact hole 220, and retain the insulating layer 230 on the sidewall of the contact hole 220.

[0074] In this embodiment, the insulating layer 230 at the bottom of the contact hole 220 is selectively removed by a directional etching process, while the insulating layer 230 on the sidewall of the contact hole 220 is retained to prevent lateral current leakage.

[0075] It is worth noting that by removing the bottom insulating layer 230, when the contact hole 220 penetrates the entire isolation structure 150, the subsequently filled metal can directly contact the silicon substrate; when the bottom of the contact hole 220 and the lower surface of the isolation structure 150 maintain a spacing of no more than 50 nanometers, the filled metal achieves electrical connection with the silicon substrate through the tunneling effect.

[0076] Step S203: Deposit a diffusion barrier layer 240 and a filler metal layer 250 in the contact hole 220 to form the first conductive plug 400.

[0077] Specifically, a titanium / titanium nitride (Ti / TiN) diffusion barrier layer 240 can be deposited on the inner surface of the contact hole 220 using physical vapor deposition (PVD), followed by the deposition of a tungsten layer (W) to fill the contact hole 220 using chemical vapor deposition (CVD), and finally the excess tungsten metal layer can be removed by chemical mechanical planarization (CMP) to form a first conductive plug 400 flush with the surface of the isolation structure 150.

[0078] In one embodiment, the method for fabricating a semiconductor device may further include: forming a plurality of second conductive plugs.

[0079] In this embodiment, the second conductive plug 500 is formed in the interlayer dielectric layer 310 on the surface of the source region 160, the drain region 170, the body region 180 and the gate 190, respectively, and the second conductive plug 500 is electrically connected to the source region 160, the drain region 170, the body region 180 and the gate 190, respectively.

[0080] In this embodiment, the second conductive plug 500 can be formed simultaneously with the first conductive plug 400. That is, when the contact hole 220 of the first conductive plug 400 is formed, the contact hole 220 of the second conductive plug 500 is also formed at the same time. When the first conductive plug 400 is formed in the contact hole 220 of the first conductive plug 400, the second conductive plug 500 is also formed accordingly.

[0081] In another embodiment, the second conductive plug 500 can also be formed separately. Specifically, the interlayer dielectric layer 310 can first be photolithographically developed to form contact hole patterns corresponding to the source region 160, drain region 170, body region 180, and gate 190; then, corresponding contact holes 220 are formed in the interlayer dielectric layer 310 by dry etching. The contact holes 220 penetrate the interlayer dielectric layer 310 and expose the surfaces of the source region 160, drain region 170, body region 180, and gate 190; further, a diffusion barrier layer and a filler metal layer are sequentially deposited in the contact holes 220, and excess filler metal layer is removed by a chemical mechanical planarization process to form the second conductive plug 500. The second conductive plug 500 is used to realize the electrical connection between the source region 160, drain region 170, body region 180, and gate 190 and the external circuit, providing an electrical path for the normal electrical function of the device.

[0082] For a more detailed description of the fabrication methods of semiconductor devices, please refer to the previous section on semiconductor devices; it will not be repeated here.

[0083] It should be noted that multiple first conductive plugs 400 can be connected to an external gradient voltage source via device pins. The external gradient voltage source uses a resistor divider circuit to provide gradient voltages to different first conductive plugs 400. For example, voltages of 30V, 20V, and 10V can be applied respectively. The source region 160, drain region 170, body region 180, and gate 190 are connected to an external circuit (e.g., a voltage source circuit) via second conductive plugs 500. A 40V operating voltage is applied to the drain region 170, the source region 160 is grounded (0V), the body region 180 is grounded (0V), and a corresponding control voltage is applied to the gate 190. Through the above voltage configuration, a voltage gradient distribution from the drain region to the source region is formed, ensuring the effective establishment of the gradient electric field.

[0084] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The features, structures, or characteristics described above can be combined in any suitable manner in one or more embodiments.

[0085] It is understood that those skilled in the art, guided by the above embodiments, can combine various implementation methods in the above embodiments to obtain technical solutions with multiple implementation methods. The above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor device, characterized by, include: Substrate; A device structure located on the substrate, the device structure including a source region, a drain region, and a gate located on the substrate between the source region and the drain region; An isolation structure located in the substrate between the drain region and the gate; A plurality of first conductive plugs located within the isolation structure are arranged at intervals along the drain region toward the gate, and each first conductive plug is electrically connected to the substrate. Multiple first conductive plugs are used to couple gradient voltages to form a gradient electric field in the region beneath the isolation structure.

2. The semiconductor device of claim 1, wherein, The first conductive plug penetrates the isolation structure, or the distance between the bottom of the first conductive plug and the lower surface of the isolation structure does not exceed 50 nanometers.

3. The semiconductor device of claim 1, wherein, The distance from the center of the first conductive plug to the boundary of the isolation structure is greater than or equal to 50 nanometers, and the diameter D of the first conductive plug and the depth H of the isolation structure satisfy 0.5H≤D≤H.

4. The semiconductor device of claim 1, wherein, Also includes: An insulating layer is located between the sidewall of the first conductive plug and the isolation structure, the thickness of the insulating layer being 5 to 20 nanometers.

5. The semiconductor device of claim 1, wherein, The conductive plug includes a diffusion barrier layer and a filler metal layer, wherein the diffusion barrier layer is a titanium / titanium nitride layer and the filler metal layer is a tungsten layer.

6. The semiconductor device of claim 1, wherein, The semiconductor device further includes: An interlayer dielectric layer is located on the substrate, and the first conductive plug penetrates the interlayer dielectric layer; A plurality of second conductive plugs are located within the interlayer dielectric layer and penetrate the interlayer dielectric layer, and the plurality of second conductive plugs are electrically connected to the source region, the drain region and the gate, respectively.

7. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A device structure is formed on the substrate, the device structure including a source region, a drain region, and a gate located on the substrate between the source region and the drain region; An isolation structure is formed in the substrate between the drain region and the gate; Along the drain region toward the gate direction, a plurality of first conductive plugs electrically connected to the substrate are disposed within the isolation structure; Multiple first conductive plugs are used to couple gradient voltages to form a gradient electric field in the region beneath the isolation structure.

8. The method as described in claim 7, characterized in that, The provision of multiple conductive plugs electrically connected to the substrate includes: The isolation structure is photolithographically developed to form a contact hole pattern; Based on the aforementioned contact hole pattern, contact holes are formed within the isolation structure by dry etching. A diffusion barrier layer and a filler metal layer are deposited within the contact hole to form a first conductive plug.

9. The method as described in claim 8, characterized in that, Prior to the deposition diffusion barrier layer, the following also includes: An insulating layer is formed on the inner surface of the contact hole by atomic layer deposition; Remove the insulating layer at the bottom of the contact hole, while retaining the insulating layer on the sidewall of the contact hole.

10. The method as described in claim 7, characterized in that, Before the provision of a plurality of first conductive plugs electrically connected to the substrate within the isolation structure, the method further includes: An interlayer dielectric layer is formed on the surface of the substrate, the interlayer dielectric layer covering the device structure and the surface of the isolation structure; the first conductive plug penetrates the interlayer dielectric layer.

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