Low-stress dielectric material for glass substrate and CTE gradient design method thereof

Abstract

The invention discloses a low-stress dielectric material for a glass substrate and a CTE gradient design method thereof, the low-stress dielectric material is formed by mixing at least two basic dielectric material components with different thermal expansion coefficients in proportion, the thermal expansion coefficient of each basic dielectric material layer is in gradient change from the first layer in contact with the glass substrate to the Nth layer in contact with the outermost layer, the difference value between the thermal expansion coefficient of the first layer and the thermal expansion coefficient of the glass substrate is less than or equal to 0.5 ppm / K; the thermal expansion coefficient of the Nth layer matches the function requirement of the top layer of the device; the difference value of thermal expansion coefficients between adjacent layers is not greater than a preset threshold value (1.0-2.0 ppm / K); the gradient change is realized by regulating and controlling the volume fraction of the components of the basic dielectric material of each layer, and the aim is to minimize the internal and interface thermal stress of the multiple dielectric layers. According to the low-stress dielectric material, the components and the thermal expansion coefficient of the low-stress dielectric material are improved, so that the thermal stress level of an upper-layer medium of a glass substrate can be remarkably reduced, and the compatibility among various materials is higher, the adaptability is stronger, and the light transmittance is better.

Description

Technical Field

[0001] This invention relates to the field of functional coating and glass substrate interface engineering technology, specifically to a low-stress dielectric material for glass substrates and its CTE (Coefficient of Thermal Expansion) gradient design method. More specifically, it relates to a dielectric material formulation and its gradient design method for reducing thermal stress caused by the mismatch of the coefficient of thermal expansion (CTE) between the glass substrate and the coated dielectric layer. It is particularly suitable for applications with high requirements for thermomechanical reliability, such as advanced packaging, flat panel displays, and optical devices. Background Technology

[0002] Glass substrates are widely used in flat panel displays (LCD, OLED, Micro-LED), semiconductor packaging interposers / intercalators, solar cell cover plates, and optical component substrates due to their excellent optical transparency, surface flatness, insulation, chemical stability, and low cost. In these applications, it is often necessary to coat or deposit various functional dielectric layers on the glass substrate, such as insulating layers (SiO2, Si3N4), passivation layers, barrier layers (water and oxygen barrier), optical films (antireflective, anti-reflective), and buffer layers under conductive layers (ITO).

[0003] However, there is usually a significant difference in the coefficient of thermal expansion between glass materials and commonly used inorganic dielectric materials (such as SiO2, Al2O3, Si3N4). During device manufacturing (such as high-temperature deposition and annealing) and service (temperature cycling), this CTE mismatch will generate huge thermal stress at the glass substrate / dielectric layer interface and within the dielectric layer. This stress will lead to a series of serious problems: (1) cracking and peeling of the dielectric coating itself; (2) warping and deformation of the glass substrate, affecting the accuracy of subsequent photolithography or bonding; (3) interface delamination failure; (4) accelerated fatigue failure under temperature cycling, significantly reducing the reliability and lifespan of the device. Especially with the trend of large-size, thin glass substrates and high-density packaging, the thermal stress problem is becoming increasingly prominent.

[0004] Traditional solutions primarily focus on selecting dielectric materials with a single dielectric dielectric layer (CTE) as close as possible to that of the glass substrate, or on modification through the addition of fillers. However, these methods have limitations: firstly, the range of single-material CTEs that perfectly match the glass is narrow, potentially limiting properties such as dielectric constant, hardness, and barrier properties; secondly, even with similar average CTEs, significant stress may still occur at the interface during temperature transients or when temperature gradients are present; and thirdly, adding fillers may affect the material's uniformity, transparency, and processability. Therefore, a new technological approach is urgently needed to more effectively address the thermal stress problem of dielectric layers on glass substrates. Summary of the Invention

[0005] The purpose of this invention is to address the problems in existing technologies, such as coating cracking, substrate warping, and decreased device reliability caused by the mismatch of the coefficient of thermal expansion (CTE) between the glass substrate and the functional dielectric layer. This invention provides a low-stress dielectric material for glass substrates and a CTE gradient design method thereof.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] In a first aspect, a low-stress dielectric material for a glass substrate is provided, comprising a multilayer dielectric layer coated on the surface of the glass substrate, wherein the multilayer dielectric layer is composed of at least two basic dielectric material components with different coefficients of thermal expansion mixed in a certain proportion; from the first layer in contact with the glass substrate to the outermost Nth layer, the coefficients of thermal expansion of each basic dielectric material layer exhibit a gradient change, and satisfying the following: the difference between the coefficient of thermal expansion of the first layer and the coefficient of thermal expansion of the glass substrate is ≤0.5ppm / K; the coefficient of thermal expansion of the Nth layer matches the functional requirements of the top layer of the device; the difference in coefficients of thermal expansion between adjacent layers is not greater than a preset threshold, wherein the preset threshold is 1.0 to 2.0ppm / K; the gradient change is achieved by adjusting the volume fraction of each basic dielectric material component, with the goal of minimizing the internal and interfacial thermal stress of the multilayer dielectric layer.

[0008] This low-stress dielectric material, through improvements to its composition and coefficient of thermal expansion, can significantly reduce the thermal stress level of the upper dielectric layer on a glass substrate. Moreover, it exhibits higher compatibility and adaptability among various materials, better light transmittance, and its precision can be ensured through scientific verification.

[0009] The multilayer dielectric layer of this low-stress dielectric material, through gradient thermal expansion coefficient (CET) design, can reduce the peak thermal stress of each interface by 50% or more (finite element simulation verification), and the volume average von Mises stress does not exceed 30 MPa (ΔT=200℃ condition), effectively solving the problems of coating cracking and glass substrate warping.

[0010] Furthermore, the components of the base medium material are selected from at least two of silicon dioxide, alumina, silicon nitride, titanium dioxide, zirconium oxide, and borosilicate glass, and satisfy any of the following conditions: when silicon dioxide and alumina are combined, the coefficient of thermal expansion of silicon dioxide is 0.5 ppm / K and the coefficient of thermal expansion of alumina is 8.0 ppm / K; when silicon nitride and silicon dioxide are combined, the coefficient of thermal expansion of silicon nitride is 2.8 ppm / K and the coefficient of thermal expansion of silicon dioxide is 0.5 ppm / K.

[0011] Furthermore, the gradient change pattern is a continuous gradient or a stepped gradient, the number of layers N satisfies: 2≤N≤10, and the thickness of each layer is 0.1~5μm.

[0012] Secondly, a CET gradient design method for low-stress dielectric materials used in glass substrates is provided, comprising the following steps:

[0013] Target CTE gradient curve generation: based on the CTE value α of the glass substrate. sub The target CTE value α at the top layer of the device top Given the temperature variation range ΔT, and combining this with the goal of minimizing thermal stress, a target CTE distribution function α is generated from the glass substrate interface to the surface. target(z) ;

[0014] Modeling the relationship between the basic media material component library and CTE: Establish a basic media material component library, and use the Turner model or Kerner model to construct the effective CTE value α of the mixed media material. mix Mapping relationship with volume fraction of basic medium material components:

[0015] α mix = F(f A , f B , ...), where f A +f B +...=1, f A f B These are the volume fractions of components A and B, respectively.

[0016] Constraint settings: Define the preset threshold Δα for adjacent layer CTEs. max and the thermal stress evaluation function Ψ;

[0017] Layered formulation optimization solution: The objective is to minimize the thermal stress evaluation function Ψ, within α... target(z) and Δα max Under constraints, the optimal volume fraction of basic medium material components {f} for each layer is solved using an optimization algorithm. A,k , f B,k , ...},k=1,2,...,N.

[0018] Furthermore, the target CTE distribution function α target(z) It is a linear function: α target(z) = α sub +(α top -α sub )·(z / t); or parabolic function: α target(z) = α sub +(α top -α sub )·(z / t)²; and the thermal stress evaluation function Ψ under this distribution is reduced by 30% or more compared to that of a uniform medium, as verified by the thermoelastic mechanical model.

[0019] Furthermore, the CTE relationship modeling includes:

[0020] Using the Turner model: 1 / α mix = Σ(f i / α i Alternatively, a microstructure-macrostructure CTE correlation database can be established through finite element analysis; when the basic medium material composition includes silicon dioxide and alumina, the mapping relationship is specified as follows: In the formula This indicates the volume fraction of silicon dioxide. This indicates the volume fraction of aluminum oxide.

[0021] Furthermore, the preset threshold Δαmax is determined by the fracture toughness of the base medium material, satisfying 0.5ppm / K≤Δα max ≤2.0ppm / K;

[0022] The thermal stress evaluation function Ψ is defined as: Ψ=w1·max(σ interface )+w2·∫σ vm dV, where w1+w2=1 represents the weighting coefficient, σ interface For the maximum tensile stress at the interface, σ vm V represents the von Mises equivalent stress, and V represents the material volume.

[0023] Furthermore, the optimization algorithm is a sequential quadratic programming method, iteratively solving for local optima that satisfy the Karush-Kuhn-Tucker conditions; or, a genetic algorithm, encoding {f} using chromosomes. A,k A global search is performed using the thermal stress evaluation function Ψ as the fitness function.

[0024] Furthermore, it also includes a gradient formulation verification step: preparing each layer of base dielectric material based on the optimization algorithm solution results, and measuring the CTE value α of each layer of base dielectric material. actual,k If |α actual,k -α target,kIf |>0.3ppm / K, then the CTE relationship modeling should be corrected and re-optimized.

[0025] Thirdly, an electronic device is provided, which is applied to: anti-crack coating on glass substrate of display panel, stress buffer layer of glass transition plate in semiconductor packaging, and anti-reflective coating system of cover glass of photovoltaic module.

[0026] Compared with existing technologies, the beneficial effects of this invention are: 1. By improving its composition and coefficient of thermal expansion, this low-stress dielectric material can significantly reduce the thermal stress level of the upper dielectric layer on the glass substrate. Furthermore, it exhibits higher compatibility and adaptability among various materials, better light transmittance, and its precision can be ensured through scientific verification. 2. The multilayer dielectric layer of this low-stress dielectric material, through gradient coefficient of thermal expansion (CET) design, can reduce the peak thermal stress at each interface by 50% or more (verified by finite element simulation). The volume average von Mises stress does not exceed 30 MPa (ΔT=200℃), effectively solving the problems of coating cracking and glass substrate warping. 3. High material performance compatibility: The CTE control range covers 0.5–80 ppm / K, suitable for soda-lime glass (α-lambda-lime glass). sub ≈90×110 -7 / ℃), borosilicate glass (α) sub ≈33×10 -7 Substrates such as / ℃), and maintain the transmittance of the dielectric layer >92% (550 nm wavelength); 4. The optimization algorithm based on the physical model ensures that the gradient parameters are accurate and controllable, and the measured CTE value of each layer deviates from the target value by <0.3 ppm / K; It supports the implementation of gradient deposition process through slot coating, and the interlayer bonding strength is >15Mpa. Attached Figure Description

[0027] Figure 1 This is a schematic flowchart of the CTE gradient design method for low-stress dielectric materials used in glass substrates according to the present invention. Detailed Implementation

[0028] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] In the description of this invention, it should be noted that the terms "middle," "upper," "lower," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0030] Example 1

[0031] This embodiment provides a low-stress dielectric material for glass substrates, comprising a multilayer dielectric layer coated on the surface of the glass substrate. The multilayer dielectric layer is composed of at least two base dielectric material components with different coefficients of thermal expansion mixed in a specific ratio. From the first layer in contact with the glass substrate to the outermost Nth layer (2≤N≤10), the coefficients of thermal expansion of each base dielectric material layer exhibit a gradient change, satisfying the following: the coefficient of thermal expansion of the first layer (first layer CTE value α1) is similar to the coefficient of thermal expansion of the glass substrate (glass substrate CTE value α). sub The difference between the two layers is ≤0.5ppm / K; the coefficient of thermal expansion of the Nth layer (CTE value α of the Nth layer) is ≤0.5ppm / K. N Matching the top-level functional requirements of the device (target CTE value α at the top level of the device) top The difference in the coefficient of thermal expansion between adjacent layers is not greater than a preset threshold, which is 1.0 to 2.0 ppm / K, or the CTE difference |α| between adjacent layers k and k+1. k -α k+1 |≤Δα max , where Δα max The preset threshold is used; the gradient change is achieved by adjusting the volume fraction of the basic medium material components in each layer, with the goal of minimizing the thermal stress inside and at the interface of the multilayer medium layer.

[0032] This low-stress dielectric material, through improvements to its composition and coefficient of thermal expansion, can significantly reduce the thermal stress level of the upper dielectric layer on a glass substrate. Moreover, it exhibits higher compatibility and adaptability among various materials, better light transmittance, and its precision can be ensured through scientific verification.

[0033] The multilayer dielectric layer of this low-stress dielectric material, through gradient thermal expansion coefficient (CET) design, can reduce the peak thermal stress of each interface by 50% or more (finite element simulation verification), and the volume average von Mises stress does not exceed 30 MPa (ΔT=200℃ condition), effectively solving the problems of coating cracking and glass substrate warping.

[0034] Because soda-lime glass (CTE ≈ 90×10) -7 / ℃) and silica dielectric layer (CTE ≈ 5×10 -7 The CTE difference for combinations such as ( / ℃) was as high as 85×10 -7 At ℃, the interfacial tensile stress exceeds 100 MPa during temperature cycling, leading to dielectric layer fracture. While existing microcrystalline glass solutions can achieve ultra-low CTE, their maximum application temperature is limited (≤ 600℃), and CTE uniformity deviation is > 0.01×10⁻⁶ during large-scale manufacturing. -6 / K; The pore defects introduced by the filler modification method increase optical haze by more than 15%, which seriously degrades the light transmittance of the display panel.

[0035] Through the design of the basic media material composition of this invention, the CTE control range covers 0.5–80 ppm / K, which is suitable for soda-lime glass (α). sub ≈90×10 -7 / ℃), borosilicate glass (α) sub ≈33×10 -7 The glass substrates are designed for temperatures of 100°C and 100°C, and the transmittance of the dielectric layer is maintained at more than 92% (550nm wavelength). Moreover, the optimization algorithm based on the physical model ensures that the gradient parameters are accurately controllable, and the measured CTE values ​​of each layer deviate from the target values ​​by less than 0.3 ppm / K. It supports the implementation of a slit coating gradient deposition process, and the interlayer bonding strength is greater than 15MPa.

[0036] Furthermore, the components of the basic dielectric material are selected from at least two of silicon dioxide (SiO2, coefficient of thermal expansion of 0.5 ppm / K), alumina (Al2O3, coefficient of thermal expansion of 8.0 ppm / K), silicon nitride (Si3N4, coefficient of thermal expansion of 2.8 ppm / K), titanium dioxide (TiO2, coefficient of thermal expansion of 9.0 ppm / K), zirconium oxide (ZrO2), and borosilicate glass, and satisfy any one of the following conditions: when silicon dioxide and alumina are combined, the coefficient of thermal expansion of silicon dioxide is 0.5 ppm / K, and the coefficient of thermal expansion of alumina is 8.0 ppm / K, i.e. , When silicon nitride and silicon dioxide are combined, the coefficient of thermal expansion of silicon nitride is 2.8 ppm / K, and that of silicon dioxide is 0.5 ppm / K. , .

[0037] Preferably, the effective CTE value α of the hybrid base medium material mix Its relationship with the volume fraction of its components is as follows: ;in + =1.

[0038] Furthermore, the gradient change pattern is a continuous gradient or a stepped gradient, the number of layers N satisfies: 2≤N≤10, and the thickness of each layer is 0.1~5μm.

[0039] Example 2

[0040] This embodiment provides a CET gradient design method for low-stress dielectric materials used in glass substrates, combined with... Figure 1 As shown, it includes the following steps:

[0041] Step 1: Target CTE gradient curve generation: Based on the CTE value α of the glass substrate... sub The target CTE value α at the top layer of the device top Given the temperature variation range ΔT, and combining this with the goal of minimizing thermal stress, a target CTE distribution function α is generated from the glass substrate interface (z = 0) to the surface (z = t). target(z) ;

[0042] Specifically, the target CTE distribution function α target(z) It is a linear function: α target(z) = α sub +(α top -α sub )·(z / t); or parabolic function: α target(z) = α sub +(α top -α sub )·(z / t)²; and the thermal stress evaluation function Ψ under this distribution is reduced by 30% or more compared to that of a uniform medium, as verified by the thermoelastic mechanical model.

[0043] Step 2: Modeling the relationship between the basic media material component library and CTE: Establish a basic media material component library, and use the Turner model or Kerner model to construct the effective CTE value α of the mixed media material. mix Mapping relationship with volume fraction of basic medium material components:

[0044] α mix = F(f A , f B , ...), where f A +f B +...=1, that is, satisfying Σf i =1, f A f B These are the volume fractions of components A and B, respectively.

[0045] Specifically, the Turner model is used: 1 / α mix = Σ(f i / α iAlternatively, a microstructure-macrostructure CTE correlation database can be established through finite element analysis; when the basic medium material composition includes silicon dioxide and alumina, the mapping relationship is specified as follows: In the formula This indicates the volume fraction of silicon dioxide. This indicates the volume fraction of aluminum oxide.

[0046] Step 3, Constraint Setting: Define the preset threshold Δα for adjacent layer CTEs. max and the thermal stress evaluation function Ψ (including the maximum tensile stress at the interface σ) max Or the volume-average von Mises stress σ vmavg );

[0047] Specifically, the preset threshold Δαmax is determined by the fracture toughness of the base medium material, satisfying 0.5ppm / K≤Δα max ≤2.0ppm / K;

[0048] The thermal stress evaluation function Ψ is defined as: Ψ=w1·max(σ interface )+w2·∫σ vm dV, where w1+w2=1 represents the weighting coefficient, σ interface For the maximum tensile stress at the interface, σ vm V represents the von Mises equivalent stress, and V represents the volume.

[0049] Step 4, Layered Formulation Optimization Solution: The objective is to minimize the thermal stress evaluation function Ψ, within α... target(z) and Δα max Under the constraints, the optimal volume fraction {f} of the basic medium material component in each gradient layer (k = 1,2,...,N) is solved by an optimization algorithm. A,k , f B,k , ...};

[0050] Specifically, the optimization algorithm is a sequential quadratic programming (SQP) method, which iteratively solves for local optima that satisfy the Karush-Kuhn-Tucker conditions; or, a genetic algorithm (GA), which encodes {f} using chromosomes. A,k A global search is performed using the thermal stress evaluation function Ψ as the fitness function.

[0051] Furthermore, it also includes step 5, gradient formulation verification: based on the optimization algorithm solution, each layer of base dielectric material is prepared, and the CTE value α of each layer of base dielectric material is measured. actual,k If |α actual,k -α target,k If |>0.3ppm / K, then the CTE relationship modeling should be corrected and re-optimized.

[0052] Furthermore, an electronic device is provided, which is applied to: anti-crack coating on glass substrate of display panel, stress buffer layer of glass transition plate in semiconductor packaging, and anti-reflective coating system of cover glass of photovoltaic module.

[0053] Example 3

[0054] This embodiment takes a three-layer gradient dielectric layer as an example to further illustrate the design method (stepped CTE change).

[0055] (1) Design objectives

[0056] Glass substrate type: Borosilicate glass (α) sub =3.3ppm / K); Top-level device functional requirements: Matching the upper ITO conductive layer (target α) top =5.0 ppm / K); Temperature range: ΔT=200℃ (-40℃ to 160℃); Number of layers: N=3 (the first layer is the substrate side, the second layer is the middle layer, and the third layer is the top layer); Constraint: CTE difference between adjacent layers ≤1.0ppm / K.

[0057] (2) Gradient design process

[0058] S1: The target CTE curve is generated using a linear transition function: α target(z) =3.3+(5.0-3.3)×(z / t); Stratified target values: First layer (z=0): α1=3.3ppm / K; Second layer (z = t / 2): α2= 4.15 ppm / K; Third layer (z = t): α3= 5.0 ppm / K.

[0059] S2: Establish material models: Basic media materials: SiO2 (α=0.5ppm / K), Al2O3 (α=8.0ppm / K); Turner model: .

[0060] S3: Set optimization constraints: CTE difference between adjacent layers: |α1-α2|≤1.0, |α2-α3|≤1.0; Stress function: Ψ=0.5×max(σ interface )+0.5×∫σ vm dV.

[0061] S4: Optimization results of sequential quadratic programming (SQP) solution. The volume fraction of Al2O3 and the calculated CTE (ppm / K) for each layer are as follows: first layer 0.18, 3.30; second layer 0.32, 4.20; third layer 0.42, 5.02.

[0062] (3) Material preparation and performance verification

[0063] Sol preparation: First layer sol: Tetraethyl orthosilicate (TEOS): Aluminum isopropoxide (AIP) molar ratio = 8.2:1.8; Second layer sol: TEOS:AIP = 6.8:3.2; Third layer sol: TEOS:AIP = 5.8:4.2.

[0064] Coating process: a. Cleaning of borosilicate glass substrate (UV-O3 treatment for 10 min); b. Spin coating of the first layer of sol (3000 rpm, 30 s), pre-baking at 150℃ for 5 min; c. Repeat coating of the second and third layers; d. Programmed temperature sintering: 5℃ / min to 500℃, holding for 1 h.

[0065] Performance Testing: Comparison of Test Item Results (Uniform Layer): Interface bonding strength (scratch) was 18.5 MPa and 12.1 MPa respectively; Warpage after thermal cycling (ΔT = 200℃) curvature was 0.03 mm respectively. -1 0.12mm -1 The transmittance at 550 nm was 93.7% and 88.2%, respectively.

[0066] Example 4

[0067] This embodiment uses a five-layer gradient dielectric layer as an example to further illustrate the design method (continuous CTE gradient).

[0068] (1) Design objectives

[0069] Glass substrate type: Soda-lime glass (α-glucopyrano) sub =9.0ppm / K); Top-level functional requirements of the device: α top =2.0ppm / K (optical film requirements); Process selection: slot coating composition gradient deposition.

[0070] (2) Gradient design process

[0071] S1: Parabolic target curve: α target(z) =9.0+(2.0-9.0)×(z / t)²;

[0072] S2: Material library expansion adds Si3N4 (α=2.8ppm / K), relational model: ;

[0073] S3: Set optimization constraints: CTE difference between adjacent layers: |α1-α2|≤1.0, |α2-α3|≤1.0; Stress function: Ψ= 0.5×max(σ interface ) + 0.5×∫σ vm dV;

[0074] S4: Optimization results obtained by the Genetic Algorithm (GA) (partial), including SiO2 fraction, Si3N4 fraction, and α at each layer. mix The ppm / K values ​​were as follows: first layer (z=0) 0.05, 0.95, 8.95; third layer (z=0.5t) 0.38, 0.62, 4.12; and fifth layer (z = t) 0.92, 0.08, 2.03.

[0075] (3) Implementation of slot coating process

[0076] Equipment configuration: Dual-channel coating head (Channel A: High SiO2 sol; Channel B: High Si3N4 sol); Real-time flow control system (accuracy ±0.1 μL / min); Gradient deposition process: a. Set flow ratio function: f B(z) = 0.95- 0.87×(z / t)²; b. Substrate transfer speed: 2mm / s; c. Wet film thickness: 50μm, single layer thickness after drying: 1.2μm.

[0077] Actual performance: CTE deviation of each layer: < 0.25 ppm / K (XRD-Rietveld refinement verification); Thermal shock test (-40℃~125℃, 500 cycles): zero cracking; Interface thermal stress: peak value 41 MPa (finite element simulation), a 54% decrease compared to the uniform layer (89 MPa).

[0078] Comparative Example

[0079] Traditional homogeneous dielectric layer failure analysis:

[0080] Sodium-calcium glass (α) sub =9.0ppm / K) coated with a uniform SiO2 layer (α mix For example, (=0.5ppm / K):

[0081] Thermal stress simulation: At ΔT=100℃, the interfacial tensile stress reaches 127MPa, which is greater than the fracture strength of SiO2 (70MPa).

[0082] Experimental results: The warpage of the substrate after sintering at 200℃ was 0.28mm. -1 After 50 thermal cycles, the coating edge peels off (peeling area > 30%).

[0083] Summary of the advantages of gradient design in this invention:

[0084] The performance data for Examples 3, 4, and the comparative example are as follows: interfacial bonding strength (MPa) is 18.5, 19.2, and 9.8, respectively; warpage after thermal cycling (mm) is... -1 The values ​​were 0.03, 0.02, and 0.28, respectively; the transmittance (%) were 93.7, 94.1, and 91.5, respectively (filler modification).

[0085] The above embodiments and comparative examples demonstrate that the gradient CTE design of the present invention can simultaneously achieve low stress, high light transmittance, and strong bonding, providing a reliable solution for glass-based electronic devices.

[0086] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A low-stress dielectric material for glass substrates, characterized in that, The device includes a multilayer dielectric layer coated on the surface of a glass substrate. The multilayer dielectric layer is composed of at least two basic dielectric material components with different coefficients of thermal expansion mixed in a specific ratio. From the first layer in contact with the glass substrate to the outermost Nth layer, the coefficients of thermal expansion of each basic dielectric material layer exhibit a gradient change, satisfying the following conditions: the difference between the coefficient of thermal expansion of the first layer and the coefficient of thermal expansion of the glass substrate is ≤ 0.5 ppm / K; the coefficient of thermal expansion of the Nth layer matches the functional requirements of the top layer of the device; the difference in coefficients of thermal expansion between adjacent layers is not greater than a preset threshold, which is 1.0–2.0 ppm / K. This gradient change is achieved by adjusting the volume fraction of each basic dielectric material component, with the goal of minimizing internal and interfacial thermal stress within the multilayer dielectric layer.

2. The low-stress dielectric material for glass substrates according to claim 1, characterized in that, The components of the base medium material are selected from at least two of silicon dioxide, alumina, silicon nitride, titanium dioxide, zirconium oxide, and borosilicate glass, and satisfy any of the following conditions: when silicon dioxide and alumina are combined, the coefficient of thermal expansion of silicon dioxide is 0.5 ppm / K and the coefficient of thermal expansion of alumina is 8.0 ppm / K; when silicon nitride and silicon dioxide are combined, the coefficient of thermal expansion of silicon nitride is 2.8 ppm / K and the coefficient of thermal expansion of silicon dioxide is 0.5 ppm / K.

3. The low-stress dielectric material for glass substrates according to claim 1, characterized in that, The gradient change pattern is a continuous gradient or a step gradient, the number of layers N satisfies: 2≤N≤10, and the thickness of each layer is 0.1~5μm.

4. The CET gradient design method for low-stress dielectric materials for glass substrates according to any one of claims 1 to 3, characterized in that, Includes the following steps: Target CTE gradient curve generation: based on the CTE value α of the glass substrate. sub The target CTE value α at the top layer of the device top Given the temperature variation range ΔT, and combining this with the goal of minimizing thermal stress, a target CTE distribution function α is generated from the glass substrate interface to the surface. target(z) ; Modeling the relationship between the basic media material component library and CTE: Establish a basic media material component library, and use the Turner model or Kerner model to construct the effective CTE value α of the mixed media material. mix Mapping relationship with volume fraction of basic medium material components: α mix = F(f A , f B , ...), where f A +f B +...=1, f A f B These are the volume fractions of components A and B, respectively. Constraint settings: Define the preset threshold Δα for adjacent layer CTEs. max and the thermal stress evaluation function Ψ; Layered formulation optimization solution: The objective is to minimize the thermal stress evaluation function Ψ, within α... target(z) and Δα max Under constraints, the optimal volume fraction of basic medium material components {f} for each layer is solved using an optimization algorithm. A , k , f B , k , ...},k=1,2,...,N.

5. The CET gradient design method for low-stress dielectric materials for glass substrates according to claim 4, characterized in that, The target CTE distribution function α target(z) It is a linear function: α target (z)=α sub +(α top -α sub )·(z / t); or parabolic function: α target (z) = α sub +(α top -α sub )·(z / t)²; and the thermal stress evaluation function Ψ under this distribution is reduced by 30% or more compared to that of a uniform medium, as verified by the thermoelastic mechanical model.

6. The CET gradient design method for low-stress dielectric materials for glass substrates according to claim 4, characterized in that, The CTE relationship modeling includes: Using the Turner model: 1 / α mix =Σ(f i / α i Alternatively, a microstructure-macrostructure CTE correlation database can be established through finite element analysis; when the basic medium material composition includes silicon dioxide and alumina, the mapping relationship is specified as follows: In the formula This indicates the volume fraction of silicon dioxide. This indicates the volume fraction of aluminum oxide.

7. The CET gradient design method for low-stress dielectric materials for glass substrates according to claim 4, characterized in that, The preset threshold Δα max The value is determined by the fracture toughness of the base medium material, satisfying 0.5ppm / K≤Δα max ≤2.0ppm / K; The thermal stress evaluation function Ψ is defined as: Ψ=w1·max(σ interface )+w2·∫σ vm dV, where w1+w2=1 represents the weighting coefficient, σ interface For the maximum tensile stress at the interface, σ vm V represents the von Mises equivalent stress, and V represents the material volume.

8. The CET gradient design method for low-stress dielectric materials for glass substrates according to claim 4, characterized in that, The optimization algorithm is a sequential quadratic programming method, iteratively solving for local optima that satisfy the Karush-Kuhn-Tucker conditions; or, a genetic algorithm, encoding {f} using chromosomes. A,k A global search is performed using the thermal stress evaluation function Ψ as the fitness function.

9. The CET gradient design method for low-stress dielectric materials for glass substrates according to claim 4, characterized in that, It also includes a gradient formulation verification step: preparing each layer of base dielectric material based on the optimization algorithm solution results, and measuring the CTE value α of each layer of base dielectric material. actual,k If |α actual,k -α target,k If |>0.3ppm / K, then the CTE relationship modeling should be corrected and re-optimized.

10. The low-stress dielectric material for glass substrates according to any one of claims 1 to 3, characterized in that, Electronic devices made from the low-stress dielectric material are used in: anti-crack coatings for glass substrates of display panels, stress buffer layers for glass transition plates in semiconductor packaging, and anti-reflective coatings for cover glass of photovoltaic modules.

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