Module and method applied to FPGA remote upgrade configuration data integrity verification

Abstract

The invention discloses a module and a method applied to FPGA (Field Programmable Gate Array) remote upgrade configuration data integrity verification. The module and the method are realized by FPGA logic resources. The configuration data integrity verification module comprises a message filling module, a message expansion function module, a compression iteration module, a constant parameter matrix and a top layer control module. The message filling module is used for receiving original configuration data; the message expansion function module is used for expanding the message blocks output by the message filling module; the compression iteration module is used for hash compression operation; the constant parameter matrix is used for storing constant values required by compression operation; and the top layer control module is used for completing the connection of the sub-modules. Compared with the existing technical scheme, the scheme can realize the integrity verification problem of the configuration data generated by random errors and malicious tampering; by adopting the mode of'pipeline + iteration ', the real-time performance and the low-delay characteristic are ensured, the consumption of the FPGA logic resources by the module is reduced, and the FPGA logic resources can be flexibly deployed on the small-capacity FPGA.

Description

Technical Field

[0001] This invention relates to the field of embedded system data integrity verification technology, and in particular to a module and method for verifying the integrity of FPGA remote upgrade configuration data. Background Technology

[0002] In high-security and high-reliability application scenarios, the configuration files and bitstream files of FPGA chips in existing embedded edge devices must ensure data integrity (no tampering, no transmission errors) throughout the entire lifecycle of remote transmission, download, storage and power-on loading to prevent startup loading failure and program function errors due to abnormal configuration data. In the existing technology, the following three methods are mainly used to verify the integrity of configuration data during FPGA remote upgrade: (1) CRC check: Add a CRC check code to the end of the configuration data. After receiving the configuration data, calculate the CRC check code generated by the received data and compare it with the CRC check code attached to the end of the data to determine whether the received data is correct; (2) Use a multi-mirror mechanism to divide the Flash into Golden area and Update area. Store the remote upgrade data in the Update area and load the program in the Update area by default. If the loading fails, it will fall back to the Golden area; (3) Use a frame protocol verification and retransmission mechanism. Use a frame protocol with verification (such as UDP+CRC) during the remote upgrade process. After the receiving end verifies, it confirms that it is correct or requests retransmission.

[0003] While existing technologies can verify the integrity of configuration data during remote upgrades, they still have certain technical defects. (1) CRC check can only detect random errors and cannot resist malicious tampering. Attackers can modify configuration data or bit streams while keeping the CRC check value unchanged. (2) The multi-mirror mechanism can only determine whether the data is complete when the upgrade data is reloaded after the remote upgrade data is received. Even if the loading is successful, it cannot guarantee that the program function is completely correct. (3) The frame protocol verification and retransmission mechanism can retransmit when there is a data receiving error, ensuring that the configuration data received through remote upgrade can pass the verification. However, it still cannot guarantee that the program function is correct.

[0004] Therefore, in view of the shortcomings of existing technologies, this paper proposes a module and method for verifying the integrity of configuration data during remote upgrades of FPGAs, taking into account the properties of hash functions. Summary of the Invention

[0005] 1. Technical problems to be solved

[0006] To address the problems existing in the background technology, the present invention provides a module and method for verifying the integrity of configuration data during remote upgrades of FPGAs. This module enables real-time calculation during data reception while ensuring the quality of data integrity verification, achieving ultra-low latency data integrity verification and providing accurate verification results upon completion of configuration data reception. Compared to existing technologies, this method can accurately verify data integrity against malicious tampering and eliminates the need for readback of configuration data and the development of complex frame protocols. It can meet the diverse needs of embedded edge devices for configuration data integrity verification in high-security and high-reliability scenarios such as electronic warfare and secure communication.

[0007] This invention relates to the field of communication security and data integrity verification, and particularly to the design and optimization technology of a configuration data integrity verification module for remote upgrades of FPGAs. Specifically, the solution of this invention can meet the requirements of embedded edge devices for configuration data integrity verification during remote upgrades, and is widely applicable to security scenarios such as configuration data integrity verification and identity authentication in military special electronics, airborne equipment, and underwater detection equipment.

[0008] 2. Technical solution of the invention

[0009] 2.1 A module for verifying the integrity of configuration data during remote upgrades of FPGAs;

[0010] The FPGA remote upgrade configuration data integrity verification module is implemented based on FPGA hardware logic resources and includes:

[0011] The message population module is used to receive raw configuration data from external input, populate the data, generate a populated message, and output it.

[0012] The message expansion function module is used to expand the message blocks output by the message filling module, expanding each message block into several fixed-length extended message words;

[0013] The compression iteration module takes the extended message word, hash vector, and constant parameter matrix output by the message expansion function module as input, and outputs the compressed hash value through several rounds of hash compression operations.

[0014] A constant parameter matrix is ​​used to store the constant parameters required for several rounds of hash operations;

[0015] The top-level control module connects the message filling module, message extension function module, compression iteration module, and constant parameter matrix, and also encapsulates the module's external interfaces.

[0016] The message filling module includes:

[0017] A data validity flag register is used to indicate whether the currently output data is valid;

[0018] A message end flag register is used to indicate that the currently output data is the last data in the message;

[0019] A message start flag register is used to indicate that the currently output data is the first data in the message;

[0020] A data register is used to output message data;

[0021] A data receive ready register is used to indicate that the message filling module is currently ready to receive data;

[0022] A counter is used to count the length of each message block in the entire message;

[0023] A message length register is used to store the length of the received message;

[0024] A populated control state machine that implements combinational logic operations and sequential logic control processes for message population modules.

[0025] The message extension function module includes:

[0026] A combinational logic circuit with a function σ0(x) consists of two XOR operations, a register, and three bit concatenation operations;

[0027] A combinational logic circuit with function σ1(x) consists of two XOR operations, a register, and three bit concatenation operations;

[0028] One hundred and twenty-eight data registers are used to buffer a complete message block;

[0029] A data counter used to count the number of data items;

[0030] A data buffer end flag register is used to indicate the end of the data buffer;

[0031] Sixteen extended message word registers are used for pipelined storage of extended message words;

[0032] An extended message word validity flag register is used to indicate whether the currently output extended message word is valid;

[0033] An extended message word counter is used to count the number of extended message words.

[0034] The compression iteration module includes:

[0035] A combinational logic circuit with the function Maj(x,y,z) consists of two XOR operations, three AND operations, and three registers.

[0036] A Ch(x,y,z) function combinational logic circuit, which consists of an XOR operation, an NOT operation, two AND operations, and three registers;

[0037] A combinational logic circuit with a ∑0(x) function, which consists of two XOR operations, a register, and three bit concatenation operations;

[0038] A ∑1(x) function combinational logic circuit, which consists of two XOR operations, a register, and three bit concatenation operations;

[0039] Seven adders are used to perform data addition operations;

[0040] A round counter is used to count the number of rounds of compression.

[0041] A hash vector register is used to store the hash value output by the current compression operation;

[0042] A hash vector cache register is used to cache the hash value output from the previous round of compression operation;

[0043] A hash initialization vector register is used to store the initial value of the hash vector in the first round of compression operations for the entire message;

[0044] A round-end flag register serves as a marker indicating the end of a multi-round compression operation.

[0045] The constant parameter matrix includes:

[0046] There are eighty registers, each of which stores a constant value.

[0047] The top-level control module includes:

[0048] A message population and extension module, which consists of a message population module and a message extension function module;

[0049] A hash compression operation module, which consists of a compression iteration module and a constant parameter matrix;

[0050] One AXI4-stream port is used by the data integrity verification module to receive message data input from other modules;

[0051] A message digest output port is used to output the hash vector value of the message after hash compression.

[0052] A message digest validity port is used to indicate whether the currently output hash vector value is valid.

[0053] 2.2 A method for verifying the integrity of configuration data during remote upgrades of FPGAs, the method comprising:

[0054] (1) Message population stage

[0055] During the message stuffing phase, the message stuffing module uses a state machine to stuff the message byte stream input from the upstream module through the AXI4-stream interface. The stuffing mechanism is as follows: first, a byte of 0x80 is added to the end of the message byte stream; then, several bytes of 0x00 are added; finally, a length field is added, ensuring that the length of the entire message after stuffing is a multiple of 1024 bits. The message stuffing module uses a pipelined approach, simultaneously outputting the stuffed message byte stream as it is input.

[0056] (2) Message expansion phase

[0057] The message expansion function module divides the input message byte stream into several message blocks of 1024 bits each. Each message block is then expanded into 80 expanded message words, each 64 bits in size. The module employs a pipelined approach for expansion calculations; the expansion calculation begins as soon as a 1024-bit message word is input, and the expanded message words are then output sequentially from the output port.

[0058] (3) Message compression stage

[0059] During the message compression phase, the compression iteration module performs 80 hash compression operations. The input for each operation is the output value of the previous hash compression operation, along with the extended message word and constant parameters. Compression operations are performed on a message block basis. After each 1024-bit message block is expanded and 80 extended message words are generated, the compression module outputs the final hash value (hash vector) of this compression operation. When the next message word becomes valid, the hash value from the previous 80 rounds of hash compression operations is used as the starting input vector for the next 80 rounds of compression operations. After the compression operation of the last message block in the entire message is completed, the output hash value is the digest of the entire message. At this point, a single-cycle high pulse will be output as the hash vector validity flag.

[0060] 3. Beneficial effects

[0061] Compared with the prior art, the advantages of this invention are:

[0062] (1) The entire data integrity verification calculation process is automatically completed by hardware logic circuits without the need for software participation, and has high real-time performance and reliability; (2) The verification module adopts a combination of "pipeline + iteration" to reduce the consumption of logic resources while ensuring low latency, so that the data integrity verification module can be deployed on low-capacity FPGAs; (3) It can verify the data integrity caused by random errors and malicious tampering, solving the problem that existing technologies cannot resist malicious tampering; (4) The verification result can be given as soon as the configuration data is received, without the need to read back the configuration data to perform the verification. Attached Figure Description

[0063] Figure 1 Application structure diagram of the data integrity verification module configured for this invention;

[0064] Figure 2 This is a flowchart illustrating the data integrity verification module processing structure of the present invention.

[0065] Figure 3 This is a structural diagram of the data integrity verification module of the present invention;

[0066] Figure 4 This invention provides a message-filling state machine.

[0067] Figure 5 The message block byte stream and extended words W0~W of this invention 15 Correspondence;

[0068] Figure 6 This is the iterative structure of the compression function in this invention;

[0069] Figure 7 This is the interface for calling the top-level module of this invention after encapsulation.

[0070] Explanation of reference numerals in the attached diagram: 1. Remote transmitting terminal; 2. Receiving antenna; 3. Wireless receiving module; 4. FPGA chip; 5. FPGA configuration Flash. Detailed Implementation

[0071] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0072] The application structure diagram of this invention is as follows: Figure 1 As shown, the overall processing flow of the present invention is as follows: Figure 2As shown in the diagram, the message input in byte stream format is first padded (formatted input message) to a multiple of 1024 bits in length. Then, the message is divided into blocks of 1024 bits each, resulting in block 1, block 2, ..., block N. Next, the message blocks are fed into the round operation and summation unit. After the round operation and summation are completed, the result of the hash compression operation (512-bit hash vector) is output. This hash compression result serves as the input for the next round operation and summation module. This process continues until the last message block N completes its round operation and summation. The output hash vector is the message digest for this message. The round operation and summation unit in the processing flow diagram consists of three modules: a message expansion function module, a compression iteration module, and a constant parameter matrix. The design employs a combination of pipelined and iterative methods, significantly reducing hardware logic resource consumption while ensuring low latency, allowing implementation on small-capacity FPGAs. Furthermore, this module does not require additional hard core support, improving its versatility.

[0073] The data integrity verification module described in the specific implementation is based on hardware logic resources in the FPGA, including a message expansion function module, a compression iteration module, a constant parameter matrix, and a top-level control module, the structure of which is as follows: Figure 3 As shown, these modules correspond to the various steps in the hardware components and methods described in the invention.

[0074] The message filling module is used to fill the message byte stream input from the AXI4-stream interface, ensuring it is a multiple of 1024 bits in length. The filling process consists of three steps: first, filling with one byte of 0x80; then, filling with several bytes of 0x00; and finally, filling with a 128-bit length field. After filling, the message is divided into blocks of 1024 bits each, and these blocks are sequentially sent to the message extension function module. The message filling process is implemented using a state machine design, and the state transition diagram of the entire state machine is shown below. Figure 4 As shown in the diagram. Initially, the state machine is in an idle state. When the last data flag is detected as valid, it jumps to the "Receive Message Byte_1" state. When the data validity flag is detected, it jumps to the "Receive Message Byte_2" state. After jumping to "Receive Message Byte_1", it receives one byte of message information, then enters the "Fill 0x80" state, followed by the "Fill 0x00" state. After 0x00 is filled, it enters the "Fill Length Field" state. After the length is filled, it enters the "End State" and then returns to the "Idle State". After jumping to the "Receive Message Byte-2" state, it continuously receives the message byte stream in this state until the last data flag is valid, completing the message data reception and returning to the "Fill 0x80" state.

[0075] The message filling module includes:

[0076] A data validity flag register is used to indicate whether the currently output data is valid. The register has a bit width of 1 bit.

[0077] A message end flag register is used to indicate that the currently output data is the last data in the message. The register has a bit width of 1 bit.

[0078] A message start flag register is used to indicate that the currently output data is the first data in the message. The width of this register is 1 bit.

[0079] A data register, used to output message data, has a width of 1024 bits;

[0080] A data receive ready register is used to indicate whether the message filling module can receive data. When the value of the register is 1, it means that data can be received, and when it is 0, it means that data cannot be received. The width of this register is 1 bit.

[0081] A counter is used to count the length of each message block in the entire message, in bytes. This register is 8 bits wide.

[0082] A message length register is used to store the length of the received message; the register has a bit width of 128 bits.

[0083] A populated control state machine is used to implement the combinational logic operations and sequential logic control process of the message population module. The state machine consists of 7 states.

[0084] The message expansion function module is used to perform expansion operations on each 1024-bit message block output by the message filling module. When the message filling module outputs a complete message block (1024 bits), the message expansion function module immediately latches the message block and simultaneously divides the message block into the first 16 expansion words W0 to W16. 15 The correspondence between message blocks and extended words is as follows: Figure 5 As shown, byte0 is the first input byte in the message stream. Next, extended word output, extended iteration calculation, and extended word shifting are performed. At the rising edge of each clock cycle, an extended word (64 bits) is output from W0, and a shift is performed simultaneously. The shift relationship is: W... t =W t:1 (0≤t≤14); W 15 =σ1(W 14 )+W9+σ0(W1)+W0, until 80 extended words are shifted and output; where: ROTR n (x): indicates that x is circularly shifted right by n positions, with the shifted-out portion placed in the most significant bit; SHR n (x): indicates that x is shifted right by n positions, the shifted-out part is discarded and the high-order bits are filled with 0; This indicates a bitwise XOR operation.

[0085] The message extension function module includes:

[0086] A combinational logic circuit with a σ0(x) function, consisting of two XOR operations, a register, and three bit concatenation operations, performs a linear transformation on the input value. The input data width of the combinational logic circuit is 64 bits, and the output data width is 64 bits.

[0087] A combinational logic circuit with a σ1(x) function, consisting of two XOR operations, a register, and three bit concatenation operations, performs a linear transformation on the input value. The input data width of the combinational logic circuit is 64 bits, and the output data width is 64 bits.

[0088] One hundred and twenty-eight data registers are used to buffer a complete message block, and each register has a bit width of 8 bits;

[0089] A data counter is used to count the number of data items; the data counter has a bit width of 8 bits.

[0090] A data buffer end flag register is used to indicate the end of the data buffer. When the data buffer ends, the value of the register becomes 1 and is automatically cleared to 0 when the rising edge of the next clock arrives. The width of the flag register is 1 bit.

[0091] Sixteen extended message word registers (W0~W 15 This register is used for pipelined storage of the expanded message word. Each register is 64 bits wide. During expansion calculations, W0 to W1 are refreshed at the rising edge of each clock cycle according to the shift formula described above. 15 The value;

[0092] An extended message word validity flag register is used to indicate whether the currently output extended message word is valid. When the value of the register is 1, it means that the extended message word is valid. When the value of the flag register is 0, it means that the extended message word is invalid. The width of this register is 1 bit.

[0093] An extended message word counter is used to count the number of extended message words. The value of the counter is incremented by 1 each time the message extension function module outputs an extended message word. The counter has a bit width of 8 bits.

[0094] The compression iteration module is used to implement 80 rounds of compression operations. In each iteration, the input is the hash value (512 bits) output from the previous compression operation, and the extended message word W... t (64-bit), constant K t (64-bit), the output is the current iteration output of the compression function, and the calculation structure of each round of the compression function is as follows: Figure 6 As shown. A through H are eight 64-bit registers used to store the 512-bit hash value required for iterative operations. They are initialized with initial values ​​H0 through H7; A is initialized with H0, and H is initialized with H7. ∑0, ∑1, Maj, and Ch are function operators.

[0095]

[0096] (H0=64'h6a09e667f3bcc908, H1=64'hbb67ae8584caa73b, H2=64'h3c6ef372fe94f82b, H3=64'ha54ff53a5f1d36f1, H4=64'h510e527fade682d1, H5=64'h9b05688c2b3e6c1f, ​​H6=64'h1f83d9abfb41bd6b, H7=64'h5be0cd19137e2179). The message compression calculation process is as follows:

[0097] (1) If the first message block of the entire message is being processed, the first step is to use eight initial hash values ​​H0, H1, H2, H3, H4, H5, H6, and H7 (each value is 64 bits) as the initial values ​​of the first iteration hash vector in the current 80 iterations, and assign H0 to H7 to the eight registers A, B, C, D, E, F, G, and H respectively for initialization; otherwise, the hash value calculated by the previous message block in the 80-round loop iteration will be used as the initial value of the first iteration hash vector in the current 80-round compression iteration.

[0098] (2) After initialization, perform 80 rounds of iterative calculations on A, B, C, D, E, F, G, and H. The pseudocode is as follows:

[0099] for t=0 to 79

[0100] H=G; G=F; F=E; E=D+T1; D=C; C=B; B=A; A=T1+T2;

[0101] endfor

[0102] Where: T1=h+∑1(E)+Ch(E,F,G)+K t +W t T2=∑0(A)+Maj(A,B,C).

[0103] (3) After completing 80 rounds of iterative calculations, add the obtained A, B, C, D, E, F, G, H to the initial iteration value used in step (1) to obtain the hash value of this operation;

[0104] (4) Repeat the above (1) to (3) operation process until all message blocks are processed. The hash value of the compressed output of the last message block is the hash value of the entire message after compression operation, which is also the message digest.

[0105] The compression iteration module includes:

[0106] A combinational logic circuit with the function Maj(x,y,z) consists of two XOR operations, three AND operations, and three registers. This combinational logic circuit performs linear transformation on the input data, with the input data being three 64-bit registers and the output data having a width of 64 bits.

[0107] A Ch(x,y,z) function combinational logic circuit consists of an XOR operation, an NOT operation, two AND operations, and three registers. This combinational logic circuit performs linear transformation on the input data, with the input data being three 64-bit registers and the output data being 64 bits wide.

[0108] A ∑0(x) function combinational logic circuit, which consists of two XOR operations, a register and three bit concatenation operations, performs linear transformation on the input data, with an input data bit width of 64 bits and an output data bit width of 64 bits;

[0109] A ∑1(x) function combinational logic circuit, which consists of two XOR operations, a register and three bit concatenation operations, performs linear transformation on the input data, with an input data bit width of 64 bits and an output data bit width of 64 bits;

[0110] Seven adders are used to perform data addition operations. Each adder has a bit width of 64 bits and performs 64-bit addition operations in parallel.

[0111] A round counter is used to count the number of rounds of compression operation. The round counter has a bit width of 8 bits.

[0112] A hash vector register is used to store the hash value output by the current compression operation, and its bit width is 64 bits;

[0113] A hash vector cache register is used to cache the hash value output from the previous round of compression operation. When each round of hash operation ends, the value of the cache register is immediately updated to the hash value output from the current round of operation when the rising edge of the clock arrives. Its bit width is 64 bits.

[0114] A hash initialization vector register is used to store the initial value of the hash vector in the first round of compression operation of the entire message. The state of the register is assigned during the initialization process and will remain unchanged thereafter. Its bit width is 64 bits.

[0115] A round-end flag register serves as a marker for the end of 80 rounds of compression operations. When the 80 rounds of compression operations are completed, the value of this register is set to 1, and it is automatically cleared to 0 when the next clock cycle arrives. Its bit width is 1 bit.

[0116] The constant parameter matrix is ​​used to store the constants required during the hash compression operation. Each compression operation consists of 80 rounds of hash compression, so there are 80 constants. In each round of operation, one constant is taken in turn to participate in the hash compression operation until 80 rounds of hash compression are completed.

[0117] The constant parameter matrix includes:

[0118] There are eighty registers, each used to store a constant value, and each register has a bit width of 64 bits.

[0119] The top-level control module is used to connect and integrate the message filling module, message expansion function module, compression iteration module, and constant parameter matrix. The top-level module receives message byte streams from other external modules through the AXI4-stream interface and outputs a message digest after hash compression. The interface for calling the encapsulated top-level module is as follows: Figure 7 As shown.

[0120] The top-level control module includes:

[0121] A message filling and expansion module, consisting of a message filling module and a message expansion function module, implements message filling and expansion, and outputs the expanded message word for use by the compression iteration module;

[0122] A hash compression operation module, which consists of a compression iteration module and a constant parameter matrix, is used to implement 80 rounds of hash compression operations;

[0123] An AXI4-stream port is used by the data integrity verification module to receive message data input from other modules; the AXI4-stream interface includes: a data ID port (axi_tid), a data port (axi_tdata), a data end port (axi_tlast), a data valid port (axi_tvalid), and a data ready port (axi_tready);

[0124] A message digest output port is used to output the hash vector value of the message after hash compression. The width of this port is 512 bits. When the entire message has been hashed and compressed to obtain a message digest, the value of this port is updated on the rising edge of the next clock.

[0125] A message digest valid port is used to indicate whether the currently output hash vector value is valid. When the message digest calculation is complete, the value of this port is kept high for one cycle on the rising edge of the next clock, and then automatically cleared to zero.

[0126] As can be seen from the implementation, the present invention can reduce the consumption of FPGA hardware logic resources while ensuring reliable verification of configuration data integrity. It also features low latency, high real-time performance and reliability, significantly improving the efficiency and security of configuration data integrity verification.

[0127] The above specific embodiments are used to explain and illustrate the present invention, but not to limit the present invention. Any modifications and changes made to the present invention within the spirit and scope of the claims shall fall within the protection scope of the present invention.

Claims

1. A module and method for verifying the integrity of configuration data during remote upgrades of FPGAs, characterized in that: The FPGA remote upgrade configuration data integrity verification module includes: The message population module is used to receive raw configuration data from external input and populate the data. The message expansion function module is used to expand the message blocks output by the message filling module, expanding each message block into several fixed-length extended message words; The compression iteration module performs several rounds of hash compression operations on the input data and outputs the compressed hash value. A constant parameter matrix is ​​used to store the constant parameters required for several rounds of hash compression operations; The top-level control module connects the message filling module, message extension function module, compression iteration module, and constant parameter matrix, and also encapsulates the module's external interfaces.

2. The module and method for verifying the integrity of configuration data during remote upgrade of FPGA according to claim 1, characterized in that: The message filling module fills the input configuration data byte stream so that the length of the filled message is an integer multiple of the specified length, and outputs the filled data to the message extension function module in a message block of the specified length.

3. The module and method for verifying the integrity of configuration data during remote upgrade of FPGA according to claim 1, characterized in that: The message expansion function module takes each message block output by the message filling module as input. When the rising edge of the clock arrives, if the message block is valid, it immediately latches the message block and performs a linear transformation on the input message block. The generated expanded message word is stored in a register, and the expansion operation is performed iteratively. The expanded message word is output at the rising edge of each clock cycle.

4. The module and method for verifying the integrity of configuration data during remote upgrade of FPGA according to claim 1, characterized in that: The compression iteration module takes the extended message word, hash vector, and constant parameter matrix output by the message extension function module as input. When the rising edge of the clock arrives, if the extended message word is valid, it immediately latches the values ​​of the extended message word, hash vector, and constant parameter input port, performs hash compression operation, and outputs the result of the hash operation to the hash vector register on the next rising edge of the clock.

5. The module and method for verifying the integrity of configuration data during remote upgrade of FPGA according to claim 1, characterized in that: The constant parameter matrix consists of several registers with the same bit width. Each register stores a constant required for hash compression operation. When performing hash compression operation, the calculated value is taken out from the constant parameter matrix in sequence.

6. The module and method for verifying the integrity of configuration data during remote upgrade of FPGA according to claim 1, characterized in that: The top-level control module is used to implement signal connections between the message filling module, message expansion function module, compression iteration module, and constant parameter matrix. It also specifies the communication interface and communication protocol when the entire data integrity verification module communicates with other external modules, so as to achieve reliable data interaction.

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