Virtual inertia cooperative control method, system and device for back-to-back modular multilevel converter, and medium

Abstract

The invention relates to the technical field of flexible direct current transmission frequency support control, in particular to a virtual inertia cooperative control method, system, equipment and medium for a back-to-back modular multilevel converter, and the method comprises the steps: dividing a positive frequency deviation scene and a negative frequency deviation scene; when a receiving end system is in a positive frequency deviation scene, sending end active power virtual inertia control is enabled, and receiving end direct current bus voltage virtual inertia control is closed, so that the direct current overvoltage risk is avoided; when a receiving end system is in a negative frequency deviation area, sending end active power virtual inertia control is combined with receiving end voltage virtual inertia control, inertia support is realized, and the voltage stress of each semiconductor power device is effectively reduced; the impedance of the direct current transmission line is considered under the active power virtual inertia control method, and a sending end power instruction value is corrected; the relationship between the AC voltage of the sending and receiving ends and the DC bus voltage is considered under the DC bus voltage virtual inertia control method, and it is ensured that overmodulation does not occur in the DC bus voltage regulation range of the MMC of the sending and receiving ends.

Description

Technical Field

[0001] This invention relates to the field of flexible DC transmission frequency support control technology, and particularly to a virtual inertia collaborative control method, system, device and medium for a back-to-back modular multilevel converter. Background Technology

[0002] With the high penetration of new energy sources, the lack of inertia in power systems has led to increasingly severe frequency stability problems. Back-to-back modular multilevel converters (MMCs), which simulate the rotor dynamics of synchronous machines through virtual inertia control, have become a key technology for improving the frequency support capability of power grids. However, existing methods have serious shortcomings when dealing with scenarios where sudden load reduction causes frequency rises. Conventional virtual inertia control based on DC bus voltage will actively raise the DC voltage to release excess energy, leading to a rise in DC bus voltage, exacerbating the voltage stress on submodule capacitors and the risk of overvoltage in power devices. When a sudden increase in load causes a drop in frequency, two main strategies are employed: active power virtual inertial control and DC voltage virtual inertial regulation. However, these strategies present two major problems: First, the limiting design of DC voltage regulation requires consideration not only of the receiving-end MMC modulation margin but also of the constraint of the sending-end AC voltage on the lower limit of the DC bus voltage, as well as whether the sending-end MMC is over-modulated. Second, the command generation for active power virtual inertial control does not take into account the power voltage drop effect of the DC line impedance, resulting in a deviation between the actual transmitted power and the command, which severely weakens the frequency support speed and accuracy. Especially when the two virtual inertial control methods are combined, the accuracy of the active power command is severely reduced.

[0003] Current technology struggles to reconcile control conflicts under different frequency disturbance scenarios. On one hand, while voltage control can participate in frequency regulation during sudden load reductions, it inevitably introduces overvoltage risks. On the other hand, combined control strategies for sudden load increases lack systematic design and fail to simultaneously meet cross-site modulation constraints and power transmission accuracy requirements. Especially in operating environments with increased frequency fluctuation amplitude and frequency in high-proportion renewable energy grids, these issues lead to a wider range of DC voltage fluctuations in converter stations, a significant increase in equipment overvoltage risks, and a decline in frequency support performance. Summary of the Invention

[0004] This invention provides a virtual inertia collaborative control method, system, device, and medium for a back-to-back modular multilevel converter, which can effectively solve the problems in the background art.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A virtual inertia cooperative control method for a back-to-back modular multilevel converter includes the following steps:

[0007] In response to the deviation of the frequency measurement value of the receiving-end power grid from the rated frequency, determine whether the power grid is in a positive frequency deviation scenario or a negative frequency deviation scenario;

[0008] If the power grid is in a positive frequency deviation scenario, a sending-end active power control command is generated and the output power of the sending-end converter is adjusted, while the virtual inertial control function of the DC bus voltage of the receiving-end converter is disabled.

[0009] If the power grid is in a negative frequency deviation scenario, the sending end active power control command and the receiving end DC bus voltage control command are generated simultaneously, and the DC bus voltage reference value of the receiving end converter is adjusted through the receiving end DC bus voltage control command.

[0010] The generation of the active power control command at the sending end takes into account the power loss of the DC transmission line impedance and compensates for it.

[0011] The generation of the receiving-end DC bus voltage control command is based on the modulation margin of the sending-end and receiving-end converters.

[0012] Furthermore, determining the power grid operating scenario includes the following steps:

[0013] Compare the frequency measurement value f with the rated frequency f N Compare;

[0014] When f≥f N When this occurs, the power grid is determined to be in the positive frequency deviation scenario;

[0015] When f < f N When this occurs, the power grid is determined to be in the negative frequency deviation scenario.

[0016] Furthermore, generating the sending-end active power control command includes the following steps:

[0017] The initial active power adjustment ΔP under the virtual inertial response when the frequency changes is calculated is as follows:

[0018] ΔP=-2H MMC ·P N ·(df / dt) / f N

[0019] Obtain the estimated line power loss ΔP from the impedance of the DC transmission line. line ;

[0020] Combined with rated power P N Generate the compensated active power control command value P at the sending end. ref_send Specifically, it is expressed as follows:

[0021] P ref_send =P N +ΔP+ΔPline ;

[0022] Where df / dt is the rate of change of the measured frequency value, H MMC This is a virtual inertial constant.

[0023] Furthermore, the rate of change of the frequency measurement value, df / dt, is obtained by analyzing the q-axis component U of the receiving-end grid voltage output by the phase-locked loop. recv_q The derivative is obtained as follows:

[0024]

[0025] The initial active power adjustment ΔP is expressed as follows:

[0026]

[0027] Where, k p and k i These are the proportional and integral coefficients of the phase-locked loop.

[0028] Furthermore, based on the DC transmission line impedance R line and the measured value of DC bus voltage at the receiving end U' dc Calculate the estimated line power loss ΔP line Specifically, it is expressed as follows:

[0029]

[0030] Furthermore, the modulation margin is determined based on the safe operating lower limit of DC voltage, which is jointly determined by the AC voltage and modulation capability of the sending and receiving end converters, thus defining the safe lower limit of DC voltage U. dc_limit This includes the following steps:

[0031] Based on the virtual inertial control of the DC bus voltage at the receiving end, and the relationship between the grid voltage and the DC bus voltage at the receiving end, the first constraint value U' of the lower limit of the DC voltage at the receiving end is determined. dc min1 Specifically, it is expressed as follows:

[0032]

[0033] Based on the relationship between the sending-end grid voltage and the DC bus voltage, determine the second constraint value U' of the receiving-end DC voltage lower limit. dc min2 Specifically, it is expressed as follows:

[0034]

[0035] Based on the first and second constraint values ​​of the DC voltage lower limit at the receiving end, the voltage under virtual inertial control of the DC bus voltage is limited to obtain the DC voltage safety lower limit value U. dc_limitSpecifically, it is expressed as follows:

[0036] U dc_limit =0.9min(U′ dcmin1 ,U′ dcmin2 );

[0037] Among them, U recv U' is the effective value of the receiving-end grid voltage. dc U is the measured value of the DC bus voltage at the receiving end. dc_send U is the effective value of the sending-end grid voltage. dc_send min This is the theoretical minimum value of the DC bus voltage at the sending end.

[0038] Furthermore, under full-frequency fluctuation conditions, the receiving-end DC bus voltage satisfies the following constraints:

[0039] U' dc ∈(U dc_limit U dcN ]

[0040] Among them, U dcN The rated DC bus voltage ensures that the voltage stress on the power devices does not exceed their rated withstand voltage level.

[0041] A virtual inertia cooperative control system for a back-to-back modular multilevel converter includes a sending-end converter, a receiving-end converter, a DC link connected therebetween, and a controller configured to perform the above-described method.

[0042] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the above-described method.

[0043] A storage medium having a computer program stored thereon that, when executed by a processor, implements the above-described method.

[0044] The beneficial effects of this invention are as follows:

[0045] In this invention, the frequency modulation method is more flexible when the frequency changes. When the grid frequency is higher than the rated value (positive deviation region), the virtual inertial control of the DC bus voltage at the receiving end is forcibly shut down, and only the active power control at the sending end is retained. This completely blocks the superposition path of voltage rise and excess energy injection in the traditional method. This significantly reduces the peak voltage stress on the submodule under sudden load reduction conditions, eliminating the risk of overvoltage breakdown of power devices from the root cause. At the same time, it maintains the system's inertial response capability to high-frequency disturbances, ensuring that frequency stability is not compromised by control simplification.

[0046] Secondly, the response accuracy is improved by integrating line impedance compensation and dual-end collaborative control. When the grid frequency is lower than the rated value, the active power control at the sending end and the voltage control at the receiving end are enabled simultaneously, and a DC line resistance voltage drop compensation mechanism is embedded in the power command generation. The cross-station modulation constraint mechanism ensures the safety boundary under all operating conditions. By simultaneously considering the coupling constraint of AC voltage on DC bus voltage at the sending end and receiving end converter stations, a voltage limiting model that takes into account the modulation margin on both sides is constructed. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a schematic diagram of the back-to-back MMC topology in this invention;

[0049] Figure 2 This is a schematic diagram of the MMC topology in this invention;

[0050] Figure 3 These are schematic diagrams illustrating virtual inertia control in different scenarios in this invention;

[0051] Figure 4 This is a schematic diagram of the virtual inertial control of active power in this invention;

[0052] Figure 5 This is a schematic diagram of the virtual inertial control of DC bus voltage in this invention;

[0053] Figure 6 This diagram illustrates the conventional control, DC bus virtual inertial control, active power virtual inertial control, and the control frequency response proposed in this invention.

[0054] Figure 7 This is a schematic diagram of DC bus voltage fluctuation.

[0055] Figure 8 This is a schematic diagram of the capacitor voltage fluctuation in the submodule of this invention;

[0056] Figure 9 This is a schematic diagram of DC power fluctuation in this invention;

[0057] Figure 10 This is a schematic diagram of the structure of a computer device. Detailed Implementation

[0058] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0059] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly attached to the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0061] This invention discloses a virtual inertia cooperative control method for a back-to-back modular multilevel converter, based on a three-phase back-to-back MMC converter topology. (See also...) Figure 1 The diagram shows a back-to-back MMC topology; in this back-to-back MMC, there are receiving-end MMC and sending-end MMC, and the grid-side voltages of the sending-end and receiving-end are U and U, respectively. send and U recv The impedance of the DC transmission line is R. line The DC bus voltage on the sending end is U dcsend The DC bus voltage at the receiving end is U' dc ;P L and Q L P1 and Q2 represent the active and reactive power of the load at the receiving end, respectively; P1 and Q1 represent the active and reactive power of the AC side of the MMC at the sending end, respectively; and P2 and Q2 represent the active and reactive power of the AC side of the MMC at the receiving end.

[0062] See further Figure 2 The circuit topology of the MMC shown is as follows: the MMC is divided into three phase units, each phase unit contains two bridge arms, with an inductance of L and a resistance of R. T and L T The resistor and inductor are on the AC grid side; the power of the bridge arm is adjusted by controlling the number of modules connected to the upper and lower bridge arms, and the sum of the number of sub-modules connected to the upper and lower bridge arms is kept at N in any phase unit; the capacitance of each sub-module is C; U sa U sb U scThe three-phase voltage values ​​on the grid side; i sa i sb i sc The three-phase current flowing from the grid into the converter; u ca ,u cb ,u cc i is the AC side output voltage of the converter; pa i pb i pc The current flowing through each phase upper arm of the bridge; u pa ,u pb ,u pc This represents the voltage of each phase's upper bridge arm, which is the sum of the submodule capacitor voltages of each phase's upper bridge arm; i za i zb i zc i represents the current in each phase lower bridge arm; na i nb i nc For each phase current component injected into the DC negative bus confluence point; i dc U is the DC-side current, the total DC current flowing into the converter from the positive bus; dc This is the DC side voltage, i.e., the total voltage between the positive and negative busbars; U dc / 2 represents half the DC side voltage, indicating the voltage between the positive bus and neutral point O, and the voltage between neutral point O and the negative bus.

[0063] The DC bus voltage control side is defined as the receiving-end MMC, used to control the stability of the DC bus voltage. The active and reactive power control side is defined as the sending-end MMC, used to control the transmitted active and reactive power. A phase-locked loop is used to measure the receiving-end grid frequency in real time, and positive and negative frequency deviation regions are further defined based on the frequency deviation. In response to the deviation of the received-end grid frequency measurement value from the rated frequency, it is determined whether the grid is in a positive or negative frequency deviation scenario. The sending-end active power virtual inertial control considers the power voltage drop caused by the DC line impedance; the receiving-end DC bus voltage virtual inertial control considers the modulation margin of both the sending and receiving-end MMCs.

[0064] If the power grid is in a positive frequency deviation scenario, a sending-end active power control command is generated and the output power of the sending-end converter is adjusted, while the virtual inertial control function of the DC bus voltage of the receiving-end converter is disabled. If the power grid is in a negative frequency deviation scenario, a sending-end active power control command and a receiving-end DC bus voltage control command are generated simultaneously, and the reference value of the DC bus voltage of the receiving-end converter is adjusted through the receiving-end DC bus voltage control command.

[0065] Among them, the generation of active power control commands at the sending end takes into account the power loss of the DC transmission line impedance and compensates for it; the generation of DC bus voltage control commands at the receiving end is based on the modulation margin of the converters at the sending and receiving ends.

[0066] In this embodiment, two distinct fault scenarios are identified, thus providing a basis for adopting different, optimal control strategies. Determining the power grid operation scenario includes the following steps:

[0067] Compare the frequency measurement value f with the rated frequency f N Compare;

[0068] When f≥f N When the frequency is higher than normal, it usually indicates that the grid frequency is higher than normal. This is usually caused by a sudden decrease in load or a sudden increase in power generation, resulting in excess kinetic energy in the grid. In this case, the grid is judged to be in a positive frequency deviation scenario.

[0069] When f < f N When the frequency is lower than normal, it indicates that the grid frequency is usually caused by a sudden increase in load or a sudden decrease in power generation, resulting in a shortage of kinetic energy in the grid. In this case, the grid is judged to be in a negative frequency deviation scenario.

[0070] See details Figure 3 The diagram shows virtual inertia control in different scenarios. The load is mainly concentrated in the receiving-end power grid. When a sudden load change occurs in the receiving-end power grid, the frequency on the grid side will change. First, the voltage U on the three-phase grid side will change. recv Sampling is performed, d-axis orientation is used, and the grid frequency f under load change conditions is obtained through a phase-locked loop; the frequency deviation is partitioned, and if f ≥ f N If f < f, it indicates a sudden decrease in load. In this case, only virtual inertial control of active power is enabled, and the influence of line impedance is considered to revise the power command value, thereby obtaining the correction amount of active power; if f < f N This indicates a sudden increase in load. In this case, it is necessary to comprehensively enable virtual inertial control of active power and virtual inertial control of DC bus voltage, and to consider the effects of line impedance and MMC modulation at both ends, so as to generate corrections for instantaneous active power and DC bus voltage.

[0071] In this embodiment, generating the sending-end active power control command includes the following steps:

[0072] The initial active power adjustment ΔP under the virtual inertial response when the frequency changes is calculated is as follows:

[0073] ΔP=-2H MMC ·P N ·(df / dt) / f N

[0074] Obtain the estimated line power loss ΔP from the impedance of the DC transmission line. line ;

[0075] Combined with rated power PN Generate the compensated active power control command value P at the sending end. ref_send Specifically, it is expressed as follows:

[0076] P ref_send =P N +ΔP+ΔP line ;

[0077] Where df / dt is the rate of change of the frequency measurement; H MMC H is a virtual inertial constant. It determines the system's "sensitivity" and "support strength" to frequency changes. MMC The larger the value, the greater the power change will be for the same rate of frequency change.

[0078] Traditional active power control commands ignore the power voltage drop caused by line impedance, resulting in a discrepancy between the command and the actual effect; however, this embodiment requires compensation for this loss when generating the command, thereby achieving precise control.

[0079] Among them, the rate of change of the frequency measurement value df / dt is obtained by analyzing the q-axis component U of the receiving-end grid voltage output by the phase-locked loop. recv_q The derivative is obtained as follows:

[0080] First, the receiving-end MMC grid-side voltage U recv Phase-locked loop (PLL) is performed, i.e.:

[0081]

[0082] Differentiating the above equation, we get:

[0083]

[0084] Therefore, the initial active power adjustment ΔP under the virtual inertial response when the frequency changes is specifically expressed as follows:

[0085]

[0086] Where, k p and k i U represents the proportional and integral coefficients of the phase-locked loop. recv_q It is the q-axis component of the receiving-end grid voltage in a rotating coordinate system. When the phase-locked loop is perfectly phase-locked, U recv_q It should be controlled to 0. Its derivative value contains dynamic information about frequency changes; the rate of change of the frequency measurement df / dt and dU recv_q The voltage is proportional to dt, thus establishing a direct mathematical relationship between the voltage q-axis component and the frequency.

[0087] Secondly, based on the DC transmission line impedance R line and the measured value of DC bus voltage at the receiving end U' dcCalculate the estimated line power loss ΔP line Specifically, it is expressed as follows:

[0088]

[0089] By calculating the line resistance R line Power loss ΔP line This greatly improves the accuracy of compensation. The final precise power command is equal to the rated power P. N In addition to the power adjustment ΔP calculated to respond to frequency changes and the extra power ΔP generated to compensate for line losses, line This eliminates the power deviation actually received at the receiving end.

[0090] See further Figure 4 The diagram shown is a schematic of virtual inertial control for active power. The q-axis component U is obtained by transforming the three-phase voltage at the receiving end through abc / dq. recv_q , will U recv_q The inertia coefficient HMMC and the integral coefficient k of the phase-locked loop PI controller are respectively compared with the integral coefficient k. i Rated power P N Multiply, then divide by 2πf N To obtain the change in active power ΔP when the frequency changes, and then compare it with the rated active power P... N Line active power consumption ΔP line The values ​​are added together and then passed through a power limiter to obtain the command value P of the total active power at the sending end. ref_send .

[0091] In this embodiment, the modulation margin is determined based on the DC voltage safe operating lower limit value U, which is jointly determined by the AC voltage and modulation capability of the sending and receiving end converters. dc_limit This includes the following steps:

[0092] Based on the virtual inertial control of the DC bus voltage at the receiving end, and the relationship between the grid voltage and the DC bus voltage at the receiving end, the first constraint value U' of the lower limit of the DC voltage at the receiving end is determined. dc min1 Specifically, it is expressed as follows:

[0093]

[0094] Based on the relationship between the sending-end grid voltage and the DC bus voltage, determine the second constraint value U' of the receiving-end DC voltage lower limit. dc min2 Specifically, it is expressed as follows:

[0095]

[0096] Based on the first and second constraint values ​​of the lower limit of the DC voltage at the receiving end, the voltage under virtual inertial control of the DC bus voltage is limited to obtain the safe lower limit value U of the DC voltage. dc_limit Specifically, it is expressed as follows:

[0097] U dc_limit =0.9min(U′ dcmin1 ,U′ dcmin2 );

[0098] Among them, U recv U' is the effective value of the receiving-end grid voltage. dc U is the measured value of the DC bus voltage at the receiving end. dc_send U is the effective value of the sending-end grid voltage. dc_send min This is the theoretical minimum value of the DC bus voltage at the sending end.

[0099] See further Figure 5 The diagram shown is a schematic of virtual inertia control of the DC bus voltage. The constant 4 is compared with the virtual inertia coefficient H of the DC voltage. dc , reference capacity S B Frequency variation per unit (f / f) N -1) Multiply by N*C, then divide by N*C, and finally divide by the rated value of the bus voltage U. dcN 2 The values ​​are added together, and finally the arithmetic square root is calculated. The DC voltage limit U is determined by the MMC at the sending and receiving ends to ensure no overshoot. dc min1,2 Thus, the lower limit value U of the safe operation of the receiving-end bus voltage is obtained. dc_limit .

[0100] The core of system safety limiting lies in the theoretical lower limit of the receiving-end DC voltage. This safe lower limit must simultaneously meet the requirements of both the sending and receiving end AC voltages. Otherwise, if the DC voltage falls below this value, one of the MMCs will enter overmodulation due to the inability to maintain the AC voltage, leading to waveform distortion and control instability. Based on the theoretical value, the safe lower limit of the receiving-end DC voltage establishes a more conservative and secure buffer zone, ensuring the system operates flawlessly within the linear modulation region and avoiding overmodulation at both the sending and receiving ends.

[0101] Finally, the real-time frequency of the receiving-end power grid is obtained through a phase-locked loop, and positive and negative deviation regions are divided according to the relationship between the frequency and the rated value. In the positive deviation region, the active power control signal of the sending end is output, and the virtual inertial control of the receiving-end voltage is disabled. In the negative deviation region, the virtual inertial control signals of the sending end power and the virtual inertial control signals of the receiving end voltage are enabled simultaneously. The sending end power command is corrected based on the line impedance, and the receiving end voltage adjustment range is constrained based on the AC and DC voltage relationship of the MMC on both sides.

[0102] Furthermore, the virtual inertia control of the sending-end power is achieved through the outer loop PQ control, circulating current suppression, and capacitor voltage balance control of the sending-end MMC to ensure stable operation of the sending-end MMC; the virtual inertia control of the receiving-end DC bus voltage is achieved through the outer loop constant DC voltage, inner loop current control, circulating current suppression, and capacitor voltage balance control of the receiving-end MMC to ensure stable operation of the receiving-end MMC.

[0103] See details Figure 6 The diagram shows the frequency response of conventional control, DC bus virtual inertial control, active power virtual inertial control, and the control proposed in this invention. Figure 5 The DC bus voltage reference value generated in the process is sent to the receiving end for dual-loop control of outer-loop DC voltage and inner-loop current, and... Figure 4 The generated active power command value at the sending end is sent to the receiving end MMC for PQ control, and the corresponding frequency response is measured. Figure 6 As shown by the black dashed line in the figure, under the control method of the present invention, the frequency change rate is smoother and the minimum frequency amplitude caused by load mutation is also the smallest.

[0104] Under full-frequency fluctuation conditions, the receiving-end DC bus voltage satisfies the following constraint:

[0105] U' dc ∈(U dc_limit U dcN ]

[0106] Among them, U dcN To ensure the DC bus voltage is within rated limits, the voltage stress on the power devices does not exceed their rated withstand voltage level, thus achieving dual optimization of MMC frequency modulation and module voltage stress. Specifically, the sending-end MMC outer loop PQ controller executes the compensated power command; the receiving-end MMC outer loop voltage controller adjusts the DC bus voltage within the limiting range; and the submodule capacitor voltage balance control ensures that the stress on the power devices is always below the rated value U. dcN .

[0107] See Figure 7 The diagram illustrates DC bus voltage fluctuations. A combined virtual inertial control of active power and DC bus voltage is enabled within 15 seconds, reducing the DC bus voltage amplitude and voltage stress. VdcCm-A1 represents the target DC voltage value set during normal system operation. VdcCm-C1 represents the active and controlled reduction of the DC bus voltage by the control strategy of this invention when a sudden load increase occurs. (See also...) Figure 8 The diagram shown illustrates the voltage fluctuation of the submodule capacitor, and its fluctuation is related to... Figure 7 Consistent with, and Figure 7The amplitudes differ by a factor of N; Vcup_SM12 is the capacitor voltage of the submodule during normal system operation, and Vcdn_SM12 is the capacitor voltage of each submodule after the control strategy is reduced; see [link / reference] Figure 9 As shown, this is a schematic diagram of DC power fluctuation. After applying two types of inertial control for 15 seconds, the instantaneous output power of the sending end increases to cope with the sudden increase in load at the receiving end. PdcA1 is the active power transmitted on the DC transmission line when the system is running normally, and PdcC1 is the control strategy instruction for the sending end converter station to rapidly increase its output active power when the load surge occurs.

[0108] Compared with existing technologies, the technical solution of this invention offers more flexible frequency modulation methods when frequencies change. When the grid frequency is higher than the rated value (positive deviation region), by forcibly shutting down the virtual inertial control of the DC bus voltage at the receiving end and retaining only the active power control at the sending end, the superposition path of voltage rise and excess energy injection in traditional methods is completely blocked. This significantly reduces the peak voltage stress borne by the submodule under sudden load reduction conditions, eliminating the risk of overvoltage breakdown of power devices at the source; at the same time, it maintains the system's inertial response capability to high-frequency disturbances, ensuring that frequency stability is not compromised by control simplification.

[0109] The system integrates line impedance compensation and dual-end collaborative control to improve response accuracy. When the grid frequency is lower than the rated value, it simultaneously enables active power control at the sending end and voltage control at the receiving end, and incorporates a DC line resistance voltage drop compensation mechanism in the power command generation. The cross-station modulation constraint mechanism ensures the safety boundary under all operating conditions. By simultaneously considering the coupling constraint of AC voltage on DC bus voltage at the sending and receiving end converter stations, a voltage limiting model that takes into account both-side modulation margins is constructed.

[0110] The present invention also discloses a virtual inertia cooperative control system for a back-to-back modular multilevel converter, including a sending-end converter, a receiving-end converter, a DC link connected therebetween, and a controller. The controller is configured to execute the virtual inertia cooperative control method for the back-to-back modular multilevel converter in the present invention.

[0111] See Figure 10 The diagram shows a structural schematic of a computer device provided in an embodiment of this application. An embodiment of this application provides a computer device 400, including a processor 410 and a memory 420. The memory 420 stores a computer program executable by the processor 410. When the computer program is executed by the processor 410, it performs the method described above.

[0112] This application embodiment also provides a storage medium 430, on which a computer program is stored, and the computer program is executed by a processor 410 to perform the above method.

[0113] The storage medium 430 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0114] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. "A plurality of" means two or more, unless otherwise explicitly specified.

[0115] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0116] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0117] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.

[0118] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0119] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0120] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it includes one or a combination of the steps of the method embodiments.

[0121] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A virtual inertia cooperative control method for a back-to-back modular multilevel converter, characterized in that, Includes the following steps: The frequency measurement f of the receiving-end power grid relative to the rated frequency f N The deviation is used to determine whether the power grid is in a positive or negative frequency deviation scenario. If the power grid is in a positive frequency deviation scenario, a sending-end active power control command is generated and the output power of the sending-end converter is adjusted, while the virtual inertial control function of the DC bus voltage of the receiving-end converter is disabled. If the power grid is in a negative frequency deviation scenario, the sending end active power control command and the receiving end DC bus voltage control command are generated simultaneously, and the DC bus voltage reference value of the receiving end converter is adjusted through the receiving end DC bus voltage control command. The generation of the active power control command at the sending end takes into account the power loss of the DC transmission line impedance and compensates for it. The generation of the receiving-end DC bus voltage control command is based on the modulation margin of the sending-end and receiving-end converters.

2. The virtual inertia cooperative control method for a back-to-back modular multilevel converter according to claim 1, characterized in that, Determining the power grid operation scenario includes the following steps: Compare the frequency measurement value f with the rated frequency f N Compare; When f≥f N When this occurs, the power grid is determined to be in the positive frequency deviation scenario; When f < f N When this occurs, the power grid is determined to be in the negative frequency deviation scenario.

3. The virtual inertia cooperative control method for a back-to-back modular multilevel converter according to claim 1, characterized in that, Generating the sending-end active power control command includes the following steps: The initial active power adjustment ΔP under the virtual inertial response when the frequency changes is calculated is as follows: ΔP=-2H MMC ·P N ·(df / dt) / f N Obtain the estimated line power loss ΔP from the impedance of the DC transmission line. line ; Combined with rated power P N Generate the compensated active power control command value P at the sending end. ref_send Specifically, it is expressed as follows: P ref_send =P N +ΔP+ΔP line ; Where df / dt is the rate of change of the measured frequency value, H MMC This is a virtual inertial constant.

4. The virtual inertia cooperative control method for a back-to-back modular multilevel converter according to claim 3, characterized in that, The rate of change of the frequency measurement value, df / dt, is obtained by analyzing the q-axis component U of the receiving-end grid voltage output by the phase-locked loop. recv_q The derivative is obtained as follows: The initial active power adjustment ΔP is expressed as follows: Where, k p and k i These are the proportional and integral coefficients of the phase-locked loop.

5. The virtual inertia cooperative control method for a back-to-back modular multilevel converter according to claim 3, characterized in that, Based on the impedance R of the DC transmission line line and the measured value of DC bus voltage at the receiving end U' dc Calculate the estimated line power loss ΔP line Specifically, it is expressed as follows:

6. The virtual inertia cooperative control method for a back-to-back modular multilevel converter according to claim 1, characterized in that, The modulation margin is determined based on the safe operating lower limit of DC voltage, which is jointly determined by the AC voltage and modulation capability of the sending and receiving converters. The safe lower limit of DC voltage, U, is then determined. dc_limit This includes the following steps: Based on the virtual inertial control of the DC bus voltage at the receiving end, and the relationship between the grid voltage and the DC bus voltage at the receiving end, the first constraint value U' of the lower limit of the DC voltage at the receiving end is determined. dc min1 Specifically, it is expressed as follows: Based on the relationship between the sending-end grid voltage and the DC bus voltage, determine the second constraint value U' of the lower limit of the receiving-end DC voltage. dc min2 Specifically, it is expressed as follows: Based on the first and second constraint values ​​of the DC voltage lower limit at the receiving end, the voltage under virtual inertial control of the DC bus voltage is limited to obtain the DC voltage safety lower limit value U. dc_limit Specifically, it is expressed as follows: IN dc_limit =0.9min(U′ dcmin1 ,IN' dcmin2 ); Among them, U recv U' is the effective value of the receiving-end grid voltage. dc U is the measured value of the DC bus voltage at the receiving end. dc_send U is the effective value of the sending-end grid voltage. dc_send min ΔP is the theoretical minimum value of the DC bus voltage at the sending end, and ΔP is the initial active power adjustment. line P is the estimated value of line power loss. N R is the rated power. line This represents the impedance of a DC transmission line.

7. The virtual inertia cooperative control method for a back-to-back modular multilevel converter according to claim 6, characterized in that, Under full-frequency fluctuation conditions, the receiving-end DC bus voltage satisfies the following constraint: IN' dc ∈(U dc_limit ,IN dcN ] Among them, U dcN The rated DC bus voltage ensures that the voltage stress on the power devices does not exceed their rated withstand voltage level.

8. A virtual inertia cooperative control system for a back-to-back modular multilevel converter, characterized in that, The device includes a sending-end converter, a receiving-end converter, a DC link connecting the sending-end converter and the receiving-end converter, and a controller configured to perform the method as described in any one of claims 1-7.

9. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method as described in any one of claims 1-7.

10. A storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the method as described in any one of claims 1-7.

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