A can transceiver circuit and signal improvement method

Abstract

The application discloses a CAN transceiver circuit, which comprises a logic and timing module, a current mirror driving group and a resistance driver group; the input end of the logic and timing module is connected with a TXD signal, and the output end outputs a plurality of groups of driving signals, each group of the driving signals controls a current mirror driving group or a resistance driver group; the current mirror driving group and the resistance driver group are used for driving a CANH port and a CANL port, wherein a single CANH port or a single CANL port is provided with upper and lower current mirror driving groups and upper and lower resistance driver groups; the upper current mirror driving group is connected with the upper resistance driver group in parallel, and the lower current mirror driving group is connected with the lower resistance driver group in parallel. The application realizes the bit width consistency improvement and the adaptive baud rate through the independent impedance control of the current mirror pull structure and the differential port, and the process of adjusting the port impedance does not affect the bit width consistency.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor design, and particularly relates to a CAN transceiver circuit and a method for improving CAN transceiver signals. Background Technology

[0002] For CAN FD bus systems using a star topology (reference) Figure 1 To meet its maximum data transmission rate of 8 Mbit / s, the latest ISO 11898-2:2024 imposes stricter requirements on the consistency and impedance matching of CAN transceiver ports to address signal reflection and consistency issues caused by high-speed transmission. Because the port impedance of a traditional CAN port changes drastically from approximately 50Ω to 6-50kΩ when transitioning from dominant to recessive (logic 0 to 1), it causes bus signal ringing. (Refer to...) Figure 5 .

[0003] The new standard introduces Signal Improvement Capability (SIC) technology, which specifies the output impedance change process when the CAN transmit signal transitions from logic low to logic high, making it easier to suppress ringing.

[0004] The problem with existing technology is:

[0005] 1. The differential signal (Vdif) on the bus is the difference between CANH and CANL (Vdif=VCANH-VCANL). Vdif greater than 0.9V is dominant, and less than 0.5V is recessive. The chip uses Vdif to determine the bus status. Bus ringing will cause signal errors.

[0006] 2. Prolonged and significant ringing can increase the EMI emission power of the bus, causing interference to other electronic components.

[0007] 3. It is necessary to meet the higher technical standards for bit width symmetry performance of transmitted data as proposed in ISO 11898-2:2024, and at the same time solve the port impedance problem. The process of adjusting the port impedance should not affect the bit width consistency.

[0008] 4. The communication frequency needs to be pre-configured or detected, and the control method is based on the current communication frequency, so it cannot be adaptive. Summary of the Invention

[0009] To address the aforementioned technical problem, this invention provides a CAN transceiver circuit and signal improvement method. By using a current mirror pull-up structure and independent impedance control of differential ports, it achieves improved bit width consistency and adaptive baud rate, and the process of adjusting port impedance does not affect bit width consistency.

[0010] According to one aspect of the present invention, a CAN transceiver circuit is provided, including a logic and timing module, a current mirror driver group, and a resistor driver group; the input terminal of the logic and timing module is connected to a TXD signal, and the output terminal outputs multiple sets of driving signals, each set of driving signals controlling a current mirror driver group or a resistor driver group; the current mirror driver group and the resistor driver group are used to drive a CANH port and a CANL port, wherein each CANH port or CANL port is configured with upper and lower current mirror driver groups and upper and lower resistor driver groups; the upper current mirror driver group is connected in parallel with the upper resistor driver group, and the lower current mirror driver group is connected in parallel with the lower resistor driver group.

[0011] As a further technical solution, if each group of drive signals is split into N signals, then each current mirror drive group or resistor driver group is configured with N current mirror drivers or resistor drivers.

[0012] As a further technical solution, the current mirror drive is implemented in an open-loop or closed-loop manner.

[0013] As a further technical solution, the resistor driver is implemented using a MOSFET, a resistor, a capacitor, or a combination thereof.

[0014] As a further technical solution, the driving capabilities of the upper current mirror drive group and the lower current mirror drive group are the same, and the driving capabilities of the upper resistor driver group and the lower resistor driver group are the same.

[0015] As a further technical solution, the logic and timing module includes a timer and a logic switch, which are interconnected.

[0016] According to one aspect of the present invention, a method for improving CAN transceiver signals is provided, implemented using the aforementioned circuit, the method comprising:

[0017] When the TXD signal changes from recessive to dominant, the upper current mirror drive group of the CANH port and the lower current mirror drive group of the CANL port are turned on, the CANH port is pulled up, the CANL port is pulled down, and the differential signal Vdif begins to increase until Vdif is greater than 0.9V, at which point the bus becomes dominant.

[0018] When the TXD signal changes from dominant to recessive, the upper current mirror drive group of the CANL port and the lower current mirror drive group of the CANH port are turned on, and both the CANH port and the CANL port are driven to the VCC / 2 potential. The start time of the recessive drive waveform is controlled by controlling the turning speed of the upper current mirror drive group of the CANL port and the lower current mirror drive group of the CANH port.

[0019] With all current mirror drive groups off and all resistor drive groups on, the CANH and CANL ports are maintained at VCC / 2 potential. At this time, the port impedance is determined by the resistor drive groups.

[0020] The TXD signal remains recessive, and all resistor drivers are turned off after the impedance control timing is completed.

[0021] As a further technical solution, the method also includes: when the baud rate is increased, before the impedance control timing is completed, the TXD signal causes all resistor driver groups to be turned off, the upper current mirror driver group of the CANH port and the lower current mirror driver group of the CANL port to be turned on, and the bus is driven to the dominant position.

[0022] According to one aspect of the present invention, a CAN transceiver is provided, which is configured with the aforementioned CAN transceiver circuit.

[0023] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0024] 1. This invention can meet ISO technical requirements, suppress bus ringing amplitude, and satisfy... Figure 2 The latest ISO expectation for port impedance changes.

[0025] 2. This invention can actively drive the bus to recessive mode, improving the accuracy of transmitter bit width symmetry, such as... Figure 7 As shown, this allows the TXD bit width to be equal to the CAN bus bit width.

[0026] 3. This invention does not require configuring the communication frequency and can adaptively generate drive signals for different communication frequencies. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the peripheral application of the CAN bus in the existing technology.

[0029] Figure 2 This is a schematic diagram illustrating the port impedance change process expected by the new ISO standard in existing technologies.

[0030] Figure 3 The topology diagram of the CAN transceiver circuit provided in the embodiment of the present invention is shown.

[0031] Figure 4The topology timing diagram of the CAN transceiver circuit provided in the embodiment of the present invention.

[0032] Figure 5 This is a schematic diagram of the bus waveform before the output signal quality was improved.

[0033] Figure 6 This is a schematic diagram of the bus waveform after the output signal quality has been improved, as provided in an embodiment of the present invention.

[0034] Figure 7 This is a schematic diagram of ideal waveform and bit width measurement provided for an embodiment of the present invention.

[0035] Figure 8 This is a schematic diagram of one type of resistor driver provided in an embodiment of the present invention. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. In addition, the technical features of the various embodiments or individual embodiments provided by the present invention can be arbitrarily combined to form new technical solutions. Such combinations are not bound by the order of steps and / or structural composition patterns, but must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0037] This invention provides a CAN transceiver circuit, including a logic and timing module, a current mirror driver group, and a resistor driver group. The logic and timing module receives a TXD signal at its input and outputs multiple sets of drive signals, each set of drive signals controlling a current mirror driver group or a resistor driver group. The current mirror driver group and resistor driver group are used to drive CANH and CANL ports, wherein each CANH or CANL port is configured with upper and lower current mirror driver groups and upper and lower resistor driver groups. The upper current mirror driver group and the upper resistor driver group are connected in parallel, and the lower current mirror driver group and the lower resistor driver group are connected in parallel.

[0038] It should be noted that the resistor driver described in this invention is a general term for a class of structures that can change port impedance. This type of structure can be a single resistor, a MOSFET operating in the linear region, a resistor and capacitor in parallel, or a MOSFET operating in the linear region in parallel with a capacitor. The last structure is provided here for reference, such as... Figure 8 As shown. The current mirror drive described in this invention can be implemented using existing technology.

[0039] See Figure 3 The TXD signal (in this manual, it refers to the transmit data signal of the CAN transceiver) is input to the logic and timing module, generating multiple sets of drive signals. These signals control multiple sets of current mirror drivers and multiple sets of resistor drivers. Each set of drive signals can be divided into multiple signals, and each driver can also be divided into multiple sub-drives to control the switching speed. The current mirror driver can be open-loop or closed-loop, and the resistor driver can be a MOSFET, resistor, capacitor, inductor, or a combination thereof. The upper and lower current mirror drivers and the upper and lower resistor drivers form a complete drive structure for a single port.

[0040] The logic and timing module includes a timer and a logic switch. The generation of multiple sets of drive signals through the logic switch and the timer can be achieved using existing technologies, which will not be elaborated upon in this invention. For example, the logic switch can be implemented using a combination of inverters and latches.

[0041] like Figure 3 The schematic diagram shows that port CANH is driven by current mirrors A and C, and resistor drivers A and C; port CANL is driven by current mirrors B and D, and resistor drivers B and D. It should be noted that... Figure 3 In the diagram, current mirror driver A is equivalent to the upper current mirror driver group of the CANH port, current mirror driver C is equivalent to the lower current mirror driver group of the CANH port, current mirror driver B is equivalent to the upper current mirror driver group of the CANL port, and current mirror driver D is equivalent to the lower current mirror driver group of the CANL port. Similarly, resistor drivers A and C are equivalent to the upper and lower resistor driver groups of the CANH port, respectively, and resistor drivers B and D are equivalent to the upper and lower resistor driver groups of the CANL port, respectively.

[0042] See Figure 4 The topology timing diagram shown is as follows:

[0043] In the first stage, the TXD signal transitions from logic 1 to logic 0 (i.e., from recessive to dominant), the current mirror drives A and D to be turned on, the CANH port is pulled up, the CANL port is pulled down, and Vdif begins to increase until Vdif is greater than 0.9V, at which point the bus becomes dominant.

[0044] In the second stage, the TXD signal transitions from logic 0 to logic 1 (i.e., from dominant to recessive). Current mirror drivers B and C are activated. Since current mirror drivers A and C have the same driving capability, CANH is driven to VCC / 2. The same applies to the CANL port. By controlling the activation speed of current mirror drivers B and C, the start time of the recessive drive waveform can be arbitrarily controlled, achieving the effect of actively adjusting the recessive speed. This improves the precision of the dominant and recessive bit widths on the bus. (Reference) Figure 7 .

[0045] In the third stage, all current mirror drivers are disabled, and all resistor drivers are enabled. Since the resistor drivers have consistent driving capabilities, CANH and CANL remain at VCC / 2. At this point, the port impedance is determined by the resistor drivers. (Refer to...) Figure 5 and Figure 6 In the comparison of the SIC effect, when the bus is driven to recessive, there is no longer any ringing with a differential voltage greater than 0.5V, thus eliminating the bit error.

[0046] In the fourth stage, TXD remains at 1, and all resistor drivers are turned off after the impedance control timing is completed.

[0047] When the baud rate increases, the impedance control timing is not yet complete. The TXD signal turns off all resistor drivers, turns on the current mirror drivers A and D, and drives the bus to the dominant position. This means the technology is fully adaptive to the communication baud rate, requiring no prior configuration or detection.

[0048] It should be noted that all parameters in the accompanying drawings of this invention can be found in ISO 11898-2:2024:

[0049] tact_rec_start: The time from when the TXD logic jumps to 1 to when bus impedance control begins;

[0050] tact_rec_end: The time from when the TXD logic jumps to 1 until the bus impedance control ends;

[0051] tpas_rec_start: The time it takes for the TXD logic to jump to 1 and for the bus impedance to recover to the 12KΩ high differential impedance.

[0052] Based on the same inventive concept as the foregoing embodiments, this embodiment of the invention also provides a CAN transceiver signal improvement method, implemented using the aforementioned CAN transceiver circuit. The main steps of the method are implemented with reference to the working process of the aforementioned CAN transceiver circuit, specifically as follows:

[0053] When the TXD signal changes from recessive to dominant, the upper current mirror drive group of the CANH port and the lower current mirror drive group of the CANL port are turned on, the CANH port is pulled up, the CANL port is pulled down, and the differential signal Vdif begins to increase until Vdif is greater than 0.9V, at which point the bus becomes dominant.

[0054] When the TXD signal changes from dominant to recessive, the upper current mirror drive group of the CANL port and the lower current mirror drive group of the CANH port are turned on, and both the CANH port and the CANL port are driven to the VCC / 2 potential. The start time of the recessive drive waveform is controlled by controlling the turning speed of the upper current mirror drive group of the CANL port and the lower current mirror drive group of the CANH port.

[0055] With all current mirror drive groups off and all resistor drive groups on, the CANH and CANL ports are maintained at VCC / 2 potential. At this time, the port impedance is determined by the resistor drive groups.

[0056] The TXD signal remains recessive, and all resistor drivers are turned off after the impedance control timing is completed.

[0057] Furthermore, when the baud rate is increased, the impedance control timing is not completed. The TXD signal turns off all the resistor driver groups, turns on the upper current mirror driver group of the CANH port and the lower current mirror driver group of the CANL port, and drives the bus to the dominant position.

[0058] Based on the same inventive concept as the foregoing embodiments, this embodiment of the invention also provides a CAN transceiver configured with the aforementioned CAN transceiver circuit.

[0059] In summary, the key innovation of this invention lies in solving the problems of existing technologies using a simple structure, achieving the latest ISO standards, specifically reflected in:

[0060] ① The current mirror pull structure improves the consistency of bit width.

[0061] ② The differential ports have independent impedance control and adaptive baud rate.

[0062] ③ The control logic and method of the drive ensure that adjusting the port impedance does not affect the consistency of the bit width.

[0063] It should be understood that any parts not described in detail in this specification belong to the prior art.

[0064] The terms “comprising” and “having”, and any variations thereof, in the specification, claims, and accompanying drawings of this invention are intended to cover a non-exclusive inclusion, such as a process, method, system, product, or apparatus that includes a series of steps or units, not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the technical solutions of the embodiments of the present invention.

Claims

1. A CAN transceiver circuit, characterized in that, It includes a logic and timing module, a current mirror driver group, and a resistor driver group; the input terminal of the logic and timing module is connected to the TXD signal, and the output terminal outputs multiple sets of driving signals, each set of driving signals controlling a current mirror driver group or a resistor driver group. The current mirror drive group and resistor driver group are used to drive the CANH port and CANL port. Each CANH port or CANL port is equipped with upper and lower current mirror drive groups and upper and lower resistor driver groups. The upper current mirror drive group and the upper resistor driver group are connected in parallel, and the lower current mirror drive group and the lower resistor driver group are connected in parallel. The driving capabilities of the upper current mirror drive group and the lower current mirror drive group are the same, and the driving capabilities of the upper resistor driver group and the lower resistor driver group are the same.

2. The CAN transceiver circuit according to claim 1, characterized in that, Each group of drive signals is divided into N signals, each current mirror drive group is configured with N current mirror drivers, and each resistor driver group is configured with N resistor drivers.

3. The CAN transceiver circuit according to claim 2, characterized in that, The current mirror drive can be implemented in an open-loop or closed-loop manner.

4. The CAN transceiver circuit according to claim 2, characterized in that, The resistor driver is implemented using a MOSFET, resistor, capacitor, or a combination thereof.

5. The CAN transceiver circuit according to claim 1, characterized in that, The logic and timing module includes a timer and a logic switch, which are interconnected.

6. A method for improving CAN transceiver signals, implemented using the circuit described in any one of claims 1-5, characterized in that, The method includes: When the TXD signal changes from recessive to dominant, the upper current mirror drive group of the CANH port and the lower current mirror drive group of the CANL port are turned on, the CANH port is pulled up, the CANL port is pulled down, and the differential signal Vdif begins to increase until Vdif is greater than 0.9V, at which point the bus becomes dominant. When the TXD signal changes from dominant to recessive, the upper current mirror drive group of the CANL port and the lower current mirror drive group of the CANH port are turned on, and both the CANH port and the CANL port are driven to the VCC / 2 potential. The start time of the recessive drive waveform is controlled by controlling the turning speed of the upper current mirror drive group of the CANL port and the lower current mirror drive group of the CANH port. With all current mirror drive groups off and all resistor drive groups on, the CANH and CANL ports are maintained at VCC / 2 potential. At this time, the port impedance is determined by the resistor drive groups. The TXD signal remains recessive, and all resistor drivers are turned off after the impedance control timing is completed.

7. The CAN transceiver signal improvement method according to claim 6, characterized in that, The method further includes: When the baud rate increases, the impedance control timing is not completed. The TXD signal turns off all resistor driver groups, turns on the upper current mirror driver group of the CANH port and the lower current mirror driver group of the CANL port, and drives the bus to the dominant position.

8. A CAN transceiver, characterized in that, It is equipped with the CAN transceiver circuit according to any one of claims 1-5.

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