PCB board ESD protection method based on composite TVS and honeycomb ground

Abstract

The application discloses a PCB board ESD protection method based on a composite TVS and a honeycomb ground, and specifically comprises the following steps: step S100, coping with external input impact layout; step S200, TVS array layout; step S300, honeycomb ground structure layout; step S400, PCB layering layout; and step S500, establishing a static electricity discharge special path. The application realizes that the ESD protection efficiency of a frequency band above 3GHz reaches 96%, the ESD protection level is improved to ±30kV, high-voltage external impact can be stably protected, and the honeycomb size effectively improves the overcurrent voltage capacity by adopting the honeycomb ground structure.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge technology, specifically to a PCB board ESD protection method based on composite TVS and cellular grounding. Background Technology

[0002] Traditional TVS diodes (such as US20170256923A1) have a response time of ≥1ns, making it difficult to protect against ns-level ESD pulses. Simply increasing the grounding area leads to a larger PCB size, and ESD protection in high-frequency circuits will introduce parasitic capacitance (>5pF), affecting signal integrity.

[0003] ESD has caused great trouble in the field of circuit design, for example: it can directly cause short circuits, open circuits or loss of function of devices; it can directly damage hard drives, flash memory, etc., resulting in data loss or file corruption; it can increase maintenance costs: frequent replacement of damaged components or return of equipment for repair, such as replacing TVS diodes when USB interface capacitors are short-circuited; and it can reduce production efficiency: equipment failures and downtime or increased testing procedures.

[0004] ESD protection is also closely related to the electronic components laid out on the PCB board, which is one of the most easily overlooked aspects of ESD protection. For instruments that require precise measurements, such as oscilloscopes and signal generators, current ESD protection methods typically use TVS diodes as a protection measure. (Reference) Figure 1 Currently, TVS diodes, as an ESD protection measure, along with some simple anti-static measures (such as magnetic rings), can only protect against external voltage surges of ±15kV.

[0005] However, ESD protection is still inadequate for external high voltage impacts of ±30kV. After repeated tests, the following problems were found: (1) ESD protection efficiency of frequencies above 3GHz is less than 60%; (2) The qualification rate of existing solutions for ±30kV air discharge is <85%.

[0006] Therefore, existing technologies can no longer meet people's current needs, and based on the current situation, there is an urgent need to improve existing technologies. Summary of the Invention

[0007] The purpose of this invention is to provide a PCB board ESD protection method based on composite TVS and cellular grounding to solve the problems mentioned in the background art.

[0008] This invention provides the following technical solution: a PCB board ESD protection method based on a composite TVS and cellular grounding, the specific steps of which include:

[0009] Step S100: Layout to cope with external input impact;

[0010] A high-pressure gas discharge tube is used at the interface to block the initial 30kV energy impact received at the interface.

[0011] Step S200: TVS array layout; including:

[0012] First-level TVS array layout and second-level TVS array layout; wherein...

[0013] A 30kW ultra-high power first-stage TVS array shall be installed at a distance of ≤5mm from the low-speed interface or ≤3mm from the high-speed interface.

[0014] A second-stage TVS array with low capacitance is set at the front end of the IC to clamp residual voltage and protect the IC.

[0015] Step S300: Layout of the cellular grounding structure;

[0016] The hexagonal grid spacing between the first-level TVS array and the second-level TVS array is set to 20mil-30mil, with a grid coverage of ≥85%.

[0017] Set the unit cell impedance to <0.1Ω and the grid line width to ≥10mil;

[0018] Step S301: Set up an independent grounding island at the interface and connect it to the main ground plane through a cellular via;

[0019] Step S302: Connect the gas discharge tube directly to the metal casing and the honeycomb grounding structure, close to the interface;

[0020] Step S303: The TVS array grounding pin adopts a star topology direct-connected cellular grounding structure.

[0021] Step S400: PCB stack-up layout, including:

[0022] The interface signal layer directly connects the TVS array to the cellular grounding structure;

[0023] The cellular grounding layer has 50% copper coverage and is reinforced with a grid.

[0024] Inner signal layer, control interface signal layer;

[0025] The planar layer is interconnected with the cellular grounding structure via an array of vias.

[0026] The power layer is slotted to isolate the high-voltage and low-voltage areas.

[0027] Step S500: Establish a dedicated path for electrostatic discharge:

[0028] Step S501: Connect the interface, TVS array, IC and PCB layer to the digital grounding post at a single point, and add a 100nF high-voltage capacitor to the connection point;

[0029] Step S502: Place grounding vias densely near the grounding pin of the ESD protection device and connect it to the internal ground plane through the grounding vias to further reduce the inductance of the grounding path.

[0030] The present invention has the following beneficial effects: the ESD protection efficiency in the frequency band above 3GHz reaches 96%, the ESD protection level is improved to ±30kV, it can stably protect against high voltage external impacts, and the honeycomb grounding structure effectively improves the overcurrent and voltage capability by adopting the honeycomb size. Attached Figure Description

[0031] Figure 1 A schematic diagram of a structure for protecting against external voltage surges of ±15kV using existing technology;

[0032] Figure 2 This is a schematic diagram of the structure of the present invention;

[0033] Figure 3 This is a schematic diagram of the TVS array structure of the present invention;

[0034] Figure 4 This is a schematic diagram of the cellular grounding structure of the present invention. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the present invention without creative effort are within the scope of protection of the present invention. References Figures 2-4 This invention provides the following technical solution: a PCB board ESD protection method based on a composite TVS and cellular grounding. Electronic devices laid out on the PCB board of an oscilloscope or signal generator generally include: interfaces, TVS arrays, ICs, and PCB layers. In this embodiment, the interfaces include low-speed interfaces and high-speed interfaces; the TVS arrays include cascaded multi-level TVS arrays; this invention provides a first-level TVS array and a second-level TVS array; the PCB layers include: an interface signal layer, a cellular grounding layer, an inner signal layer, a power layer, and a planar layer; wherein, TVS represents a transient voltage suppressor diode; ESD represents electrostatic discharge; IC represents an integrated circuit; and PCB represents a printed circuit board.

[0036] The specific steps include:

[0037] Step S100: Blocking external input impact layout; specifically:

[0038] High-voltage gas discharge tubes (GDTs) are used at the interface to deal with the initial 30kV energy impact received at the interface.

[0039] Step S200: TVS array layout;

[0040] This includes: a first-level TVS array layout and a second-level TVS array layout; among which,

[0041] A 30kW ultra-high power first-stage TVS array shall be installed at a distance of ≤5mm from the low-speed interface or ≤3mm from the high-speed interface.

[0042] A low-capacitance second-stage TVS array (such as model ESD9544 with a capacitance <1pF) is set at the front end of the IC to clamp the residual voltage and protect the IC.

[0043] Step S201: Match the parameters of the first-level TVS array;

[0044] This includes: setting the junction capacitance to 0.75pF; setting the breakdown voltage to ≥ 24V; setting the peak pulse current to ≥ 100A; setting the response time to ≤ 0.5ns; and connecting the TVS array grounding pin to the cellular grounding area via a short, straight trace (<3mm).

[0045] Step S202: Match the parameters of the second-level TVS array:

[0046] Set the spacing between the second-stage TVS array and the IC to ≥15mm; and set the spacing between the first-stage TVS array and the second-stage TVS array to ≥10mm to avoid coupling between stages;

[0047] Step S203: Solder mask opening: Do not cover the area within 0.5mm around the TVS array pads with solder mask.

[0048] Step S300: Layout of the cellular grounding structure;

[0049] The hexagonal grid spacing between the first-level TVS array and the second-level TVS array is set to 20mil-30mil, so that the grid coverage is ≥85%.

[0050] Set the unit cell impedance to <0.1Ω (1GHz test) and the grid line width to ≥10mil to reduce the current density;

[0051] Step S301: Set up an independent grounding island at the interface and connect it to the main ground plane through a cellular via;

[0052] Step S302: Connect the gas discharge tube directly to the metal housing and the honeycomb grounding structure, close to the interface (such as the outer shell of a USB interface / RJ45 interface);

[0053] Step S303: The TVS array grounding pin adopts a star topology direct-connected cellular grounding structure; wherein, a 3×3 via array (0.3mm diameter, 2mm spacing) is arranged around the grounding terminal of the TVS array, and the via density of the whole board is ≥ 1 / cm², to avoid common impedance interference and ensure low impedance return current.

[0054] Step S400: PCB stack-up layout, including:

[0055] The interface signal layer directly connects the TVS array to the cellular grounding structure;

[0056] The cellular grounding layer has 50% copper coverage and is reinforced with a grid.

[0057] Inner signal layer, control interface signal layer;

[0058] The planar layer is interconnected with the cellular grounding structure via an array of vias.

[0059] The power layer is slotted to isolate the high-voltage and low-voltage areas.

[0060] Step S401: Match high-voltage isolation parameters:

[0061] The distance between high-voltage and low-voltage areas is ≥10mm (to meet the 30kV air breakdown requirement); 2mm slot isolation is used in the interface signal layer, filled with insulating varnish (such as polyimide).

[0062] Step S500: Establish a dedicated path for electrostatic discharge:

[0063] Step S501: Connect the interface, TVS array, IC and PCB layer to the digital grounding post at a single point, and add a 100nF high-voltage capacitor to the connection point. The high-voltage capacitor (e.g., 100pF / 2KV) provides a path for high-frequency ESD current.

[0064] Step S502: Place grounding vias densely near the grounding pins of the ESD protection device and connect it to the internal ground plane through the grounding vias to further reduce the inductance of the grounding path;

[0065] Establishing a dedicated path for electrostatic discharge can not only discharge static electricity, but also prevent huge ESD currents / noise from flooding into sensitive internal signal grounds, causing system resets or interference. Among them, internal signal ground (Signal GND) is the main reference ground on the motherboard and the grounding reference point for all sensitive chips.

[0066] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A PCB board ESD protection method based on composite TVS and cellular grounding, characterized in that, The specific steps include: Step S100: Layout to cope with external input impact; A high-pressure gas discharge tube is used at the interface to block the initial 30kV energy impact received at the interface. Step S200: TVS array layout; including: First-level TVS array layout and second-level TVS array layout; wherein... A 30kW ultra-high power first-stage TVS array shall be installed at a distance of ≤5mm from the low-speed interface or ≤3mm from the high-speed interface. The parameters that match the first-level TVS array include: Set the junction capacitance to 0.75pF; Set the breakdown voltage to ≥ 24V; Set the peak pulse current to ≥ 100A; Set the response time to ≤ 0.5ns; Connect the TVS array grounding pin to the cellular grounding area using a short, straight trace. A low-capacitance second-stage TVS array is set at the front end of the IC to clamp residual voltage and protect the IC. The parameters for matching the second-level TVS array include: Set the spacing between the second-stage TVS array and the IC to ≥15mm; Set the spacing between the first-level TVS array and the second-level TVS array to ≥ 10mm; Step S300: Layout of the cellular grounding structure; The hexagonal grid spacing between the first-level TVS array and the second-level TVS array is set to 20mil-30mil, with a grid coverage of ≥85%. Set the unit cell impedance to <0.1Ω and the grid line width to ≥10mil; Step S301: Set up an independent grounding island at the interface and connect it to the main ground plane through a cellular via; Step S302: Connect the gas discharge tube directly to the metal casing and the honeycomb grounding structure, close to the interface; Step S303: The TVS array grounding pin adopts a star topology direct-connected cellular grounding structure; Step S400: PCB stack-up layout, including: The interface signal layer directly connects the TVS array to the cellular grounding structure; The cellular grounding layer has 50% copper coverage and is reinforced with a grid. Inner signal layer, control interface signal layer; The planar layer is interconnected with the cellular grounding structure via a via array; wherein, a 3×3 via array is arranged around the grounding terminal of the TVS array, and the via density of the entire board is ≥ 1 via / cm², and the via diameter is 0.3mm and the spacing is 2mm; The power layer is slotted to isolate the high-voltage and low-voltage areas. Step S500: Establish a dedicated path for electrostatic discharge: Step S501: Connect the interface, TVS array, IC and PCB layer to the digital grounding post at a single point, and add a 100nF high-voltage capacitor to the connection point; Step S502: Place grounding vias densely near the grounding pin of the ESD protection device and connect it to the internal ground plane through the grounding vias to further reduce the inductance of the grounding path.

2. The PCB board ESD protection method based on composite TVS and cellular grounding according to claim 1, characterized in that: TVS array layouts also include: Solder mask opening: No green solder mask is applied within 0.5mm around the TVS array pads.

3. The PCB board ESD protection method based on composite TVS and cellular grounding according to claim 1, characterized in that: The capacitance in the second-stage TVS array with low capacitance is <1pF.

4. The PCB board ESD protection method based on composite TVS and cellular grounding according to claim 1, characterized in that: Matching high-voltage isolation parameters, including: The distance between high-pressure and low-pressure areas shall be ≥10mm; The interface signal layer is isolated by a 2mm slot and filled with insulating varnish.

Images