Control on-chip low dropout linear regulator and off-chip triode current distribution circuit

Abstract

According to the control on-chip low dropout linear regulator and off-chip triode current distribution circuit provided by the embodiment of the invention, two signals output by a common end between a drain electrode of a first NMOS (N-channel Metal Oxide Semiconductor) tube and a first current source and a common end between a drain electrode of a second NMOS tube and a second current source are utilized; the logic of the digital control unit is controlled, and the purpose of distributing current between the interior of the low-voltage linear voltage regulator and the triodes according to a design value is achieved.

Description

Technical Field

[0001] The embodiments of this application belong to the field of circuit design technology, and in particular relate to a control circuit for an on-chip low dropout linear regulator and an external transistor current distribution circuit. Background Technology

[0002] In the field of automotive electronics, power management is a crucial aspect of ensuring system stability and reliability. With the development of intelligent vehicles, modules such as electronic control units (ECUs) have increasingly higher requirements for power quality and capacity. Among these, low dropout regulators (LDOs) have become one of the mainstream on-board power supply solutions due to their low noise, fast response, and low cost.

[0003] Compared to switching power supplies, low dropout linear regulators have lower output ripple and do not require inductors, reducing PCB design complexity and saving costs. At the same time, due to the absence of switching losses, low dropout linear regulators can also provide a relatively low quiescent power consumption.

[0004] However, compared to switching power supplies, low-dropout linear regulators are less efficient, and their efficiency further decreases as the input voltage increases due to the need to maintain a constant output voltage (essentially because the power on the power transistors increases under constant load current). A significant problem arising from this low efficiency is the rise in on-chip temperature. Because the power on the on-chip power transistors is high, this causes the chip's operating temperature to rise. Due to the over-temperature protection requirements of automotive electronics, under the same load conditions, the higher the on-chip power, the easier it is to trigger the over-temperature protection threshold (meaning the chip temperature reaches a preset value). Typically, triggering over-temperature protection causes the system to actively shut down the power module, which affects modules that require its power.

[0005] To address the aforementioned issues and enhance the load-carrying capacity of low-dropout linear regulators (LDLs) so they can handle larger loads without triggering over-temperature protection, a mainstream solution has emerged: using an external transistor in parallel with an internal power transistor to distribute power, or current, across them in a specific ratio, thereby reducing the internal power consumption. However, determining the appropriate current distribution ratio and designing the control circuit for the external transistor to achieve current sharing with the LDL has proven challenging. Summary of the Invention

[0006] To address or mitigate the problems in the prior art, this application provides a current distribution circuit for controlling an on-chip low-dropout linear regulator and an external transistor, including a transistor and a low-dropout linear regulator;

[0007] The low-dropout linear regulator includes a first error amplifier, a negative feedback loop, and a current sampling circuit.

[0008] The emitter and collector of the transistor are both connected to the negative feedback loop and the current sampling circuit, and the collector of the transistor is connected to the current sampling circuit.

[0009] One end of the negative feedback loop is connected to the reference voltage; the other end of the negative feedback loop is connected to the collector of the transistor.

[0010] One end of the current sampling circuit is connected to the collector of the transistor, and the other end of the current sampling circuit is connected to the gate of the first NMOS transistor and the gate of the second NMOS transistor in sequence. The drain of the first NMOS transistor is connected to the first current source, and the drain of the second NMOS transistor is connected to the second current source.

[0011] The common terminal between the drain of the first NMOS transistor and the first current source is connected to the input terminal of the digital control unit, and the common terminal between the drain of the second NMOS transistor and the second current source is connected to the input terminal of the digital control unit. The digital control unit controls the opening or closing of the switch, thereby controlling the magnitude of the current flowing into the base of the transistor.

[0012] As a preferred embodiment of this application, it also includes a first inverter and a second inverter;

[0013] The drain of the first NMOS transistor and the input of the first inverter are both connected to the first current source, and the drain of the second NMOS transistor and the input of the second inverter are both connected to the second current source.

[0014] The output terminals of the first inverter and the second direction inverter are both connected to the input terminal of the digital control unit.

[0015] In a preferred embodiment of this application, the negative feedback loop includes a first error amplifier, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first resistor, and a second resistor;

[0016] The common terminal between the first resistor and the second resistor is connected to the negative input terminal of the first error amplifier;

[0017] The output terminal of the first error amplifier is connected to the gate of the third NMOS transistor, the source of the third NMOS transistor is connected to ground, the drain of the third NMOS transistor is connected to the drain and gate of the first PMOS transistor, the gate and drain of the first PMOS transistor are connected to the gate of the second PMOS transistor, and the drain of the second PMOS transistor is connected to the collector of the transistor and one end of the first resistor; the end of the second resistor furthest from the first resistor is connected to ground.

[0018] The source of the first PMOS transistor and the source of the second PMOS transistor are both connected to the emitter of the transistor.

[0019] In a preferred embodiment of this application, the current sampling circuit includes a third PMOS transistor, a second PMOS transistor, and a fourth NMOS transistor;

[0020] The source of the third PMOS transistor is connected to the emitter of the transistor, and the gate of the third PMOS transistor is connected to the gate of the second PMOS transistor; the drain of the third PMOS transistor is connected to the drain and gate of the fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the gate of the first NMOS transistor, and the source of the fourth NMOS transistor is connected to the ground terminal.

[0021] In a preferred embodiment of this application, the current sampling circuit further includes a second error amplifier;

[0022] The positive input terminal of the second error amplifier is connected to the drain of the third PMOS transistor, and the negative input terminal of the second error amplifier is connected to the drain of the second PMOS transistor.

[0023] The output of the second error amplifier is connected to the gate of the fourth NMOS transistor.

[0024] In a preferred embodiment of this application, the load is connected in parallel with the circuit containing the first resistor and the second resistor, one end of the load is connected to one end of the first resistor, and the other end of the load is connected to the ground terminal.

[0025] As a preferred embodiment of this application, it also includes a capacitor:

[0026] The upper plate of the capacitor is connected to one end of the load, and the lower plate of the capacitor is connected to the other end of the load.

[0027] Compared with the prior art, the embodiments of this application utilize two signals output from the common terminal between the drain of the first NMOS transistor and the first current source, and the common terminal between the drain of the second NMOS transistor and the second current source, to control the logic of the digital control unit, thereby achieving the purpose of distributing current according to design values ​​within the low-voltage linear regulator and between the transistors. Attached Figure Description

[0028] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. Some specific embodiments of this application will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0029] Figure 1 This application provides an embodiment of a circuit diagram for controlling the current distribution between an on-chip low-dropout linear regulator and an external transistor.

[0030] Figure 2 Another embodiment of this application provides a circuit diagram for controlling the current distribution between an on-chip low-dropout linear regulator and an external transistor;

[0031] Figure 3 Another embodiment of this application provides a circuit diagram for controlling the current distribution between an on-chip low-dropout linear regulator and an external transistor;

[0032] Figure 4 This is a schematic diagram of the digital control unit controlling the switch according to an embodiment of this application;

[0033] Figure 5 This is a graph showing the distribution of current in the second PMOS transistor and the current in the PNP transistor in this application as a function of the load current Iload. Detailed Implementation

[0034] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.

[0035] To address the technical problems in existing technologies, the current sharing between external transistors and internal power transistors is achieved through active current sharing control. The core of this method lies in using one or more operational amplifiers to form an analog control loop. This loop uses a negative feedback mechanism to continuously and in real-time adjust the drive signals of the power devices, thereby forcing current sharing. Specifically, the current on the transistor is sampled using a high-precision resistor and converted into a voltage signal. Simultaneously, the current on the internal power transistor is also sampled and converted into a voltage signal. These two voltage signals serve as the two inputs of an error amplifier, and the output is connected to a Gm-stage amplifier to drive the base of the external transistor, forming a negative feedback loop. This loop clamps the two input voltage signals together. Based on the current-to-voltage conversion factor, the ratio of the current on the external transistor to that on the internal power transistor can be obtained. However, this method has two drawbacks. First, a high-precision resistor needs to be connected in series with the emitter or collector of the off-chip transistor. The resistance value and temperature coefficient of this resistor must be accurate enough to ensure that the voltage signal converted from the voltage drop across the resistor is reliable. Second, this method introduces an additional analog loop, which works together with the loop of the low-dropout linear regulator itself. This requires designing a reasonable compensation method to avoid the two loops from affecting each other and causing loop instability, which is an extremely difficult problem to solve.

[0036] Another approach is to use mixed-signal control. Specifically, this also requires sampling the current from the external transistor and internal power transistor and converting it into voltage signals. However, the voltage signals then need to be converted into digital codes using an analog-to-digital converter (ADC). The digital codes output control signals based on their magnitude, which are then passed through a digital-to-analog converter (DAC) to control the base current of the transistor, thus controlling the transistor current. The advantage of this approach is that the analog circuitry only handles sampling, while feedback and calculation are performed by the digital section, avoiding the introduction of additional loops. However, it still requires high-precision sampling resistors and an ADC, which impacts the chip's area and power consumption.

[0037] In order to solve the technical problems in the prior art, this application provides the following technical solution.

[0038] The distribution circuit in this application is housed within a chip, while the transistor is located outside the chip. The emitter, collector, and base of the transistor are all connected to the chip's pins. This application primarily aims to distribute current according to design values ​​between the low-voltage linear regulator and the transistor. Furthermore, the low-dropout linear regulator is located on the chip.

[0039] like Figure 1 As shown, this application provides a current distribution circuit for controlling an on-chip low-dropout linear regulator and an external transistor, including a transistor and a low-dropout linear regulator;

[0040] The low-dropout linear regulator includes a first error amplifier EA1, a negative feedback loop, and a current sampling circuit.

[0041] One end of the negative feedback loop is connected to the reference voltage VREF; the other end of the negative feedback loop is connected to the collector of the transistor.

[0042] One end of the current sampling circuit is connected to the collector of the transistor, and the other end of the current sampling circuit is connected to the gate of the first NMOS transistor M2 and the gate of the second NMOS transistor M1 in sequence. The drain of the first NMOS transistor M2 is connected to the first current source I2, and the drain of the second NMOS transistor M1 is connected to the second current source I1.

[0043] The common terminal between the drain of the first NMOS transistor M2 and the first current source I2 is connected to the input terminal of the digital control unit. The common terminal between the drain of the second NMOS transistor M1 and the second current source I1 is also connected to the input terminal of the digital control unit. The digital control unit controls the opening or closing of the switch, thereby controlling the magnitude of the current flowing from the current source into the base of the transistor. Both the digital control unit and the switch are located inside the chip.

[0044] This application embodiment utilizes two signals output from the common terminal between the drain of the first NMOS transistor M2 and the first current source I2, and the common terminal between the drain of the second NMOS transistor M1 and the second current source I1, to control the logic of the digital control unit, thereby achieving the purpose of distributing current according to design values ​​within the low-voltage linear regulator and between the transistors.

[0045] Preferably, the negative feedback loop includes a first error square amplifier EA1, a third NMOS transistor M7, a first PMOS transistor M6, a second PMOS transistor M5, a first resistor R1, and a second resistor R2;

[0046] The common terminal between the first resistor R1 and the second resistor R2 is connected to the negative input terminal VFB of the first error amplifier EA1.

[0047] The output terminal of the first error amplifier EA1 is connected to the gate of the third NMOS transistor M7, the source of the third NMOS transistor M7 is connected to the ground terminal, the drain of the third NMOS transistor M7 is connected to the drain and gate of the first PMOS transistor M6, the gate and drain of the first PMOS transistor M6 are connected to the gate of the second PMOS transistor M5, and the drain of the second PMOS transistor M5 is connected to the collector of the transistor and one end of the first resistor R1.

[0048] The source of the first PMOS transistor M6 and the source of the second PMOS transistor M5 are both connected to the emitter of the transistor.

[0049] When the voltage at the positive input terminal VREF of the first error amplifier EA1 is greater than the voltage at the negative input terminal VFB, the gate voltage of the third NMOS transistor M7 will be raised, the drain and gate voltages of the first PMOS transistor M6 will be lowered, and the gate voltage of the second PMOS transistor M5 will be lowered. As a result, the current of the second PMOS transistor M5 increases, and VOUT increases. After VOUT increases, the voltage across the first resistor R1 and the second resistor R2 will also increase. At this time, the voltage VFB between the first resistor R1 and the second resistor R2 will also increase, thus forming a negative feedback loop.

[0050] It should be noted that the second PMOS transistor M5 is the power transistor in the linear low-dropout regulator, and the third NMOS transistor M7 and the first PMOS transistor M6 form a buffer circuit, which acts as a driver stage to drive the second PMOS transistor M5. This application uses a negative feedback loop to clamp the positive input terminal VREF and the negative input terminal VFB of the first error amplifier EA1 to the same voltage. In the embodiments of this application, the first resistor R1 and the second resistor R2 simply represent two resistors with different resistance values; the first resistor R1 and the second resistor R2 themselves can include multiple resistors connected in series or parallel.

[0051] Figures 1 to 3 It is an LDO architecture. The first error amplifier EA1 is clamped to the same voltage by the positive input terminal VREF and the negative input terminal VFB of the first error amplifier EA1 after passing through the third NMOS transistor M7, the first PMOS transistor M6 and the second PMOS transistor M5, and the feedback voltage divider first resistor R1 and second resistor R2. This results in VOUT*R2 / (R1+R2)=VREF. The above equation holds true within the normal load range of the linear low dropout regulator LDO. This is the basic principle that the linear low dropout regulator LDO can keep the output voltage unchanged with the load.

[0052] Preferably, the current sampling circuit includes a third PMOS transistor M4, a second PMOS transistor M5, and a fourth NMOS transistor M3; the third PMOS transistor M4 and the second PMOS transistor M5 generally operate in the saturation region and are not sensitive to changes in VDS (the drain-source voltage difference of the MOS transistor).

[0053] The source of the third PMOS transistor M4 is connected to the emitter of the first transistor, and the gate of the third PMOS transistor M4 is connected to the gate of the second PMOS transistor M5. The drain of the third PMOS transistor M4 is connected to the drain and gate of the fourth NMOS transistor M3, the gate of the fourth NMOS transistor M3 is connected to the gate of the first NMOS transistor M2, and the source of the fourth NMOS transistor M3 is connected to ground. The current on the third PMOS transistor M4 is replicated to the first NMOS transistor M2 and the second NMOS transistor M1 through the fourth NMOS transistor M3. The fourth NMOS transistor M3, the first NMOS transistor M2, and the second NMOS transistor M1 form a current mirror.

[0054] like Figure 1 As shown, the signals isns_high and isns_low are then sent to the digital control unit. The working logic is as follows: when the load current jumps to a value exceeding the threshold iload_high, isns_high becomes 0. Therefore, the current on the second PMOS transistor M5 inside the LDO exceeds the threshold iload_high, and isns_low will also necessarily become 0. The digital control unit controls an N-bit binary counter to continuously increment. As the counter value increases, the counter signal and the switch it controls use binary code instead of thermometer code. The counter signal DAC_counter will activate the corresponding switch Sx according to the current value, causing the base current of the external PNP transistor to increase linearly. According to Ic = Ib * β, where β is the current amplification factor of the PNP transistor, Ic is the collector current, and Ib is the base current, the collector current of the PNP transistor will increase linearly, thus reducing the current on the second PMOS transistor M5 inside the LDO. The load current RL is equal to the sum of the collector current of the PNP transistor and the current of the second PMOS transistor M5. With a constant load current RL, an increase in the collector current of the PNP transistor will decrease the current of the second PMOS transistor M5. As the counter signal increments, isns_high eventually becomes 1, at which point the counter remains active. During this process, isns_low remains 0. When there are enough counter bits, meaning the current change caused by each counter step is sufficiently small, it can be assumed that in this case, when the counter remains active, the current on the second PMOS transistor M5 inside the LDO is less than but almost equal to iload_high, and the remaining load current is borne by the PNP transistor. This achieves current distribution between the PNP transistor and the second PMOS transistor M5. Since the second PMOS transistor M5 and the PNP transistor are connected in parallel, this essentially also represents power distribution between them.

[0055] It should be noted that the comparators that generate isns_high and isns_low can also be voltage-type, which means that the current flowing through the resistor is linearly converted into a voltage signal, and then the voltage signal is compared with the generated reference voltage.

[0056] When the load current jumps down to a value higher than iload_low, two cases need to be discussed: If the current of the second PMOS transistor M5 does not decrease below iload_low (i.e., the absolute value of the load current is relatively high), the signal isns_high is 1, isns_low is 0, and the counter remains active. In this case, the entire decrease in the load current RL is applied to the second PMOS transistor M5. If the current of the second PMOS transistor M5 decreases below iload_low (i.e., the absolute value of the load current is relatively low), the signal isns_high is 1, isns_low is 1, and the counter decrements, following the same incrementing logic as described above. As the current on the PNP transistor gradually decreases, the current on the second PMOS transistor M5 gradually increases, eventually causing isns_low to return to 0. At this point, the conditions of isns_high being 1, isns_low being 0, and the counter remaining active are met again. The current on the second PMOS transistor M5 is greater than but almost equal to iload_low, thus achieving a redistribution of current between the PNP transistor and the second PMOS transistor M5.

[0057] Furthermore, when the load current increases from 0 but does not reach iload_high, isns_high is 1 and isns_low is 0, and the counter remains in its initial state (0, no current in the PNP transistor). When the load current gradually decreases from high to low until it is lower than iload_low, isns_high is 1 and isns_low is 1, and the counter decreases until it reaches 0. Because the total load is less than iload_low, the current on the second PMOS transistor M5 cannot exceed iload_low, so isns_low will never become 0 again until the counter decreases to 0.

[0058] like Figure 5 As shown, the current distribution of the second PMOS transistor M5 and the current of the PNP transistor varies with the load current Iload. The distribution circuit provided in this embodiment can control the on-chip distributed load current to a low level, and the thresholds of iload_high and iload_low can be set according to actual needs.

[0059] like Figure 2 As shown, it also includes a first inverter INV1 and a second inverter INV2;

[0060] The drain of the first NMOS transistor M2 and the input of the first inverter INV1 are both connected to the first current source I2. The drain of the second NMOS transistor M1 and the input of the second inverter INV2 are both connected to the second current source I1. The outputs of the first inverter INV1 and the second inverter INV2 are both connected to the input of the digital control unit.

[0061] This application embodiment utilizes the polarity of two signals output from the first inverter INV1 and the second inverter INV2 to indicate the magnitude of the internal current of the low-voltage linear regulator, thereby controlling the current of the external transistor. Based on the polarity of the two signals, it controls whether the counter in the digital control unit increments or decrements or maintains the original control logic, thereby controlling the opening or closing of the switch, and thus controlling the magnitude of the base current flowing into the transistor. This application directly applies the two signals output from the first inverter INV1 and the second inverter INV2 to the base of the transistor, but indirectly ensures that the on-chip current is below the set threshold, thus realizing the current distribution between the low-voltage linear regulator and the transistor according to the design value.

[0062] Preferred, such as Figure 3 As shown, in Figure 1 and Figure 2 Based on this, the current sampling circuit also includes a second error amplifier EA2;

[0063] The positive input terminal of the second error amplifier EA2 is connected to the drain of the third PMOS transistor M4, and the negative input terminal of the second error amplifier EA2 is connected to the drain of the second PMOS transistor M5; the output terminal of the second error amplifier EA2 is connected to the gate of the fourth NMOS transistor M3.

[0064] With the addition of a second error amplifier EA2, the current sampling circuit forms a negative feedback loop. This negative feedback loop ensures that the drain voltages of the third PMOS transistor M4 and the second PMOS transistor M5 are equal, thereby improving accuracy. If high accuracy is not required, the second error amplifier EA2 can be omitted. This application uses a current sampling circuit to ensure that VDS (drain-source voltage) is equal in the second PMOS transistor M5 and the third PMOS transistor M4.

[0065] It should be noted that the method of acquiring the current on the second PMOS transistor M5 is different. Since the third PMOS transistor M4 and the second PMOS transistor M5 operate in the saturation region most of the time, they are not sensitive to changes in VDS (drain-source voltage of the MOS transistor). If the accuracy requirement is not high, the second error amplifier EA2 can be omitted to clamp the drain voltage of the third PMOS transistor M4 and the second PMOS transistor M5.

[0066] In a preferred embodiment of this application, the load RL is connected in parallel with the current sampling circuit containing the first resistor R1 and the second resistor R2. One end of the load RL is connected to one end of the first resistor R1, and the other end of the load RL is connected to the end of the second resistor R2 furthest from the first resistor R1. It should be noted that the load is an internal load of the LDO.

[0067] As a preferred embodiment of this application, it also includes a capacitor CL:

[0068] The upper plate of the capacitor CL is connected to one end of the load RL, and the lower plate of the capacitor CL is connected to the other end of the load RL.

[0069] In this embodiment, capacitor CL primarily functions as a voltage regulator and filter when the load RL changes. It should be noted that capacitor CL is an external capacitor located outside the linear low-dropout regulator.

[0070] Figure 2 and Figure 3 The function of the second error amplifier EA2 is to input the drain of the second PMOS transistor M5. The second error amplifier EA2, the second PMOS transistor M5, the fourth NMOS transistor M3, and the third PMOS transistor M4 form a negative feedback loop, so that the drain voltages of the third PMOS transistor M4 and the second PMOS transistor M5 are equal, and the gate voltages and source voltages of the third PMOS transistor M4 and the second PMOS transistor M5 are also equal. From the saturation current formula of the MOS transistor I=1 / 2β*(VGS-VTH)^2*(W / L)*(1+λVDS), it can be seen that the current ratio of the third PMOS transistor M4 and the second PMOS transistor M5 is determined by their W / L ratios. Furthermore, even if the third PMOS transistor M4 and the second PMOS transistor M5 are in the linear region, according to the current formula for the linear region of MOS transistors, the current ratio of the third PMOS transistor M4 and the second PMOS transistor M5 is still determined by their respective W / L ratios. Here, let (W / L)M5 / (W / L)M4 = k1, then IM4 = IM5 / k1. Since the resistances of the first resistor R1 and the second resistor R2 are much larger than the load RL, IM5 = iload (load current). In this way, the load current of the LDO can be converted into an internal current with a certain proportional coefficient. Because this internal current is used to compare with the magnitude of the internal current source, it is essentially current sampling to obtain information about the load current; if the size of the load current cannot be known, the subsequent circuits cannot be controlled.

[0071] Next, the current of the fourth NMOS transistor M3 (i.e., the current of the third PMOS transistor M4) is copied to the second NMOS transistor M1 (the first NMOS transistor M2) at a certain ratio using a current mirror. This ratio k2 = I(M1 or IM2) / IM3, so IM1 or IM2 = k2*IM5 / k1. Appropriate values ​​are set for the second current source I1 and the first current source I2, such that when IM1 > I1 and IM2 > I2, the signals isns_high and isns_low transition from low to high. The comparison between the second NMOS transistor M1 and the second current source I1, and between the first NMOS transistor M2 and the first current source I2, can also be seen as a comparator comparing two current signals. The threshold of the comparator is determined by IM1 = I1 and IM2 = I2. A reasonable threshold needs to be set so that the toggle threshold of isns_high, iload_high, is higher than the toggle threshold of isns_low, iload_low; that is, when the load current exceeds iload_high, the signal isns_high toggles from low to high, and vice versa when the load current is lower than iload_high; the toggle of isns_low is similar.

[0072] As shown in the figure Figure 2 and Figure 3As shown, the signals isns_high and isns_low are then sent to the digital control unit. The working logic is as follows: when the load current jumps to a value exceeding the threshold iload_high, isns_high becomes 1. Therefore, the current on the second PMOS transistor M5 inside the LDO exceeds the threshold iload_high, and isns_low will also necessarily become 1. The digital control unit controls an N-bit binary counter to continuously accumulate. As the counter value increases, the counter signal and the switch it controls use binary code instead of thermometer code. The counter signal DAC_counter will open the corresponding switch Sx according to the current value, causing the base current of the external PNP transistor to increase linearly. Also, Ic = Ib * β, where β is the current amplification factor of the PNP transistor, Ic is the collector current, and Ib is the base current. Therefore, the collector current of the PNP transistor will also increase linearly. However, when the load RL is constant, as the current on the PNP transistor increases, the current on the second PMOS transistor M5 inside the LDO decreases. Because the load current RL is constant, its magnitude equals the sum of the current of the PNP transistor and the current of the second PMOS transistor M5. As the current of the PNP transistor increases, the current of the second PMOS transistor M5 decreases. As the counter signal increments, isns_high eventually becomes 0, at which point the counter remains active. During this process, isns_low remains 1. When there are enough counter bits, meaning the current change caused by each counter step is sufficiently small, it can be assumed that in this case, when the counter remains active, the current on the second PMOS transistor M5 inside the LDO is less than but almost equal to iload_high, and the remaining load current is borne by the PNP transistor. This achieves current distribution between the PNP transistor and the second PMOS transistor M5. Since the second PMOS transistor M5 and the PNP transistor are connected in parallel, this essentially also represents power distribution between them.

[0073] It should be noted that the comparators that generate isns_high and isns_low can also be voltage-type, that is, the current flows through the resistor and is linearly converted into a voltage signal, and then the voltage signal is compared with the generated reference voltage.

[0074] When the load current drops to a value higher than iload_low, two cases need to be discussed: First, if the current of the second PMOS transistor M5 does not decrease below iload_low (i.e., the absolute value of the load current is relatively high), the signals isns_high and isns_low are 0, and the counter remains active. In this case, the entire decrease in the load current RL is applied to the second PMOS transistor M5. Second, if the current of the second PMOS transistor M5 decreases below iload_low (i.e., the absolute value of the load current is relatively low), the signals isns_high and isns_low are 0, and the counter decrements, following the same incrementing logic as described above. As the current on the PNP transistor gradually decreases, the current on the second PMOS transistor M5 gradually increases, eventually causing isns_low to return to 1. At this point, the conditions of isns_high being 0, isns_low being 1, and the counter remaining active are met again. The current on the second PMOS transistor M5 is greater than but almost equal to iload_low, thus achieving a redistribution of current between the PNP transistor and the second PMOS transistor M5.

[0075] Furthermore, when the load current increases from 0 but does not reach iload_high, isns_high is 0 and isns_low is 1, and the counter remains in its initial state (0, no current in the PNP transistor). When the load current gradually decreases from high to low until it is lower than iload_low, isns_high is 0 and isns_low is 0, and the counter decreases until it reaches 0. Because the total load is less than iload_low, the current on the second PMOS transistor M5 cannot exceed iload_low, so isns_low will never become 1 again until the counter decreases to 0.

[0076] like Figure 5 As shown, the current distribution of the second PMOS transistor M5 and the current of the PNP transistor varies with the load current Iload. The distribution circuit provided in this embodiment can control the on-chip distributed load current to a low level, and the thresholds of iload_high and iload_low can be set according to actual needs.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A control circuit for a low-dropout linear regulator on-chip and an off-chip transistor current distribution circuit, characterized by, The triode and low dropout linear regulator are included; The low dropout linear regulator includes a negative feedback loop and a current sampling circuit; The triode emitter and collector are connected with the negative feedback loop and the current sampling circuit; One end of the negative feedback loop is connected with the reference voltage, and the other end of the negative feedback loop is connected with the triode collector; One end of the current sampling circuit is connected with the load, and the other end of the current sampling circuit is connected with the gate of the first NMOS tube and the gate of the second NMOS tube in turn, the drain of the first NMOS tube is connected with the first current source, and the drain of the second NMOS tube is connected with the second current source; The common end between the drain of the first NMOS tube and the first current source is connected with the digital control unit input end, the common end between the drain of the second NMOS tube and the second current source is connected with the digital control unit input end, and the opening or closing of the switch is controlled through the digital control unit, so as to control the current flowing into the triode base.

2. The control circuit for the low-dropout linear regulator and off-chip transistor current sharing circuit of claim 1, wherein, The first inverter and the second inverter are further included; The drain of the first NMOS tube and the input end of the first inverter are connected with the first current source, and the drain of the second NMOS tube and the input end of the second inverter are connected with the second current source; The output end of the first inverter and the output end of the second inverter are connected with the digital control unit input end.

3. The control circuit for the low-dropout linear regulator and off-chip transistor current allocation circuit of claim 1, wherein, The negative feedback loop includes a first error amplifier, a third NMOS tube, a first PMOS tube, a second PMOS tube, a first resistor and a second resistor; The common end between the first resistor and the second resistor is connected with the negative input end of the first error amplifier; The output end of the first error amplifier is connected with the gate of the third NMOS tube, the source of the third NMOS tube is connected with the ground end, the drain of the third NMOS tube is connected with the drain and gate of the first PMOS tube, the gate and drain of the first PMOS tube are connected with the gate of the second PMOS tube, the drain of the second PMOS tube is connected with the collector of the triode and one end of the first resistor, and the other end of the second resistor away from the first resistor is connected with the ground end; The source of the first PMOS tube and the source of the second PMOS tube are connected with the emitter of the triode.

4. The control circuit for the low-dropout linear regulator and off-chip transistor current allocation circuit of claim 3, wherein, The current sampling circuit includes a third PMOS tube, a second PMOS tube and a fourth NMOS tube; The source of the third PMOS tube is connected with the emitter of the triode, the gate of the third PMOS tube is connected with the gate of the second PMOS tube, the drain of the third PMOS tube is connected with the drain and gate of the fourth NMOS tube, the gate of the fourth NMOS tube is connected with the gate of the first NMOS tube, and the source of the fourth NMOS tube is connected with the ground end.

5. A control circuit for a low-dropout linear regulator on-chip and off-chip transistor current allocation circuit as defined in claim 4, wherein, The current sampling circuit further includes a second error amplifier; The positive input end of the second error amplifier is connected with the drain of the third PMOS tube, and the negative input end of the second error amplifier is connected with the drain of the second PMOS tube. The output end of the second error amplifier is connected with the gate of the fourth NMOS tube.

6. The control circuit of claim 2, wherein the current distribution circuit comprises a first resistor and a second resistor, and the load is connected in parallel with the first resistor and the second resistor. The load is connected in parallel with the circuit in which the first resistor and the second resistor are located, one end of the load is connected with one end of the first resistor, and the other end of the load is connected with the ground end.

7. A control circuit for a low-dropout linear regulator on-chip and off-chip transistor current allocation circuit as defined in claim 6, wherein, Further comprising a capacitor: One end of the capacitor is connected with one end of the load, and the other end of the capacitor is connected with the other end of the load.

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