A three-node flip-flop fault-tolerant latch suitable for harsh radiation environments

Abstract

This application relates to a three-node flip-flop fault-tolerant latch suitable for harsh radiation environments in the field of integrated circuit design technology. The latch includes: an excitation module for transmitting input signals to sensitive nodes N2, N4, N6, and Q through multiple clock-controlled transmission gates; an interlock feedback loop consisting of four three-input clock-gated inverting CE units and four three-input inverting CE units; a module responsible for generating voltages for sensitive nodes N1, N3, N5, and N7, and for achieving interference self-recovery of sensitive nodes N1 to N7 and Q based on signals from sensitive nodes A and B; and an AB node generation and recovery module using two four-input inverting CE units and inversion operation to generate voltages for sensitive nodes A and B from signals from N1 to N7 and Q. This latch has good TNU (Terror-Noise Nullification) immunity, enabling three-node flip-flop recovery even when any three sensitive nodes experience a TNU.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology and relates to a three-node flip-flop fault-tolerant latch suitable for harsh radiation environments. Background Technology

[0002] As semiconductor feature sizes continue to shrink, while performance and power efficiency improve, new challenges emerge. The reduction in supply voltage, node capacitance, and the critical charge at electronic circuit nodes makes them more susceptible to radiation-induced soft errors. Large electron-hole pairs are generated when particles interact with sensitive areas of integrated circuits. These electron-hole pairs accumulate in the depletion regions of the circuit, leading to transient pulses induced by ionized particles, commonly known as single-event transients (SETs). In digital storage circuits, the occurrence of SETs can cause data corruption, a phenomenon known as single-event upsets (SEUs).

[0003] As the feature size of transistors continues to shrink and the density of integrated circuits increases, the impact of particle bombardment on circuits becomes increasingly significant. These bombardments generate electron-hole pairs, potentially affecting multiple nodes in the circuit. When two nodes are affected, this is called a two-node flip (DNU). Due to the widespread charge distribution, it accumulates not only at the bombarded location but also in its vicinity, leading to a large charge collection. Therefore, other locations may not accumulate enough charge to trigger a node state flip. In current multi-node flip cases, the most common scenario is two-node flip. To address two-node flip, some literature has begun to study anti-two-node flip latches. When any two nodes are disturbed through a feedback loop, this latch can achieve self-recovery, and its structure is as follows: Figure 1 As shown. However, the structure has the following drawback: when a partial three-node pair flip (TNU) occurs, the latch cannot recover.

[0004] Therefore, there is an urgent need for a latch design scheme that is TNU resistant. Summary of the Invention

[0005] To address the problems existing in the above-mentioned traditional methods, this invention proposes a three-node flip-tolerant latch suitable for harsh radiation environments, which can achieve three-node flip-tolerance recovery when any three sensitive nodes experience a TNU (Total Nullification Nullification) condition.

[0006] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0007] On the one hand, a three-node flip-flop fault-tolerant latch suitable for harsh radiation environments is provided, comprising:

[0008] The excitation module is used to transmit the input signal to the sensitive nodes N2, N4, N6 and Q through multiple clocked transmission gates;

[0009] The interlocked feedback loop is a three-node flip feedback loop composed of four three-input clock-gated inverting CE units CE1, CE3, CE5, and CE7 and four three-input inverting CE units CE2, CE4, CE6, and CE8; it is responsible for the voltage generation of sensitive nodes N1, N3, N5, and N7, and also for the interference self-recovery of sensitive nodes N1 to N7 and Q;

[0010] The AB node generation and recovery module is used to process the signals of sensitive nodes N1 to N7 and Q using two four-input inverted CE units and inversion operation, and feeds back the processing results to sensitive nodes A and B.

[0011] In one embodiment, in the interlocked feedback loop, the first input terminal of CE1 and the output terminal of CE8 are both connected to sensitive node N1; the output terminal of CE1 and the first input terminal of CE2 are both connected to sensitive node N2; the output terminal of CE2 and the first input terminal of CE3 are both connected to sensitive node N3; the output terminal of CE3 and the first input terminal of CE4 are both connected to sensitive node N4; the output terminal of CE4 and the first input terminal of CE5 are both connected to sensitive node N5; the output terminal of CE5 and the first input terminal of CE6 are both connected to sensitive node N6; and the output terminal of CE6 and the first input terminal of CE7 are both connected to sensitive node N1. Node N7 is connected, and the output of CE7 and the first input of CE8 are both connected to sensitive node Q; the second inputs of CE1, CE3, CE5, and CE7 are all connected to sensitive node A, and the third inputs of CE1, CE3, CE5, and CE7 are connected to sensitive nodes N7, N1, N3, and N5, respectively; the second inputs of CE2, CE4, CE6, and CE8 are all connected to control node B, and the third inputs of CE2, CE4, CE6, and CE8 are connected to sensitive nodes Q, N2, N4, and N6, respectively; the enable terminals of CE2, CE4, CE6, and CE8 all receive the clock signal CLK.

[0012] In one embodiment, the AB node generation and recovery module includes: two four-input inverted CE units CE9 and CE10 and two inverters;

[0013] The output of CE9 is connected to the input of the first inverter, the output of the first inverter is connected to the sensitive node A, and the four inputs of CE9 are connected to the agile nodes N1, N3, N5 and N7 respectively.

[0014] The output of CE10 is connected to the input of the second inverter, the output of the second inverter is connected to the sensitive node B, and the four inputs of CE10 are connected to the agile nodes N2, N4, N6 and Q respectively.

[0015] In one embodiment, the excitation module includes four transmission gates TG1 to TG4; each transmission gate includes an NMOS transistor and a PMOS transistor, with the drain of the NMOS transistor and the source of the PMOS transistor connected together as the input terminal of the transmission gate, and the drain of the NMOS transistor and the source of the PMOS transistor connected together as the output terminal of the transmission gate.

[0016] The clock signal CLK is connected to the gate of the NMOS transistors TG1 to TG4, and the clock signal CLK is connected to the gate of the PMOS transistors TG1 to TG4 through an inverter; the input terminals of TG1, TG2, TG3, and TG4 are all connected to the data input terminal, and the output terminals of TG1, TG2, TG3, and TG4 are connected to the sensitive nodes N2, N4, N6, and Q, respectively.

[0017] In one embodiment, when the clock signal CLK=1, the three-node flip-flop fault-tolerant latch operates in transparent mode; transmission gates TG1 to TG4 are turned on, and input data D is directly transmitted to sensitive nodes N2, N4, N6, and Q; CE1, CE3, CE5, and CE7 are not turned on, and sensitive nodes N1, N3, N5, and N7 are written through CE2, CE4, CE6, and CE8, while other sensitive nodes remain unchanged.

[0018] In one embodiment, when the clock signal CLK=0, the three-node flip-tolerant latch operates in hold mode; transmission gates TG1 to TG4 are closed, N2, N4, N6 and Q remain unchanged, while CE1, CE3, CE5 and CE7 are open, and CE1 to CE8 together form a feedback interlock circuit to ensure the stability of the latch.

[0019] One of the above technical solutions has the following advantages and beneficial effects:

[0020] The aforementioned three-node flip-flop fault-tolerant latch, suitable for harsh radiation environments, comprises: an excitation module for transmitting input signals to sensitive nodes N2, N4, N6, and Q through multiple clock-controlled transmission gates; an interlock feedback loop consisting of four three-input clock-gated inverting CE units and four three-input inverting CE units; a module responsible for generating voltages for sensitive nodes N1, N3, N5, and N7, and for achieving interference self-recovery of sensitive nodes N1 to N7 and Q based on signals from sensitive nodes A and B; and an AB node generation and recovery module for generating voltages for sensitive nodes A and B using two four-input inverting CE units and inversion operation on signals from N1 to N7 and Q. This latch exhibits excellent TNU (Terror-Nutrition Nullification) immunity, enabling three-node flip-flop recovery even when any three sensitive nodes experience a TNU. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a block diagram of an anti-DNU flip-flop latch in the prior art;

[0023] Figure 2 This is a block diagram of a three-node flip-flop fault-tolerant latch suitable for harsh radiation environments in one embodiment.

[0024] Figure 3 This is a schematic diagram of the internal workings of CE4 in one embodiment;

[0025] Figure 4 This is a schematic diagram of the internal workings of CE3 in one embodiment;

[0026] Figure 5 This is a schematic diagram of the internal workings of CE10 in one embodiment;

[0027] Figure 6 This is a timing diagram of each node during normal operation in one embodiment;

[0028] Figure 7 This is a timing diagram of each node during TN1 in one embodiment;

[0029] Figure 8 This is a timing diagram of each node in TN2 of one embodiment;

[0030] Figure 9 This is a timing diagram of each node in TN3 of one embodiment;

[0031] Figure 10 This is a timing diagram of each node in TN4 of one embodiment;

[0032] Figure 11 This is a timing diagram of each node in TN5 of one embodiment;

[0033] Figure 12 This is a timing diagram of each node in TN6 of one embodiment;

[0034] Figure 13 This is a timing diagram of each node during TN7 in one embodiment. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0037] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, including such combinations.

[0038] CE unit, full name: C-elements, also known as C unit, abbreviated as CE unit.

[0039] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0040] In one embodiment, such as Figure 2 As shown, a three-node flip-flop fault-tolerant latch suitable for harsh radiation environments is provided, comprising:

[0041] The excitation module 10 is used to transmit the input signal to the sensitive nodes N2, N4, N6 and Q through multiple clocked transmission gates.

[0042] Specifically, the excitation module 10 charges the sensitive nodes N2, N4, N6 and Q through four clocked transmission gates.

[0043] The interlocked feedback loop 20 is a three-node flip feedback loop composed of four three-input clock-gated inverted CE units CE1, CE3, CE5, and CE7 and four three-input inverted CE units CE2, CE4, CE6, and CE8; it is responsible for the voltage generation of sensitive nodes N1, N3, N5, and N7, and also for the interference self-recovery of sensitive nodes N1 to N7 and Q.

[0044] Specifically, CE2, CE4, CE6, and CE8 are three-input inverting CE units (the input voltage is reversed when all three inputs are the same, and remains unchanged when the three inputs are different). CE1, CE3, CE5, and CE7 are clock-gated three-input inverting CE units (the voltage remains unchanged when CLK=1, and operates on the same principle as a three-input inverting CE when CLK=0). These eight CE units together form a feedback loop. Nodes N2, N4, N6, and Q are connected by D through four transmission gates, while CE9 and CE10 are four-input inverting CE units (the input voltage is reversed when all four inputs are the same, and remains unchanged when the four inputs are different).

[0045] CE1 to CE8 are all three-input CE units. This design is intended to prevent three-input switching. Another advantage is that the three-input CE can completely prevent dual-node switching, thus avoiding temporary interference to the normal node due to the feedback loop when dual-node switching occurs.

[0046] Compared to the DNU-resistant flip-flop latch, since there is no dual-node co-directional CE unit, this invention can completely isolate DNU, ensuring that no more nodes are affected when DNU occurs. Specifically, this is reflected in: in... Figure 1 In the DNU-resistant flip-flop latch shown, if...<N_1,a> This type of DNU interference, then Figure 1 The output N_2 of CE_1 will be briefly disturbed, while in... Figure 2 Within the TNU flip-flop latch shown, no DNU will generate additional node interference.

[0047] The AB node generation and recovery module 30 is used to process the signals of sensitive nodes N1 to N7 and Q using two four-input inverted CE units and inversion operation, and feed the processing results back to sensitive nodes A and B.

[0048] Specifically, Figure 2Sensitive nodes A and B are each obtained through a four-input inverting CE element. The goal here is to prevent node A from flipping due to the flipping of any three nodes among the four sensitive nodes N1, N3, N5, and N7, or the flipping of node B due to the flipping of any three nodes among the four sensitive nodes N2, N4, N6, and N8. This prevents sensitive node A and any three of the flipped N1, N3, N5, and N7 from continuing to affect other nodes through the three-input CE element of the feedback loop, thus preventing the flipping of any three nodes among the four sensitive nodes N1, N3, N5, and N7. Similarly, it prevents sensitive node B and any three of the flipped N2, N4, N6, and N8 from continuing to affect other nodes through the three-input CE element of the feedback loop, thus preventing the flipping of any three nodes among the four sensitive nodes N2, N4, N6, and N8.

[0049] Compared to Figure 1 structure, Figure 2 The structures shown introduce more redundant nodes, which ensure that any node can recover from interference.

[0050] When CLK=1, all four transmission gates are on, and N2, N4, N6, and Q are pre-charged through D. Simultaneously, CE1, CE3, CE5, and CE7 are off. Nodes N1, N3, N5, and N7 are written to through CE2, CE4, CE6, and CE8. Due to the characteristic of four-input unidirectional CE gates, nodes N1, N3, N5, N7, and A are in phase, while nodes B, N2, N4, N6, and Q are in phase. In hold mode (CLK=0), the transmission gates are off, and N2, N4, N6, and Q remain unchanged. Simultaneously, CE1, CE3, CE5, and CE7 are on. CE1-8 together form a feedback interlock circuit, ensuring the stability of the latch.

[0051] In hold mode, the circuit consists of 10 sensitive nodes: N7, Q, A, and B. When a DNU occurs, Figure 2 The advantages of this design are as follows: when any two-node pair flips, all CE cells will not cause the next node to fail due to an input error, and Figure 1 Then it will be<N_1,a> In this type of situation, the next node is affected through CE.

[0052] The aforementioned three-node flip-flop fault-tolerant latch, suitable for harsh radiation environments, comprises: an excitation module for transmitting input signals to sensitive nodes N2, N4, N6, and Q through multiple clock-controlled transmission gates; an interlock feedback loop consisting of four three-input clock-gated inverting CE units and four three-input inverting CE units; a module responsible for generating voltages for sensitive nodes N1, N3, N5, and N7, and for achieving interference self-recovery of sensitive nodes N1 to N7 and Q based on signals from sensitive nodes A and B; and an AB node generation and recovery module for generating voltages for sensitive nodes A and B using two four-input inverting CE units and inversion operation on signals from N1 to N7 and Q. This latch exhibits excellent TNU (Terror-Nutrition Nullification) immunity, enabling three-node flip-flop recovery even when any three sensitive nodes experience a TNU.

[0053] In one embodiment, in the interlocked feedback loop 20, the first input terminal of CE1 and the output terminal of CE8 are both connected to sensitive node N1; the output terminal of CE1 and the first input terminal of CE2 are both connected to sensitive node N2; the output terminal of CE2 and the first input terminal of CE3 are both connected to sensitive node N3; the output terminal of CE3 and the first input terminal of CE4 are both connected to sensitive node N4; the output terminal of CE4 and the first input terminal of CE5 are both connected to sensitive node N5; the output terminal of CE5 and the first input terminal of CE6 are both connected to sensitive node N6; and the output terminal of CE6 and the first input terminal of CE7 are both connected to sensitive node N1. Sensing node N7 is connected, and the output of CE7 and the first input of CE8 are both connected to sensing node Q; the second inputs of CE1, CE3, CE5, and CE7 are all connected to sensing node A, and the third inputs of CE1, CE3, CE5, and CE7 are connected to sensing nodes N7, N1, N3, and N5, respectively; the second inputs of CE2, CE4, CE6, and CE8 are all connected to control node B, and the third inputs of CE2, CE4, CE6, and CE8 are connected to sensing nodes Q, N2, N4, and N6, respectively; the enable terminals of CE2, CE4, CE6, and CE8 all receive the clock signal CLK.

[0054] Specifically, the three-input inverting CE unit consists of three NMOS transistors and three CMOS transistors, with each pair of MOS transistors having the same input. According to the working principle of MOS transistors: when all three inputs are high, the output is low; when all three inputs are low, the output is high; when the three inputs are not completely identical, one MOS transistor will be cut off, exhibiting a high impedance state, causing the output to remain unchanged.

[0055] The structure of a four-input inverting CE unit is similar to that of a three-input inverting CE unit, except that the four-input inverting CE unit has four inputs. The rest of the working principle is exactly the same as that of the three-input inverting CE unit.

[0056] Compared to the standard three-input inverting CE unit, the three-input inverting CE unit with CLK has an additional pair of MOSFETs. The PMOS is connected to the input CLK, and the NMOS is connected to NCK (the inverted signal of CLK). This means that when CLK=1, the clock-controlled MOSFET is off, and the output is in a high-impedance state, remaining unchanged. When CLK=0, the clock-controlled MOSFET is on, and the operating mode of the three-input inverting CE unit with CLK is the same as that of the standard three-input inverting CE unit.

[0057] CE4 is a three-input inverting CE unit. The internal schematic diagram of CE4 is shown below. Figure 3 CE3 is a three-input inverting CE unit with CLK. The internal schematic of CE3 is shown below. Figure 4 As shown.

[0058] In one embodiment, the AB node generation and recovery module 30 includes: two four-input inverted CE units CE9 and CE10 and two inverters INV1 and INV2;

[0059] The output of CE9 is connected to the input of the first inverter INV1, the output of the first inverter INV1 is connected to the sensitive node A, and the four inputs of CE9 are connected to the agile nodes N1, N3, N5 and N7 respectively.

[0060] The output of CE10 is connected to the input of the second inverter INV2, and the output of the second inverter INV2 is connected to the sensitive node B. The four inputs of CE10 are connected to the agile nodes N2, N4, N6, and Q, respectively. A schematic diagram of the internal principle of CE10 is shown below. Figure 5 As shown.

[0061] In one embodiment, the excitation module 10 includes four transmission gates TG1 to TG4; each transmission gate includes an NMOS transistor and a PMOS transistor, with the drain of the NMOS transistor and the source of the PMOS transistor connected together as the input terminal in of the transmission gate, and the drain of the NMOS transistor and the source of the PMOS transistor connected together as the output terminal out of the transmission gate.

[0062] The clock signal CLK is connected to the gate of the NMOS transistors TG1 to TG4. The clock signal CLK is output as NCK through an inverter. The gate of the PMOS transistors TG1 to TG4 is connected to NCK. The input terminals of TG1, TG2, TG3, and TG4 are all connected to the data input terminal in. The output terminals out of TG1, TG2, TG3, and TG4 are connected to the sensitive nodes N2, N4, N6, and Q, respectively.

[0063] In one embodiment, when the clock signal CLK=1, the three-node flip-flop fault-tolerant latch operates in transparent mode; transmission gates TG1 to TG4 are turned on, and input data D is directly transmitted to sensitive nodes N2, N4, N6, and Q; CE1, CE3, CE5, and CE7 are not turned on, and sensitive nodes N1, N3, N5, and N7 are written through CE2, CE4, CE6, and CE8, while other sensitive nodes remain unchanged.

[0064] In one embodiment, when the clock signal CLK=0, the three-node toggle fault-tolerant latch operates in hold mode; transmission gates TG1 to TG4 are closed, N2, N4, N6, and Q remain unchanged, while CE1, CE3, CE5, and CE7 are open. CE1 to CE8 together form a feedback interlock circuit, ensuring the stability of the latch. Under normal operation (normal operation means: no interference, relying solely on the curves generated by the internal node drives), the timing of each node is as follows: Figure 6 As shown.

[0065] Specifically, in hold mode, when TNU occurs, there are a total of 120 possible scenarios, which can be broadly categorized into the following 7 types:

[0066] TN1: When<N1,N3,N5> In the event of a TNU attack, CE1, CE3, and CE5 will intercept the error to prevent N2, N4, and N6 from being affected. Other nodes remain unchanged, and N1 is...<Q,N6,B> Restored, N3 by<N2,Q,B> Restored, N5 by<N4,N2,B> Recovery.<N1,N3,N7> and<N2,N4,N6> Similar situations exist. There are a total of 8 such cases. The timing sequence of each node in TN1 is as follows: Figure 7 As shown.

[0067] TN2: When<N1,N3,N2> During a TNU attack, CE1, CE3, and CE2 will intercept errors to prevent N2, N4, and N3 from being affected. N1 is...<Q,N6,B> Restored, N2 from<N1,N7,A> After N2 recovers, N3 is restored.<N2,Q,B> Restore, other nodes remain unchanged.<N1,N3,N4> and<N2,N4,N5> Similar situations exist. There are a total of 48 such cases. The timing sequence of each node in TN2 is as follows: Figure 8 As shown.

[0068] TN3: When<N1,N7,A> When a TNU occurs, CE1 will propagate the error to N2. CE2 will intercept the error so that N3 is unaffected. Eventually, N1 will recover through CE8, N7 will recover through CE6, and then N2 will recover, while the remaining nodes remain unchanged.<B,N2,Q> and<A,N5,N7> Similar situations exist. There are a total of 8 cases. The timing sequence of each node in TN3 is as follows: Figure 9 As shown.

[0069] TN4: When<N1,N5,A> When subjected to TNU, N1 recovers through CE8, N5 recovers through CE4, and finally A recovers through CE9.<N3,N7,A> and<N2,N6,B> Similar situations exist. There are a total of 4 cases. The timing of each node in TN4 is as follows: Figure 10 As shown.

[0070] TN5:<N1,N7,B> When subjected to TNU, B recovers via CE10, N1 recovers via CE8, N7 recovers via CE6, and the remaining nodes remain unchanged.<A,N2,Q> ,<A,N6,Q> Similar situations exist. There are a total of 12 cases. The timing sequence of each node in TN5 is as follows: Figure 11 As shown.

[0071] TN6:<A,N1,N2> When subjected to TNU, N1 recovers first through CE8, then A recovers through CE9, and finally N2 recovers through N1, while the remaining nodes remain unchanged.<A,N1,N6> ,<A,N1,Q> Similar situations exist. There are a total of 32 possibilities. The timing sequence of each node in TN6 is as follows: Figure 12 As shown.

[0072] TN7:<A,B,N1> When subjected to TNU, B recovers first through CE10, then N1 recovers through CE8, and finally A recovers through CE9, while the remaining nodes remain unchanged.<A,B,N2> ,<A,D,N1> And so on, a total of 8 cases. The timing of each node in TN7 is as follows: Figure 13 As shown.

[0073] Compared to DNU-resistant flip-flop latches, this application features a three-node flip-flop self-recovery function. Specifically, in the DNU-resistant flip-flop latch, if a flip-flop occurs...<N1,N5,N3> ,<a,b,N1> In the event of a TNU interference scenario, all nodes in the anti-DNU flip latch will flip. Analysis of the specific solution shows that when any three nodes in this invention experience a TNU, the three nodes can be restored through redundant nodes, four-input CE, three-input CE, and clock-gated three-input CE units. Therefore, this invention has excellent anti-TNU functionality.

[0074] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0075] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and all such modifications and improvements fall within the scope of protection of this application.

Claims

1. A three-node flip-flop fault-tolerant latch suitable for harsh radiation environments, characterized in that, The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes.

2. The three-node flip flop latch suitable for harsh radiation environments of claim 1, wherein, The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes.

3. The three-node flip flop latch suitable for harsh radiation environments of claim 1, wherein, The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. 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The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip feedback loop for generating and recovering AB nodes. The application relates to a three-node flip The clock signal CLK is connected with the gate of the NMOS transistor of TG1-TG4, and the clock signal CLK is connected with the gate of the PMOS transistor of TG1-TG4 through an inverter; the input end of TG1, TG2, TG3 and TG4 is connected with the data input end, and the output end of TG1, TG2, TG3 and TG4 is connected with the sensitive nodes N2, N4, N6 and Q respectively.

4. The three-node flip flop latch suitable for harsh radiation environments of claim 1, wherein, When the clock signal CLK=1, the three-node flip-flop latch works in a transparent mode; the transmission gate TG1-TG4 is turned on, and the input data D is directly transmitted to the sensitive nodes N2, N4, N6 and Q; CE1, CE3, CE5 and CE7 are not opened, the sensitive nodes N1, N3, N5 and N7 are written through CE2, CE4, CE6 and CE8, and the other sensitive nodes remain unchanged.

5. The three-node flip flop latch suitable for harsh radiation environments of claim 1, wherein, When the clock signal CLK=0, the three-node flip-flop latch works in a holding mode; the transmission gate TG1-TG4 is closed, N2, N4, N6 and Q remain unchanged, and meanwhile CE1, CE3, CE5 and CE7 are opened, and CE1-CE8 jointly constitute a feedback interlocking circuit, which ensures the stability of the latch.

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