Oxide semiconductor 2 t0c dram non-volatile power-off testing circuit and verification method
By designing a non-volatile power-off test circuit for 2T0C DRAM, and utilizing high-impedance nodes and external transmission gate structures, the data volatility problem of 2T0C DRAM cells under power-off conditions was solved, realizing non-volatile testing and verification, and broadening its application scope.
WO2026040139A1 Publication Date: 2026-02-26PEKING UNIV
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Patent Information
- Application Number
- PCT/CN2024/118124
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-08-19
- Filing Date
- 2024-09-11
- Publication Date
- 2026-02-26
AI Technical Summary
Technical Problem
Existing oxide semiconductor 2T0C DRAM cells suffer from data volatility issues when power is off, and cannot effectively protect stored data from loss.
Method used
A non-volatile power-off test circuit for 2T0C DRAM of oxide semiconductor was designed. By introducing a high-impedance node and an external transmission gate structure, the complete power-off of the 2T0C DRAM cell of oxide semiconductor and its isolation from external circuits are realized, so as to carry out non-volatile testing and verification.
Benefits of technology
It enables non-volatile testing and verification of oxide semiconductor 2T0C DRAM cells, broadening their application scope in the post-Moore era and ensuring that data is not lost in the event of power failure.
✦ Generated by Eureka AI based on patent content.
Abstract
An oxide semiconductor 2 T0C DRAM non-volatile power-off testing circuit and verification method, relating to the technical field of information materials and devices. The testing circuit comprises an oxide semiconductor 2 T0C DRAM cell, transmission gates, an input data buffer, a current mode sense amplifier, and a bootstrap write word line driver. After a write operation of the oxide semiconductor 2 T0C DRAM cell, high-impedance nodes are introduced in the form of the transmission gates, so that the oxide semiconductor 2 T0C DRAM cell is completely powered off and isolated from an external circuit. In the present invention, non-volatility test and verification can be well performed on an oxide semiconductor 2 T0C DRAM cell, thereby broadening the application range of non-volatility of an oxide semiconductor 2 T0C DRAM, which is of great significance for the development of the oxide semiconductor 2 T0C DRAM in the post-Moore era.
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