Oxide semiconductor 2 t0c dram non-volatile power-off testing circuit and verification method

Abstract

An oxide semiconductor 2 T0C DRAM non-volatile power-off testing circuit and verification method, relating to the technical field of information materials and devices. The testing circuit comprises an oxide semiconductor 2 T0C DRAM cell, transmission gates, an input data buffer, a current mode sense amplifier, and a bootstrap write word line driver. After a write operation of the oxide semiconductor 2 T0C DRAM cell, high-impedance nodes are introduced in the form of the transmission gates, so that the oxide semiconductor 2 T0C DRAM cell is completely powered off and isolated from an external circuit. In the present invention, non-volatility test and verification can be well performed on an oxide semiconductor 2 T0C DRAM cell, thereby broadening the application range of non-volatility of an oxide semiconductor 2 T0C DRAM, which is of great significance for the development of the oxide semiconductor 2 T0C DRAM in the post-Moore era.

Description

Oxide semiconductor 2T0C DRAM non-volatile power-off test circuit and verification method TECHNICAL FIELD

[0001] The application relates to an oxide semiconductor 2T0C DRAM non-volatile power-off test circuit and verification method, and belongs to the technical field of information materials and devices. BACKGROUND

[0002] Oxide semiconductor materials are widely used in the display field due to their high light transmittance, high mobility and large-area uniformity. In recent years, with the continuous development of the integrated circuit industry, oxide semiconductor materials with low thermal budget technology have shown great potential in the fields of logic, storage and radio frequency in the later stage. Due to the wide band gap of oxide semiconductors, an ultra-low off current of less than 10 −20 A / um is realized in the oxide semiconductor transistor. Based on this unique advantage, the oxide semiconductor DRAM cell with a 2T0C structure and the system have been deeply and carefully studied. The excellent leakage characteristics reduce the requirement for the size of the storage capacitor, so that the 2T0C design can be used to store charges using the gate capacitance of the read transistor. This structure not only has the unique advantage of lossless reading operation, but also does not require a high aspect ratio capacitor, which provides a feasible solution for high-density 3D-DRAM. The latest work shows that the data retention time in the oxide semiconductor material-based 2T0C DRAM cell can reach thousands of seconds or more at a storage capacitance value of a few fF.

[0003] The excellent data retention characteristics of the oxide semiconductor material-based 2T0C DRAM cell change the data volatility of the traditional silicon-based DRAM cell. The internal structure of the oxide semiconductor material-based 2T0C DRAM cell can isolate the read and write operations from each other, and the advantage of lossless reading operation makes it have the characteristics of non-volatility. Even in the case of power supply interruption, the data stored in the DRAM storage cell will not be lost, and after the power supply is restored, the data in the memory can be read. This feature enables the non-volatile memory to protect data from being lost in the case of sudden power failure. SUMMARY

[0004] The application provides an oxide semiconductor 2T0C DRAM non-volatile power-off test circuit and verification method, which can improve the reliability of the oxide semiconductor 2T0C DRAM system.

[0005] The technical scheme provided by the application is as follows:

[0006] An oxide semiconductor 2T0C DRAM non-volatile power-off test circuit, characterized in that the 2T0C DRAM unit is connected with four transmission gates, wherein the RBL port of the 2T0C DRAM unit is connected with the OUT port of the first transmission gate, the IN port of the first transmission gate is connected with the power supply, the V EN port of the first transmission gate is connected with the V sense signal, the V EN *port of the first transmission gate is connected with the V sense signal, the RWL port of the 2T0C DRAM unit is connected with the IN port of the second transmission gate, the OUT port of the second transmission gate is connected with the I IN port of the current mode sense amplifier, the V EN port of the second transmission gate is connected with the V sense signal, the V EN *port of the second transmission gate is connected with the V sense signal; the PEQ* of the current mode sense amplifier is connected with the PEQ* signal, the VDD is connected with the power supply, the PEQ is connected with the PEQ signal, the VASEN* is connected with the VASEN* signal, the VSAEN is connected with the VSAEN signal, the CSAEN* is connected with the CSAEN* signal, the SA and SA* ports are output ports, the WWL port of the 2T0C DRAM unit is connected with the OUT port of the fourth transmission gate, the IN port of the fourth transmission gate is connected with the OUT port of the bootstrap write word line driver, the V EN port of the fourth transmission gate is connected with the V write signal, the V EN *port of the fourth transmission gate is connected with the V write signal; the VDD port of the bootstrap write word line driver is connected with the power supply, the Phase port is connected with the Phase signal, the DEC* port is connected with the WWL* Bus signal, the DEC port is connected with the WWL Bus signal, the WBL port of the 2T0C DRAM unit is connected with the OUT port of the third transmission gate, the IN port of the third transmission gate is connected with the DOUT* port of the input data buffer, the V EN port of the third transmission gate is connected with the V write signal, the V EN *port of the third transmission gate is connected with the V write signal, the VDD port of the input data buffer is connected with the power supply, the DATA port is connected with the WBL Bus signal, the TRAP* port is connected with the TRAP* signal, and the EN* port is connected with the EN* signal.

[0007] Further, the 2T0C DRAM cell is composed of a first transistor and a second transistor, and the active layer of the first transistor and the second transistor is a layer of oxide semiconductor thin film or a composite material of multi-layer oxide thin film stack, wherein the d port of the first transistor is the WBL port of the 2T0C DRAM cell, the g port of the first transistor is the WWL port of the 2T0C DRAM cell, the s port of the first transistor is connected with the g port of the second transistor, the d port of the second transistor is the RBL port of the 2T0C DRAM cell, and the s port of the second transistor is the RWL port of the 2T0C DRAM cell.

[0008] Further, the transmission gate is composed of two transistors, wherein the d port of the first transistor is connected with the s port of the second transistor, the s port of the first transistor is connected with the d port of the second transistor, the d port of the first transistor and the s port of the second transistor jointly form the IN port of the transmission gate, the s port of the first transistor and the d port of the second transistor jointly form the OUT port of the transmission gate, the g port of the first transistor is the V EN port of the transmission gate, and the g port of the second transistor is the V EN port of the transmission gate.

[0009] Further, the bootstrap write word line driver is composed of three transistors, wherein the d port of the first transistor is the DEC port of the bootstrap write word line driver, the g port of the first transistor is the VDD port of the bootstrap write word line driver, the s port of the first transistor is connected with the g port of the second transistor, the d port of the second transistor is the Phase port of the bootstrap write word line driver, the s port of the second transistor is connected with the d port of the third transistor, the g port of the third transistor is the DEC* port of the bootstrap write word line driver, the s port of the third transistor is connected with GND, and the s port of the second transistor and the d port of the third transistor jointly form the OUT port of the bootstrap write word line driver.

[0010] Further, the input data buffer is composed of four transistors, two inverters, four NAND gates, wherein the s port of the first transistor is connected to GND, the g port of the first transistor is connected to the g port of the third transistor, the d port of the first transistor is connected to the d port of the third transistor, the g port of the first transistor and the g port of the third transistor jointly constitute the DATA port of the input data buffer, the s port of the third transistor is connected to the d port of the fourth transistor, the g port of the fourth transistor is the EN* port of the input data buffer, the s port of the fourth transistor is the VDD port of the input data buffer, the g port of the second transistor is the EN* port of the input data buffer, the s port of the second transistor is connected to GND, the d port of the second transistor is connected to the d port of the third transistor and the d port of the first transistor, the g port of the second transistor is connected to the IN port of the first inverter, the OUT port of the first inverter is connected to the B port of the third NAND gate, the A port of the third NAND gate is connected to the A port of the first NAND gate, jointly constituting the TRAP* port of the input data buffer, the OUT port of the third NAND gate is connected to the B port of the fourth NAND gate, and the OUT port of the third NAND gate is also connected to the B port of the first NAND gate, the OUT port of the first NAND gate is connected to the A port of the second NAND gate, the B port of the second NAND gate is connected to the OUT port of the fourth NAND gate, the OUT port of the second NAND gate is connected to the A port of the fourth NAND gate, the OUT port of the second NAND gate is connected to the IN port of the second inverter, and the OUT port of the second inverter is the DOUT* port in the input data buffer.

[0011] Further, the NAND gate is composed of four transistors, wherein the g port of the first transistor in the NAND gate is connected to the g port of the fourth transistor, the d port of the first transistor in the NAND gate is connected to the s port of the fourth transistor, the g port of the second transistor in the NAND gate is connected to the g port of the third transistor, the d port of the second transistor in the NAND gate is connected to the s port of the first transistor, the d port of the third transistor in the NAND gate is connected to the d port of the fourth transistor, the s port of the third transistor in the NAND gate and the s port of the fourth transistor jointly constitute the VDD port of the NAND gate, connected to the power supply, the s port of the second transistor in the NAND gate is connected to GND, and the d port of the first transistor and the s port of the fourth transistor jointly constitute the OUT port of the NAND gate.

[0012] Further, the inverter is composed of two transistors, the g port of the first transistor in the inverter is connected with the g port of the second transistor in the inverter, the d port of the first transistor in the inverter is connected with the d port of the second transistor in the inverter, the g port of the first transistor in the inverter and the g port of the second transistor in the inverter jointly constitute the IN port of the inverter, and the d port of the first transistor in the inverter and the d port of the second transistor in the inverter jointly constitute the OUT port of the inverter.

[0013] Further, the current mode sense amplifier is composed of 12 transistors. Among them, the g port of the first transistor is connected with the g port of the second transistor, jointly constituting the VDD port of the current mode sense amplifier, the s port of the first transistor is connected with the s port of the second transistor, jointly connecting GND, the d port of the first transistor is connected with the s port of the third transistor, the d port of the second transistor is connected with the s port of the fourth transistor, the reference current source I REF is connected with the d port of the first transistor, the d port of the second transistor and the s port of the fourth transistor jointly constitute the I INPort, the d port of the third transistor is connected with the g port of the fourth transistor, the g port of the third transistor is connected with the d port of the fourth transistor, the d port of the third transistor is connected with the d port of the fifth transistor, the d port of the fourth transistor is connected with the d port of the sixth transistor, the g port of the fifth transistor is connected with the g port of the sixth transistor, the s port of the fifth transistor is connected with the s port of the sixth transistor, the g port of the fifth transistor and the g port of the sixth transistor jointly constitute the VSAEN port of the current mode sensitive amplifier, the s port of the fifth transistor and the s port of the sixth transistor are connected with the d port of the seventh transistor, the g port of the seventh transistor is the CSAEN* port of the current mode sensitive amplifier, the s port of the seventh transistor is the VDD port of the current mode sensitive amplifier, the d port of the eighth transistor is connected with the s port of the ninth transistor, the s port of the eighth transistor is connected with the d port of the ninth transistor, the g port of the eighth transistor is the PEQ port of the current mode sensitive amplifier, the g port of the ninth transistor is the PEQ* port of the current mode sensitive amplifier, the d port of the eighth transistor is connected with the d port of the fourth transistor, the s port of the eighth transistor is connected with the d port of the third transistor, the d port of the tenth transistor is connected with the s port of the eleventh transistor, the g port of the tenth transistor is connected with the d port of the eleventh transistor, the s port of the tenth transistor is connected with the g port of the eleventh transistor, the d port of the twelfth transistor is connected with the d port of the tenth transistor, the g port of the twelfth transistor is the VSAEN* port of the current mode sensitive amplifier, the s port of the twelfth transistor is the VDD port of the current mode sensitive amplifier, the s port of the tenth transistor is the SA output port of the current mode sensitive amplifier, and the d port of the eleventh transistor is the SA* output port of the current mode sensitive amplifier.

[0014] The application further provides an oxide semiconductor 2T0C DRAM non-volatile power-off test verification method, characterized by being divided into three steps: writing operation, holding operation and reading operation, and the test waveforms of the three operations are all based on the CLK signal provided by the external programmable gate array, and the specific steps include:

[0015] 1) in the writing operation, V sense The signal is always maintained in a low state; V write The signal becomes high at t2, V writeThe signal becomes low at the t5 moment; the EN* signal becomes low at the t2 moment and high at the t5 moment; the TRAP* signal becomes low at the t2 moment and high at the t5 moment; the WWL Bus, i.e. DEC signal, becomes high at the t2 moment and low at the t5 moment; the DEC* signal becomes low at the t2 moment and high at the t5 moment; the Phase signal becomes high at the t3 moment and low at the t4 moment; for the WBL Bus, i.e. DATA signal, if the data written into the oxide semiconductor 2T0C DRAM unit is 1, the signal becomes high at the t2 moment and low at the t5 moment; for the WBL Bus, i.e. DATA signal, if the data written into the oxide semiconductor 2T0C DRAM unit is 0, the signal is always low;

[0016] 2) In the maintaining operation, V sense The signal is always maintained at the low level; V write The signal is always maintained at the low level. When V sense The signal and V write The signals are at the low level, the WWL, WBL, RBL and RWL ports of the oxide semiconductor 2T0C DRAM unit are in the suspended state due to the high resistance characteristics of the transmission gates 1, 2, 3 and 4, and other signals are not operated, so that the oxide semiconductor 2T0C DRAM unit is in the power-off maintaining state; sense The signal and V write The signal are at the low level, the WWL, WBL, RBL and RWL ports of the oxide semiconductor 2T0C DRAM unit are in the suspended state due to the high resistance characteristics of the transmission gates 1, 2, 3 and 4, and other signals are not operated, so that the oxide semiconductor 2T0C DRAM unit is in the power-off maintaining state;

[0017] 3) In the reading operation, V sense The signal is always maintained at the high level; V write The signal is always maintained at the low level, the CSAEN* signal becomes low at the t1 moment and high at the t2 moment; the PEQ signal becomes low at the t1 moment and high at the t4 moment; the PEQ* signal becomes high at the t1 moment and low at the t4 moment; the VSAEN signal becomes high at the t2 moment and low at the t3 moment; and the VSAEN* signal becomes low at the t2 moment and high at the t3 moment.

[0018] The beneficial effects of the present application are as follows:

[0019] In order to comprehensively and completely test the non-volatility of the oxide semiconductor material 2T0C DRAM, the application proposes a new oxide semiconductor 2T0C DRAM non-volatility power-off test circuit. After the write operation of the oxide semiconductor 2T0C DRAM, a high resistance node is introduced by designing a transmission gate outside the storage unit, which realizes the complete power-off of the oxide semiconductor 2T0C DRAM unit and the isolation from the external circuit. The introduction of the high resistance node can well test and verify the non-volatility of the oxide semiconductor 2T0C DRAM unit, thereby widening the application range of the oxide semiconductor 2T0C DRAM non-volatility, and having important significance for the development of the oxide semiconductor 2T0C DRAM in the post-moore era. BRIEF DESCRIPTION OF DRAWINGS

[0020] Fig. 1 is a schematic diagram of the oxide semiconductor 2T0C DRAM non-volatility power-off test circuit module of the application;

[0021] Fig. 2 is a schematic diagram of the oxide semiconductor 2T0C DRAM unit circuit in the embodiment of the application;

[0022] Fig. 3 is a schematic diagram of the transmission gate in the embodiment of the application, wherein (1) and (2) are the module symbol and structure of the transmission gate, respectively;

[0023] Fig. 4 is a schematic diagram of the bootstrap write word line driver circuit in the embodiment of the application;

[0024] Fig. 5 is a schematic diagram of the input data buffer circuit in the embodiment of the application;

[0025] Fig. 6 is a schematic diagram of the NAND gate circuit in the embodiment of the application;

[0026] Fig. 7 is a schematic diagram of the inverter in the embodiment of the application, wherein (1) and (2) are the module symbol and structure, respectively;

[0027] Fig. 8 is a schematic diagram of the current mode sense amplifier circuit in the embodiment of the application;

[0028] Fig. 9 is a timing diagram of the non-volatility test and verification circuit in the verification method of the test circuit of the application;

[0029] Fig. 10 is a circuit timing diagram of the write operation in the verification method of the test circuit of the application;

[0030] Fig. 11 is a circuit timing diagram of the power-off holding operation in the verification method of the test circuit of the application;

[0031] Fig. 12 is a circuit timing diagram of the read operation in the verification method of the test circuit of the application. DETAILED DESCRIPTION

[0032] The application provides a non-volatile power-off test circuit of an oxide semiconductor 2T0C DRAM, as shown in Fig. 1, and the structure is as follows: the RBL port of the 2T0C DRAM unit is connected with the OUT port of the No. 1 transmission gate, the IN port of the No. 1 transmission gate is connected with a power supply, the V EN port of the No. 1 transmission gate is connected with a V sense signal, the V EN port of the No. 1 transmission gate is connected with a V sense signal. The RWL port of the 2T0C DRAM unit is connected with the IN port of the No. 2 transmission gate, the OUT port of the No. 2 transmission gate is connected with the I IN port of the current mode sense amplifier, the V EN port of the No. 2 transmission gate is connected with a V sense signal, the V EN port of the No. 2 transmission gate is connected with a V sense signal; the PEQ* of the current mode sense amplifier is connected with a PEQ* signal, the VDD is connected with a power supply, the PEQ is connected with a PEQ signal, the VASEN* is connected with a VASEN* signal, the VSAEN is connected with a VSAEN signal, the CSAEN* is connected with a CSAEN* signal, and the SA and SA* ports are output ports. The WWL port of the 2T0C DRAM unit is connected with the OUT port of the No. 4 transmission gate, the IN port of the No. 4 transmission gate is connected with the OUT port of the bootstrap write word line driver, the V EN port of the No. 4 transmission gate is connected with a V write signal, the V EN port of the No. 4 transmission gate is connected with a V write signal; the VDD port of the bootstrap write word line driver is connected with a power supply, the Phase port is connected with a Phase signal, the DEC* port is connected with a WWL* Bus signal, and the DEC port is connected with a WWL Bus signal. The WBL port of the 2T0C DRAM unit is connected with the OUT port of the No. 3 transmission gate, the IN port of the No. 3 transmission gate is connected with the DOUT* port of the input data buffer, the V EN port of the No. 3 transmission gate is connected with a V write signal, the V EN port of the No. 3 transmission gate is connected with a V write signal. The VDD port of the input data buffer is connected with a power supply, the DATA port is connected with a WBL Bus signal, the TRAP* port is connected with a TRAP* signal, and the EN* port is connected with an EN* signal.

[0033] As shown in FIG. 2, a 2T0C DRAM cell is composed of a transistor No. 1 and a transistor No. 2, the active layer of the transistor No. 1 and the transistor No. 2 includes but is not limited to all oxide semiconductor thin films and multi-layer oxide thin film stacks of various doping components and proportions and composite channels, and the transistor structure includes but is not limited to a bottom gate structure, a top gate structure, a double gate structure, a fin-type gate structure, a surround gate structure, a ring channel structure, a vertical channel structure, etc. Among them, the d port of the transistor No. 1 is the WBL port of the 2T0C DRAM cell, the g port of the transistor No. 1 is the WWL port of the 2T0C DRAM cell, the s port of the transistor No. 1 is connected with the g port of the transistor No. 2, the d port of the transistor No. 2 is the RBL port of the 2T0C DRAM cell, and the s port of the transistor No. 2 is the RWL port of the 2T0C DRAM cell.

[0034] As shown in FIG. 3, a transmission gate is composed of two transistors, wherein the d port of the transistor No. 1 is connected with the s port of the transistor No. 2, the s port of the transistor No. 1 is connected with the d port of the transistor No. 2, the d port of the transistor No. 1 and the s port of the transistor No. 2 together constitute the IN port of the transmission gate, the s port of the transistor No. 1 and the d port of the transistor No. 2 together constitute the OUT port of the transmission gate, the g port of the transistor No. 1 is the V EN port of the transmission gate, and the g port of the transistor No. 2 is the V EN port of the transmission gate.

[0035] As shown in FIG. 4, a bootstrap write word line driver is composed of three transistors, wherein the d port of the transistor No. 1 is the DEC port of the bootstrap write word line driver, the g port of the transistor No. 1 is the VDD port of the bootstrap write word line driver, the s port of the transistor No. 1 is connected with the g port of the transistor No. 2, the d port of the transistor No. 2 is the Phase port of the bootstrap write word line driver, the s port of the transistor No. 2 is connected with the d port of the transistor No. 3, the g port of the transistor No. 3 is the DEC* port of the bootstrap write word line driver, the s port of the transistor No. 3 is connected with GND, and the s port of the transistor No. 2 and the d port of the transistor No. 3 together constitute the OUT port of the bootstrap write word line driver.

[0036] As shown in Figure 5, the input data buffer is composed of four transistors, two inverters, four NAND gates. Among them, the NAND gate is composed of four transistors, as shown in Figure 6, the g port of No. 1 transistor in the NAND gate is connected with the g port of No. 4 transistor, the d port of No. 1 transistor in the NAND gate is connected with the s port of No. 4 transistor, the g port of No. 2 transistor in the NAND gate is connected with the g port of No. 3 transistor, the d port of No. 2 transistor in the NAND gate is connected with the s port of No. 1 transistor, the d port of No. 3 transistor in the NAND gate is connected with the d port of No. 4 transistor, the s port of No. 3 transistor in the NAND gate is connected with the s port of No. 4 transistor, which together constitute the VDD port of the NAND gate, connected with the power supply, the s port of No. 2 transistor in the NAND gate is connected with the GND, and the d port of No. 1 transistor is connected with the s port of No. 4 transistor, which together constitute the OUT port of the NAND gate. The inverter is composed of two transistors, as shown in Figure 7, the g port of No. 1 transistor in the inverter is connected with the g port of No. 2 transistor in the inverter, the d port of No. 1 transistor in the inverter is connected with the d port of No. 2 transistor in the inverter, the g port of No. 1 transistor in the inverter is connected with the g port of No. 2 transistor in the inverter, which together constitute the IN port of the inverter, and the d port of No. 1 transistor in the inverter is connected with the d port of No. 2 transistor in the inverter, which together constitute the OUT port of the inverter.

[0037] The s port of the first transistor in the input data buffer is connected to GND, the g port of the first transistor in the input data buffer is connected to the g port of the third transistor in the input data buffer, the d port of the first transistor in the input data buffer is connected to the d port of the third transistor in the input data buffer, and the g port of the first transistor in the input data buffer and the g port of the third transistor in the input data buffer together constitute the DATA port of the input data buffer. The s port of the third transistor in the input data buffer is connected to the d port of the fourth transistor, the g port of the fourth transistor is the EN* port of the input data buffer, and the s port of the fourth transistor is the VDD port of the input data buffer. The g port of the second transistor in the input data buffer is the EN* port of the input data buffer, the s port of the second transistor is connected to GND, and the d port of the second transistor is connected to the d port of the third transistor and the d port of the first transistor. The g port of the second transistor in the input data buffer is connected to the IN port of the first inverter in the input data buffer, and the OUT port of the first inverter in the input data buffer is connected to the B port of the third NAND gate. The A port of the third NAND gate in the input data buffer is connected to the A port of the first NAND gate, together constituting the TRAP* port of the input data buffer. The OUT port of the third NAND gate in the input data buffer is connected to the B port of the fourth NAND gate, and the OUT port of the third NAND gate is also connected to the B port of the first NAND gate. The OUT port of the first NAND gate in the input data buffer is connected to the A port of the second NAND gate, the B port of the second NAND gate is connected to the OUT port of the fourth NAND gate, the OUT port of the second NAND gate is connected to the A port of the fourth NAND gate, the OUT port of the second NAND gate is connected to the IN port of the second inverter, and the OUT port of the second inverter is the DOUT* port of the input data buffer.

[0038] As shown in FIG. 8, the current-mode sense amplifier is composed of 12 transistors. Among them, the g port of the first transistor in the current-mode sense amplifier is connected to the g port of the second transistor, together constituting the VDD port of the current-mode sense amplifier, and the s port of the first transistor in the current-mode sense amplifier is connected to the s port of the second transistor, together connected to GND. The d port of the first transistor in the current-mode sense amplifier is connected to the s port of the third transistor, and the d port of the second transistor in the current-mode sense amplifier is connected to the s port of the fourth transistor. The reference current source I REF The d port of the first transistor is connected to the d port of the second transistor, and the s port of the fourth transistor is connected to the s port of the third transistor, together constituting the I INThe d port of the transistor No. 3 in the current mode sensitive amplifier is connected with the g port of the transistor No. 4, and the g port of the transistor No. 3 is connected with the d port of the transistor No. 4. The d port of the transistor No. 3 in the current mode sensitive amplifier is connected with the d port of the transistor No. 5, and the d port of the transistor No. 4 is connected with the d port of the transistor No. 6. The g port of the transistor No. 5 in the current mode sensitive amplifier is connected with the g port of the transistor No. 6, and the s port of the transistor No. 5 is connected with the s port of the transistor No. 6. The g port of the transistor No. 5 and the g port of the transistor No. 6 jointly constitute the VSAEN port of the current mode sensitive amplifier. The s port of the transistor No. 5 and the s port of the transistor No. 6 are jointly connected with the d port of the transistor No. 7, the g port of the transistor No. 7 in the current mode sensitive amplifier is the CSAEN* port of the current mode sensitive amplifier, and the s port of the transistor No. 7 is the VDD port of the current mode sensitive amplifier. The d port of the transistor No. 8 in the current mode sensitive amplifier is connected with the s port of the transistor No. 9, the s port of the transistor No. 8 is connected with the d port of the transistor No. 9, the g port of the transistor No. 8 is the PEQ port of the current mode sensitive amplifier, and the g port of the transistor No. 9 is the PEQ* port of the current mode sensitive amplifier. The d port of the transistor No. 8 in the current mode sensitive amplifier is connected with the d port of the transistor No. 4, and the s port of the transistor No. 8 is connected with the d port of the transistor No. 3. The d port of the transistor No. 10 in the current mode sensitive amplifier is connected with the s port of the transistor No. 11, the g port of the transistor No. 10 is connected with the d port of the transistor No. 11, and the s port of the transistor No. 10 is connected with the g port of the transistor No. 11. The d port of the transistor No. 12 in the current mode sensitive amplifier is connected with the d port of the transistor No. 10, the g port of the transistor No. 12 is the VSAEN* port of the current mode sensitive amplifier, and the s port of the transistor No. 12 is the VDD port of the current mode sensitive amplifier. The s port of the transistor No. 10 in the current mode sensitive amplifier is the SA output port of the current mode sensitive amplifier, and the d port of the transistor No. 11 is the SA* output port of the current mode sensitive amplifier.

[0039] The verification method of the oxide semiconductor 2T0C DRAM non-volatile power-off test circuit of the application includes three steps: writing operation, holding operation and reading operation, as shown in Fig. 9. The test waveforms of the three operations are all based on the CLK signal provided by the external programmable gate array, and the amplitude and frequency of the CLK signal are not limited in the application.

[0040] As shown in Fig. 10, in the writing operation, V sense The signal is always maintained in the low level state; V write The signal becomes high level when reaching t2, V writeThe signal becomes low at time t5; the EN* signal becomes low at time t2 and high at time t5; the TRAP* signal becomes low at time t2 and high at time t5; the WWL Bus, i.e., DEC signal, becomes high at time t2 and low at time t5; the DEC* signal becomes low at time t2 and high at time t5; the Phase signal becomes high at time t3 and low at time t4; for the WBL Bus, i.e., DATA signal, if the data written into the oxide semiconductor 2T0C DRAM cell is 1, the signal becomes high at time t2 and low at time t5; and for the WBL Bus, i.e., DATA signal, if the data written into the oxide semiconductor 2T0C DRAM cell is 0, the signal is always low.

[0041] As shown in FIG. 11, in the hold operation, V sense The signal is always maintained at a low level; V write The signal is always maintained at a low level. When V sense The signal and V write The signals are both at a low level, and the WWL, WBL, RBL, and RWL ports of the oxide semiconductor 2T0C DRAM cell are in a suspended state due to the high resistance characteristics of the transmission gates 1, 2, 3, and 4. Therefore, the present patent does not limit other signals except for the V sense The signal and V write The signals are both at a low level, and the WWL, WBL, RBL, and RWL ports of the oxide semiconductor 2T0C DRAM cell are in a suspended state due to the high resistance characteristics of the transmission gates 1, 2, 3, and 4. Therefore, the present patent does not limit other signals except for the V

[0042] As shown in FIG. 12, in the read operation, V sense The signal is always maintained at a high level; V write The signal is always maintained at a low level. For the CSAEN* signal, the signal becomes low at time t1 and high at time t2; for the PEQ signal, the signal becomes low at time t1 and high at time t4; for the PEQ* signal, the signal becomes high at time t1 and low at time t4; for the VSAEN signal, the signal becomes high at time t2 and low at time t3; and for the VSAEN* signal, the signal becomes low at time t2 and high at time t3.

[0043] It should be noted that the foregoing examples have been provided merely for the purpose of explanation and are in no way to be construed as limiting of the present application.

Claims

1. An oxide semiconductor 2T0C DRAM nonvolatile power-off test circuit characterized by comprising: 2T0C DRAM cell is connected with four transfer gates respectively, wherein, the RBL port of the 2T0C DRAM cell is connected with the OUT port of the first transfer gate, the IN port of the first transfer gate is connected with the power supply, the V EN port of the first transfer gate is connected with the V sense signal, the V EN *port of the first transfer gate is connected with the V sense signal, the RWL port of the 2T0C DRAM cell is connected with the IN port of the second transfer gate, the OUT port of the second transfer gate is connected with the I IN port of the current mode sense amplifier, the V EN port of the second transfer gate is connected with the V sense signal, the V EN *port of the second transfer gate is connected with the V sense signal; the PEQ* of the current mode sense amplifier is connected with the PEQ* signal, the VDD is connected with the power supply, the PEQ is connected with the PEQ signal, the VASEN* is connected with the VASEN* signal, the VSAEN is connected with the VSAEN signal, the CSAEN* is connected with the CSAEN* signal, the SA and SA* ports are output ports, the WWL port of the 2T0C DRAM cell is connected with the OUT port of the fourth transfer gate, the IN port of the fourth transfer gate is connected with the OUT port of the bootstrap write word line driver, the V EN port of the fourth transfer gate is connected with the V write signal, the V EN *port of the fourth transfer gate is connected with the V write signal; the VDD port of the bootstrap write word line driver is connected with the power supply, the Phase port is connected with the Phase signal, the DEC* port is connected with the WWL* Bus signal, the DEC port is connected with the WWL Bus signal, the WBL port of the 2T0C DRAM cell is connected with the OUT port of the third transfer gate, the IN port of the third transfer gate is connected with the DOUT* port of the input data buffer, the V EN port of the third transfer gate is connected with the V write signal, the V EN *port of the third transfer gate is connected with the V write signal, the VDD port of the input data buffer is connected with the power supply, the DATA port is connected with the WBL Bus signal, the TRAP* port is connected with the TRAP* signal, the EN* port is connected with the EN* signal.

2. The oxide semiconductor 2T0C DRAM nonvolatile power-off test circuit according to claim 1, characterized by The 2T0C DRAM cell is composed of a first transistor and a second transistor, and the active layer of the first transistor and the second transistor is a layer of oxide semiconductor film or a composite material of a plurality of oxide film stacks, wherein the d port of the first transistor is the WBL port of the 2T0C DRAM cell, the g port of the first transistor is the WWL port of the 2T0C DRAM cell, the s port of the first transistor is connected with the g port of the second transistor, the d port of the second transistor is the RBL port of the 2T0C DRAM cell, and the s port of the second transistor is the RWL port of the 2T0C DRAM cell.

3. The oxide semiconductor 2T0C DRAM non-volatile power-off test circuit according to claim 1, characterized by The transmission gate is composed of two transistors, wherein the d port of the first transistor is connected with the s port of the second transistor, the s port of the first transistor is connected with the d port of the second transistor, the d port of the first transistor and the s port of the second transistor jointly constitute the IN port of the transmission gate, the s port of the first transistor and the d port of the second transistor jointly constitute the OUT port of the transmission gate, the g port of the first transistor is the V EN port of the transmission gate, and the g port of the second transistor is the V EN port of the transmission gate.

4. The oxide semiconductor 2T0C DRAM non-volatile power-off test circuit according to claim 1, characterized by The bootstrap write word line driver is composed of three transistors, wherein the d port of the first transistor is the DEC port of the bootstrap write word line driver, the g port of the first transistor is the VDD port of the bootstrap write word line driver, the s port of the first transistor is connected with the g port of the second transistor, the d port of the second transistor is the Phase port of the bootstrap write word line driver, the s port of the second transistor is connected with the d port of the third transistor, the g port of the third transistor is the DEC* port of the bootstrap write word line driver, the s port of the third transistor is connected with GND, and the s port of the second transistor and the d port of the third transistor jointly form the OUT port of the bootstrap write word line driver.

5. The oxide semiconductor 2T0C DRAM non-volatile power-down test circuit according to claim 1, characterized by The input data buffer is composed of four transistors, two inverters and four NAND gates, wherein the s port of the first transistor is connected with GND, the g port of the first transistor is connected with the g port of the third transistor, the d port of the first transistor is connected with the d port of the third transistor, the g port of the first transistor and the g port of the third transistor jointly form the DATA port of the input data buffer, the s port of the third transistor is connected with the d port of the fourth transistor, the g port of the fourth transistor is the EN* port of the input data buffer, the s port of the fourth transistor is the VDD port of the input data buffer, the g port of the second transistor is the EN* port of the input data buffer, the s port of the second transistor is connected with GND, the d port of the second transistor is connected with the d port of the third transistor and the d port of the first transistor, the g port of the second transistor is connected with the IN port of the first inverter, the OUT port of the first inverter is connected with the B port of the third NAND gate, the A port of the third NAND gate is connected with the A port of the first NAND gate, and they jointly form the TRAP* port of the input data buffer, the OUT port of the third NAND gate is connected with the B port of the fourth NAND gate, and simultaneously the OUT port of the third NAND gate is connected with the B port of the first NAND gate, the OUT port of the first NAND gate is connected with the A port of the second NAND gate, the B port of the second NAND gate is connected with the OUT port of the fourth NAND gate, the OUT port of the second NAND gate is connected with the A port of the fourth NAND gate, the OUT port of the second NAND gate is connected with the IN port of the second inverter, and the OUT port of the second inverter is the DOUT* port of the input data buffer.

6. The oxide semiconductor 2T0C DRAM non-volatile power-off test circuit according to claim 5, characterized by The NAND gate is composed of four transistors, the first transistor g port in the NAND gate is connected with the g port of the fourth transistor, the first transistor d port in the NAND gate is connected with the s port of the fourth transistor, the second transistor g port in the NAND gate is connected with the g port of the third transistor, the second transistor d port in the NAND gate is connected with the s port of the first transistor, the third transistor d port in the NAND gate is connected with the d port of the fourth transistor, the third transistor s port in the NAND gate is connected with the s port of the fourth transistor, which jointly constitute the VDD port of the NAND gate, connected with the power supply, the second transistor s port in the NAND gate is connected with GND, and the d port of the first transistor and the s port of the fourth transistor jointly constitute the OUT port of the NAND gate.

7. The oxide semiconductor 2T0C DRAM non-volatile power-off test circuit according to claim 5, characterized by The inverter is composed of two transistors, the g port of the first transistor in the inverter is connected with the g port of the second transistor in the inverter, the d port of the first transistor in the inverter is connected with the d port of the second transistor in the inverter, the g port of the first transistor in the inverter is connected with the g port of the second transistor in the inverter, which jointly constitute the IN port of the inverter, and the d port of the first transistor in the inverter is connected with the d port of the second transistor in the inverter, which jointly constitute the OUT port of the inverter.

8. The oxide semiconductor 2T0C DRAM non-volatile power-off test circuit according to claim 1, characterized by The current mode sense amplifier is composed of 12 transistors. Among them, the g port of the first transistor is connected with the g port of the second transistor, and together constitutes the VDD port of the current mode sense amplifier; the s port of the first transistor is connected with the s port of the second transistor, and together connects GND; the d port of the first transistor is connected with the s port of the third transistor; the d port of the second transistor is connected with the s port of the fourth transistor; the reference current source I REF is connected with the d port of the first transistor; the d port of the second transistor and the s port of the fourth transistor together constitute the I IN port of the current mode sense amplifier; the d port of the third transistor is connected with the g port of the fourth transistor; the g port of the third transistor is connected with the d port of the fourth transistor; the d port of the third transistor is connected with the d port of the fifth transistor; the d port of the fourth transistor is connected with the d port of the sixth transistor; the g port of the fifth transistor is connected with the g port of the sixth transistor; the s port of the fifth transistor is connected with the s port of the sixth transistor; the g port of the fifth transistor and the g port of the sixth transistor together constitute the VSAEN port of the current mode sense amplifier; the s port of the fifth transistor and the s port of the sixth transistor are connected with the d port of the seventh transistor; the g port of the seventh transistor is the CSAEN* port of the current mode sense amplifier; the s port of the seventh transistor is the VDD port of the current mode sense amplifier; the d port of the eighth transistor is connected with the s port of the ninth transistor; the s port of the eighth transistor is connected with the d port of the ninth transistor; the g port of the eighth transistor is the PEQ port of the current mode sense amplifier; the g port of the ninth transistor is the PEQ* port of the current mode sense amplifier; the d port of the eighth transistor is connected with the d port of the fourth transistor; the s port of the eighth transistor is connected with the d port of the third transistor; the d port of the tenth transistor is connected with the s port of the eleventh transistor; the g port of the tenth transistor is connected with the d port of the eleventh transistor; the s port of the tenth transistor is connected with the g port of the eleventh transistor; the d port of the twelfth transistor is connected with the d port of the tenth transistor; the g port of the twelfth transistor is the VSAEN* port of the current mode sense amplifier; the s port of the twelfth transistor is the VDD port of the current mode sense amplifier; the s port of the tenth transistor is the SA output port of the current mode sense amplifier; and the d port of the eleventh transistor is the SA* output port of the current mode sense amplifier.

9. The verification method for the non-volatile power-off test circuit of the oxide semiconductor 2TOC DRAM as described in claim 1, characterized in that, The test waveform of the three operations is provided by the CLK signal of the external programmable gate array as the reference, and the specific steps include: 1) In the write operation, V sense the signal is always maintained at the low level; V write the signal becomes high at time t2, V write the signal becomes low at time t5; the EN* signal becomes low at time t2, the EN* signal becomes high at time t5; the TRAP* signal becomes low at time t2, the TRAP* signal becomes high at time t5; the WWL Bus, i.e., DEC signal, becomes high at time t2, and becomes low at time t5; the DEC* signal becomes low at time t2, the DEC* signal becomes high at time t5; the Phase signal becomes high at time t3, the Phase signal becomes low at time t4; for the WBL Bus, i.e., DATA signal, if the data written into the oxide semiconductor 2T0C DRAM cell is 1, the signal becomes high at time t2, and becomes low at time t5; for the WBL Bus, i.e., DATA signal, if the data written into the oxide semiconductor 2T0C DRAM cell is 0, the signal is always low; 2) in the hold operation, V sense signal is always maintained at a low level; V write signal is always maintained at a low level. When V sense signal and V write signal are both at a low level, due to the high resistance characteristics of the transmission gates 1, 2, 3, 4, the WWL, WBL, RBL, RWL ports of the oxide semiconductor 2T0C DRAM cell are all in a suspended state, except for V sense signal and V write signal, no operation is performed on the other signals, and the oxide semiconductor 2T0C DRAM cell is in a power-off hold state; 3) in the read operation, V sense the signal is always maintained at high level; V write the signal is always maintained at low level, for the signal CSAEN* it goes to low level at the instant tl and to high level at the instant t2; for the signal PEQ it goes to low level at the instant tl and to high level at the instant t4; for the signal PEQ* it goes to high level at the instant tl and to low level at the instant t4; for the signal VSAEN it goes to high level at the instant t2 and to low level at the instant t3; for the signal VSAEN* it goes to low level at the instant t2 and to high level at the instant t3.

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