Metal oxide semiconductor quantum well structure and preparation method thereof

Abstract

The invention provides a metal oxide semiconductor quantum well structure and a preparation method thereof. The structure comprises a substrate, a first barrier layer, a first quantum well layer, a second barrier layer, a second quantum well layer, a gate oxide layer and a gate metal layer, the first barrier layer is located between the first quantum well layer and the substrate, and the first quantum well layer is used for providing carriers for a transport interface between the second quantum well layer and the gate oxide layer; the first barrier layer and the second barrier layer are made of germanium-silicon, and the second quantum well layer is made of silicon or germanium. Thus, when a voltage is applied to the gate metal layer and the transport interface between the second quantum well layer and the gate oxide layer transports carriers, the first quantum well layer located below the second quantum well layer can inject carriers into the transport interface in a tunneling injection mode, so that the effective concentration of the carriers of the transport interface is improved, and the performance of the device is improved. Therefore, the MOS type quantum well structure with high mobility and high effective carriers is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, in particular to a metal-oxide-semiconductor quantum well structure and a preparation method thereof. BACKGROUND

[0002] Si-based quantum computing material systems are divided into three structures of heterojunction Si quantum well, heterojunction Ge quantum well and metal-oxide-semiconductor field-effect transistor (MOSFET) quantum well. Among them, the Si-based MOSFET quantum well (referred to as MOS type quantum well) is widely used due to its better compatibility with the existing complementary metal oxide semiconductor (CMOS) process. However, in the MOS type quantum well structure, the carrier localization occurs at the interface between the oxide layer and the semiconductor material, and due to the influence of the interface state, it is subjected to greater scattering, resulting in generally lower mobility, thereby making its application more obviously limited. Therefore, it is an urgent technical problem to provide a MOS type quantum well structure with higher mobility. SUMMARY

[0003] Therefore, the purpose of the present application is to provide a metal-oxide-semiconductor quantum well structure and a preparation method thereof, to improve the effective concentration of carriers at the transport interface, and to realize a MOS type quantum well structure with high mobility and high effective carriers. The specific scheme is as follows:

[0004] In one aspect, the present application provides a metal-oxide-semiconductor quantum well structure, comprising:

[0005] a substrate, and a first barrier layer, a first quantum well layer, a second barrier layer, a second quantum well layer, a gate oxide layer and a gate metal layer stacked in sequence on one side of the substrate; the first barrier layer is located between the first quantum well layer and the substrate, and the first quantum well layer is used to provide carriers to the transport interface between the second quantum well layer and the gate oxide layer.

[0006] The materials of the first barrier layer and the second barrier layer are both germanium silicon, and the material of the second quantum well layer is silicon or germanium.

[0007] In one possible implementation, in the film layer stacking direction, the thickness of the second barrier layer is greater than or equal to 1 nm and less than or equal to 60 nm.

[0008] In one possible implementation, the materials of the first quantum well layer and the second quantum well layer are the same.

[0009] In a possible implementation, when the material of the second quantum well layer is germanium, the material of the first quantum well layer is germanium tin; when the material of the second quantum well layer is silicon, the material of the first quantum well layer is silicon germanium tin.

[0010] In a possible implementation, the metal-oxide-semiconductor quantum well structure further includes:

[0011] A third barrier layer and a third quantum well layer between the substrate and the first barrier layer, the third quantum well layer being in contact with the first barrier layer.

[0012] In a possible implementation, the metal-oxide-semiconductor quantum well structure further includes:

[0013] A passivation layer between the second quantum well layer and the gate oxide layer.

[0014] In a possible implementation, when the material of the second quantum well layer is germanium, the metal-oxide-semiconductor quantum well structure further includes:

[0015] A first buffer layer between the substrate and the first barrier layer, the material of the first buffer layer being Si 1-x Ge x In the direction of the substrate pointing to the first barrier layer, the content of Ge in the first buffer layer gradually decreases.

[0016] In a possible implementation, the metal-oxide-semiconductor quantum well structure further includes:

[0017] A germanium layer between the substrate and the first buffer layer.

[0018] In a possible implementation, when the material of the second quantum well layer is silicon, the metal-oxide-semiconductor quantum well structure further includes:

[0019] A second buffer layer between the substrate and the first barrier layer, the material of the second buffer layer being Si 1-x Ge x In the direction of the substrate pointing to the first barrier layer, the content of Ge in the second buffer layer gradually increases.

[0020] In another aspect, the embodiments of the present application further provide a preparation method of a metal-oxide-semiconductor quantum well structure, including:

[0021] providing a substrate;

[0022] A first barrier layer, a first quantum well layer, a second barrier layer, a second quantum well layer, a gate oxide layer and a gate metal layer are formed in sequence on one side of the substrate by chemical vapor deposition; the first barrier layer is between the first quantum well layer and the substrate, and the first quantum well layer is configured to provide carriers to a transport interface between the second quantum well layer and the gate oxide layer.

[0023] The materials of the first barrier layer and the second barrier layer are both germanium silicon, and the material of the second quantum well layer is silicon or germanium.

[0024] The application provides a metal-oxide-semiconductor quantum well structure and a preparation method thereof. The structure comprises a substrate and a first barrier layer, a first quantum well layer, a second barrier layer, a second quantum well layer, a gate oxide layer and a gate metal layer which are sequentially stacked on one side of the substrate. The first barrier layer is between the first quantum well layer and the substrate, and the first quantum well layer is configured to provide carriers to a transport interface between the second quantum well layer and the gate oxide layer. The materials of the first barrier layer and the second barrier layer are both germanium silicon, and the material of the second quantum well layer is silicon or germanium. When a voltage is applied to the gate metal layer, the first quantum well layer below the second quantum well layer can inject carriers to the transport interface by means of tunneling injection when the transport interface between the second quantum well layer and the gate oxide layer transports carriers, so as to improve the effective concentration of carriers of the transport interface, and thus a MOS quantum well structure with high mobility and high effective carriers is realized. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0026] Figure 1 A schematic diagram of a metal-oxide-semiconductor quantum well structure provided by an embodiment of the application is shown;

[0027] Figure 2 A schematic diagram of another metal-oxide-semiconductor quantum well structure provided by an embodiment of the application is shown;

[0028] Figure 3 A flowchart of a preparation method of a metal-oxide-semiconductor quantum well structure provided by an embodiment of the application is shown;

[0029] Figure 4 A structural schematic diagram of a Ge MOS quantum well structure provided by an embodiment of the application is shown;

[0030] Figure 5 Fig. 6 shows a structure schematic diagram of another Si MOS quantum well structure provided by an embodiment of the present application;

[0031] Figure 6 Fig. 6 shows a structure schematic diagram of another Si MOS quantum well structure provided by an embodiment of the present application;

[0032] Figure 7 Fig. 6 shows a structure schematic diagram of another Si MOS quantum well structure provided by an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to make the above objectives, features and advantages of the present application more apparent, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0034] In the following description, a lot of specific details are set forth in order to facilitate a full understanding of the present application, but the present application can also be implemented in other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the connotation of the present application, therefore the present application is not limited to the specific embodiments disclosed below.

[0035] Secondly, the present application is described in detail in combination with the schematic diagram, and in the detailed description of the embodiments of the present application, for the convenience of description, the cross-sectional view showing the device structure will be partially enlarged without the general proportion, and the schematic diagram is only an example, which should not limit the scope of protection of the present application herein. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual manufacture.

[0036] As described in the background, the carrier localization of the MOS quantum well structure occurs at the interface between the oxide layer and the semiconductor material, and due to the influence of the interface state, it is subjected to greater scattering, resulting in generally lower mobility, thus its application is more obviously limited. Therefore, it is an urgent technical problem to provide a MOS quantum well structure with higher mobility.

[0037] Based on the above technical problems, this application provides a metal-oxide-semiconductor quantum well structure and its fabrication method. The structure includes a substrate and, sequentially stacked on one side of the substrate, a first barrier layer, a first quantum well layer, a second barrier layer, a second quantum well layer, a gate oxide layer, and a gate metal layer. The first barrier layer is located between the first quantum well layer and the substrate, and is used to provide charge carriers to the transport interface between the second quantum well layer and the gate oxide layer. Both the first and second barrier layers are made of germanium-silicon, and the second quantum well layer is made of silicon or germanium. Thus, when a voltage is applied to the gate metal layer, and charge carriers are transported at the transport interface between the second quantum well layer and the gate oxide layer, the first quantum well layer below the second quantum well layer can inject charge carriers into the transport interface through tunneling injection, thereby increasing the effective carrier concentration at the transport interface and achieving a MOS-type quantum well structure with high mobility and high effective charge carriers.

[0038] For ease of understanding, the following detailed description, in conjunction with the accompanying drawings, illustrates a metal-oxide-semiconductor quantum well structure and its fabrication method provided in this application.

[0039] refer to Figure 1 The diagram shown is a schematic of a metal-oxide-semiconductor quantum well structure provided in an embodiment of this application. (Refer to...) Figure 2 The diagram shown is a schematic diagram of another metal-oxide-semiconductor quantum well structure provided in an embodiment of this application.

[0040] A metal-oxide-semiconductor quantum well structure (i.e., a MOS quantum well structure) may include a substrate 101, and a first barrier layer 104, a first quantum well layer 110, a second barrier layer 106, a second quantum well layer 105, a gate oxide layer 108, and a gate metal layer 109 sequentially stacked on one side of the substrate 101. The first barrier layer 104 is located between the first quantum well layer 110 and the substrate 101. The materials of the first barrier layer 104 and the second barrier layer 106 are both germanium-silicon, and the material of the second quantum well layer 105 is silicon or germanium.

[0041] Specifically, the substrate 101 can be a silicon substrate 101, a germanium substrate 101, a silicon-on-insulator (SOI) substrate 101, or a germanium-on-insulator (GeOI) substrate 101, or other substrates 101.

[0042] That is, on the substrate 101, there are a first barrier layer 104, a first quantum well layer 110, a second barrier layer 106, a second quantum well layer 105, a gate oxide layer 108, and a gate metal layer 109 stacked sequentially from bottom to top. Among them, the two barrier layers are wide-bandgap barrier layers, also known as barrier layers, and the material of the barrier layers is germanium-silicon (Si).1-x Ge x The material of the second quantum well layer 105 can be Si or Ge. Above the second quantum well layer 105, there is also a gate oxide layer 108 and a gate metal layer 109. The material of the gate oxide layer 108 is, for example, silicon oxide, and the material of the gate metal layer 109 can be a metal. In the source and drain of the MOS quantum well structure (… Figure 1 When a voltage is applied to the gate metal layer 109 (not shown in the diagram, typically located on the left and right sides of the MOS quantum well structure), and a voltage is also applied to the gate metal layer 109, charge carriers can be transported at the interface between the second quantum well layer 105 and the gate oxide layer 108. This interface is the transport interface, thereby realizing the transport of charge carriers.

[0043] To further improve carrier mobility, a first quantum well layer 110 can be disposed below the second quantum well layer 105. The quantum wells in the second quantum well layer 105 can be considered as surface quantum wells, which are used to realize carrier transport. Specifically, carriers are transported on the upper surface of the surface quantum wells. The quantum wells in the first quantum well layer 110 can be considered as embedded quantum wells, which are used to inject carriers into the surface quantum wells. That is, the first quantum well layer 110 can be used to provide carriers to the transport interface between the second quantum well layer 105 and the gate oxide layer 108.

[0044] Thus, when a voltage is applied to the gate metal layer 109, and carriers are transported at the transport interface between the second quantum well layer 105 and the gate oxide layer 108, the first quantum well layer 110 located below the second quantum well layer 105 can inject carriers into the transport interface through tunneling injection, thereby increasing the effective carrier concentration at the transport interface and thus realizing a MOS-type quantum well structure with high mobility and high effective carriers.

[0045] In one possible implementation, the thickness of the second barrier layer 106 in the film stacking direction can be greater than or equal to 1 nm and less than or equal to 60 nm. Thus, by reasonably adjusting the thickness of the second barrier layer 106, the distance between the two quantum well layers can be adjusted. This avoids the second barrier layer 106 being too thin, which would lead to double-well coupling transport, and also avoids the second barrier layer 106 being too thick, which would prevent charge carriers in the first quantum well layer 110 from tunneling into the second quantum well layer 105, thus compromising effective charge carrier injection.

[0046] In a possible implementation, the first quantum well layer 110 and the second quantum well layer 105 are made of the same material. Specifically, in a Ge MOS quantum well structure, the two quantum well layers can both be made of Ge, and in a Si MOS quantum well structure, the two quantum well layers can both be made of Si. In this way, in the preparation of the MOS quantum well structure, since the two quantum well layers are made of the same material, the material of the quantum well layer and the material of the barrier layer can be alternately formed into corresponding film layers. In the film layer deposition process, the deposition parameters such as precursor flow, temperature, chamber pressure, and the like can be more regular, greatly reducing the process difficulty in the deposition process and simplifying the process steps.

[0047] In a possible implementation, when the material of the second quantum well layer 105 is germanium, the material of the first quantum well layer 110 is germanium tin; and when the material of the second quantum well layer 105 is silicon, the material of the first quantum well layer 110 is silicon germanium tin.

[0048] That is, in a Ge MOS quantum well structure, the material of the first quantum well layer 110 for carrier injection can also be germanium tin, which has a higher mobility, thereby improving the injection efficiency and injection amount of carriers in the first quantum well layer 110, and further realizing a Ge MOS quantum well structure with higher mobility and higher effective carriers. In a Si MOS quantum well structure, the material of the first quantum well layer 110 can be silicon germanium tin, thereby improving the injection efficiency and injection amount of carriers in the first quantum well layer 110, and further realizing a Si MOS quantum well structure with higher mobility and higher effective carriers.

[0049] In a possible implementation, the metal-oxide-semiconductor quantum well structure can further include a third barrier layer and a third quantum well layer between the substrate 101 and the first barrier layer 104, and the third quantum well layer is in contact with the first barrier layer 104.

[0050] That is, in order to further improve the mobility of carriers, a third quantum well layer can be further arranged below the first quantum well layer 110, so that the two buried quantum well layers below can inject carriers for the transport interface of the surface quantum well above, thereby further improving the amount of carriers of the transport interface and improving the mobility of carriers of the MOS quantum well structure.

[0051] In a possible implementation, the metal-oxide-semiconductor quantum well structure can further include a passivation layer between the second quantum well layer 105 and the gate oxide layer 108.

[0052] In order to improve the interface quality between the gate oxide layer 108 and the second quantum well layer 105, a passivation layer can be arranged between the two, for example, a high-valence stable oxide can be formed by passivation methods such as ozone (dry method) or concentrated nitric acid (wet method), as the passivation layer. In this way, the film layer quality of the passivation layer is higher, and the film layer surface is more flat, so that better interface contact between the semiconductor (i.e., the second quantum well layer 105) and the oxide (i.e., the gate oxide layer 108) can be achieved, and the film layer quality is improved.

[0053] In a possible implementation, when the material of the second quantum well layer 105 is germanium, the metal-oxide semiconductor quantum well structure can further include: a first buffer layer 1031 located between the substrate 101 and the first barrier layer 104, the material of the first buffer layer 1031 is Si 1-x Ge x In the direction of the substrate 101 pointing to the first barrier layer 104, the Ge content in the first buffer layer 1031 gradually decreases.

[0054] That is, in the Ge MOS quantum well structure, before the first barrier layer 104 is formed on the substrate 101, the first buffer layer 1031 Si 1-x Ge x , the first buffer layer 1031 Si 1-x Ge x , the Ge content in the first buffer layer 1031 Si 1-x Ge x decreases from bottom to top, which can be considered as a silicon-germanium reverse graded layer (Si 1-x Ge x , the more Si content and the less Ge content of the first barrier layer 104, so that the dislocation between the first buffer layer 1031 and the first barrier layer 104 is small, and the quality of the first barrier layer 104 is less affected by the dislocation, so that a higher-quality first barrier layer 104 can be obtained.

[0055] In a possible implementation, the metal-oxide semiconductor quantum well structure further includes: a germanium layer 102 located between the substrate 101 and the first buffer layer 1031.

[0056] In order to improve the interface quality between the first buffer layer 1031 and the substrate 101, a Ge layer 102 can be formed between the two. Since the Ge content in the lower part of the first buffer layer 1031 is higher, the dislocation between the first buffer layer 1031 and the underlying Ge layer 102 is smaller, the film layer quality of the first buffer layer 1031 is improved, and the overall quality of the heterojunction quantum well is improved.

[0057] In a possible implementation, when the material of the second quantum well layer 105 is silicon, the metal oxide semiconductor quantum well structure can further include: a second buffer layer 1032 between the substrate 101 and the first barrier layer 104, the material of the second buffer layer 1032 being Si 1-x Ge x In the direction in which the substrate 101 points to the first barrier layer 104, the content of Ge in the second buffer layer 1032 gradually increases.

[0058] That is, in the Si MOS quantum well structure, before the first barrier layer 104 is formed, a second buffer layer 1032 can be formed on the substrate 101 by using a precursor, the material of the second buffer layer 1032 being Si 1-x Ge x From bottom to top, the content of Ge in the second buffer layer 1032 gradually increases, that is, in the second buffer layer 1032, the higher the position, the more the content of Ge, so that the dislocation between the first buffer layer 1031 and the first barrier layer 104 above the first buffer layer 1031 is smaller, and at this time, the first buffer layer 1031 can be referred to as a silicon germanium positive gradient layer (Si 1-x Ge x FG), which improves the interface quality of the first buffer layer 1031.

[0059] Reference Figure 3 Fig. 1 shows a flowchart of a method for manufacturing a metal oxide semiconductor quantum well structure provided by an embodiment of the present application, which can include the following steps.

[0060] S101, providing a substrate 101;

[0061] S102, forming, on one side of the substrate 101, a first barrier layer 104, a first quantum well layer 110, a second barrier layer 106, a second quantum well layer 105, a gate oxide layer 108, and a gate metal layer 109 in sequence by a chemical vapor deposition method; the first barrier layer 104 is between the first quantum well layer 110 and the substrate 101, and the first quantum well layer 110 is configured to provide carriers to a transport interface between the second quantum well layer 105 and the gate oxide layer 108; the materials of the first barrier layer 104 and the second barrier layer 106 are both silicon germanium, and the material of the second quantum well layer 105 is silicon or germanium.

[0062] The entire fabrication process of the Ge MOS quantum well structure will be described next. Referring to Figure 4, a schematic diagram of a Ge MOS quantum well structure provided in this embodiment is shown. It is mainly fabricated using chemical vapor deposition (CVD) with germanium-based and silicon-based precursors to form various film layers, as shown in (a) and (b). A germanium layer 102, a first buffer layer 1031, and a first barrier layer 104 are formed on a silicon substrate 101. Specifically, the first buffer layer 1031 is a reverse-gradient Si. 1-x Ge x The first barrier layer 104, also known as the lower constant composition layer, has a fixed silicon and germanium content. As shown in (c), a first quantum well layer 110, such as a Ge quantum well layer, is deposited. As shown in (d), a second barrier layer 106, also known as the upper constant composition layer, is deposited. In these two barrier layers, Si... 1-x Ge x The value of x in this context ranges from 65% to 95%. (Reference) Figure 5 For example, (e) a second quantum well layer 105 is generated, the material being, for example, Ge. For example, (f) a cap layer 107 is grown, the material being, for example, germanium. For example, (g) the product obtained after the cap layer oxidation is removed by HF etching, and a high-valence-state stable oxide is formed by passivation using ozone (dry method) or concentrated nitric acid (wet method) as a passivation layer (not shown). Then, a gate oxide layer 108 (e.g., ALO / HFO) is grown by atomic layer deposition (ALD), and finally a semiconductor-oxide interface with a good surface is formed. Then, metal is evaporated to form a gate metal layer 109, and finally a high-mobility quantum well is formed.

[0063] The entire fabrication process of the Si MOS quantum well structure will be described next. Referring to Figure 6, which is a schematic diagram of a Si MOS quantum well structure provided in an embodiment of this application, the structure is mainly formed by chemical vapor deposition (CVD) using germanium-based and silicon-based precursors, as shown in (a) and (b). A second buffer layer 1032 and a first barrier layer 104 are formed on the silicon substrate 101. The first buffer layer 1031 is specifically a reverse-gradient Si. 1-x Ge x The first barrier layer 104, also known as the lower constant composition layer, has a fixed silicon and germanium content. As shown in (c), the first quantum well layer 110, such as a Si quantum well layer, is deposited. As shown in (d), the second barrier layer 106, also known as the upper constant composition layer, is deposited. In these two barrier layers, Si... 1-x Ge xx is in the range of 10% to 40%. Referring to Figure 7 As (e) continues to generate the second quantum well layer 105, the material is, for example, Si. As (f) continues to grow the cap layer 107, the material is, for example, silicon. As (g), the product obtained after etching the cap layer with HF is removed, and a high-valence stable oxide is formed as a passivation layer (not shown) using passivation methods such as ozone (dry method) or concentrated nitric acid (wet method), and then a gate oxide layer 108 (for example, ALO / HFO, etc.) is grown by atomic layer deposition (ALD), finally forming a good semiconductor-oxide interface, and then a metal is evaporated to form a gate metal layer 109, and finally a high-mobility quantum well is formed.

[0064] In addition, the top view of the MOS quantum well structure can be a rectangle, a square, a rhombus, a circle, etc., and is not limited to one type. Overall, it can be a cuboid, a cylinder, a circular cone, a circular cone, etc., and is not limited to one type, and is not limited herein.

[0065] Each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the difference from other embodiments. In particular, for the method embodiment, since it is basically similar to the device embodiment, it is described more simply, and the related part can be referred to the part of the device embodiment.

[0066] The above only describes the preferred embodiments of the present application. Although the present application has been disclosed as above with the preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solutions disclosed above, or modify equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the content of the technical solutions of the present application, still belongs to the scope of protection of the technical solutions of the present application.

Claims

1. A metal-oxide-semiconductor quantum well structure, characterized in that, The metal-oxide-semiconductor quantum well structure comprises: a substrate, and a first barrier layer, a first quantum well layer, a second barrier layer, a second quantum well layer, a gate oxide layer and a gate metal layer which are sequentially stacked on one side of the substrate; the first barrier layer is between the first quantum well layer and the substrate, and the first quantum well layer is configured to provide carriers to a transport interface between the second quantum well layer and the gate oxide layer. The materials of the first barrier layer and the second barrier layer are both germanium silicon, and the material of the second quantum well layer is silicon or germanium.

2. The metal-oxide-semiconductor quantum well structure of claim 1, wherein In a film layer stacking direction, the thickness of the second barrier layer is greater than or equal to 1 nm and less than or equal to 60 nm.

3. The metal-oxide-semiconductor quantum well structure of claim 1, wherein, The materials of the first quantum well layer and the second quantum well layer are the same.

4. The metal-oxide-semiconductor quantum well structure of claim 1, wherein, When the material of the second quantum well layer is germanium, the material of the first quantum well layer is germanium tin; and when the material of the second quantum well layer is silicon, the material of the first quantum well layer is silicon germanium tin.

5. The metal-oxide-semiconductor quantum well structure of any of claims 1-4, wherein the metal-oxide-semiconductor quantum well structure is a metal-oxide-semiconductor quantum well structure of a metal-oxide-semiconductor field effect transistor (MOSFET). The metal-oxide-semiconductor quantum well structure further comprises: a third barrier layer and a third quantum well layer between the substrate and the first barrier layer, and the third quantum well layer is in contact with the first barrier layer.

6. The metal-oxide-semiconductor quantum well structure of any of claims 1-4, wherein the metal-oxide-semiconductor quantum well structure is a metal-oxide-semiconductor quantum well structure. The metal-oxide-semiconductor quantum well structure further comprises: a passivation layer between the second quantum well layer and the gate oxide layer.

7. The metal-oxide-semiconductor quantum well structure of any of claims 1-4, wherein the metal-oxide-semiconductor quantum well structure is a metal-oxide-semiconductor quantum well structure. When the material of the second quantum well layer is germanium, the metal-oxide-semiconductor quantum well structure further comprises: a first buffer layer between the substrate and the first barrier layer, the first buffer layer being of Si 1- x Ge x a Ge content in the first buffer layer gradually decreases in a direction of the substrate toward the first barrier layer.

8. The metal-oxide-semiconductor quantum well structure of claim 7, wherein, The metal-oxide-semiconductor quantum well structure further comprises: a germanium layer between the substrate and the first buffer layer.

9. The metal-oxide-semiconductor quantum well structure of claim 1, wherein, When the material of the second quantum well layer is silicon, the metal-oxide-semiconductor quantum well structure further comprises: a second buffer layer between the substrate and the first barrier layer, the second buffer layer being of Si 1- x Ge x In the direction of the substrate pointing to the first barrier layer, the Ge content in the second buffer layer gradually increases.

10. A method for fabricating a metal-oxide-semiconductor quantum well structure, characterized in that, The metal-oxide-semiconductor quantum well structure comprises: providing a substrate; forming, on one side of the substrate, a first barrier layer, a first quantum well layer, a second barrier layer, a second quantum well layer, a gate oxide layer and a gate metal layer which are sequentially stacked by a chemical vapor deposition method; the first barrier layer is between the first quantum well layer and the substrate, and the first quantum well layer is configured to provide carriers to a transport interface between the second quantum well layer and the gate oxide layer; The materials of the first barrier layer and the second barrier layer are both germanium silicon, and the material of the second quantum well layer is silicon or germanium.

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