RISC-V soft core development method compatible with Xilinx tool chain
By preprocessing and generating BSPs for RISC-V soft cores in the Vivado and Vitis development environments, the compatibility and flexibility issues of RISC-V soft cores in FPGA development are resolved, achieving an efficient and reliable development process and improving development efficiency and product quality.
Patent Information
- Application Number
- CN202511321562.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-16
- Publication Date
- 2025-12-23
AI Technical Summary
In existing technologies, there are multiple versions of RISC-V soft cores in FPGA development, which leads to high compatibility risks, long development cycles, and many system integration errors. Furthermore, traditional development methods lack flexibility or have high learning costs, making it difficult to meet customized needs.
By preprocessing the RISC-V soft core files in the Vivado development environment to ensure compliance with the XSA standard, and generating a BSP compatible with the Xilinx toolchain in the Vitis development environment, the development process is simplified, allowing direct entry into the application software building stage, avoiding traditional BSP and SDK development.
It improves the development efficiency and product quality of RISC-V soft cores on FPGAs, reduces development errors, and enhances the accuracy and reliability of development. It provides a standardized and efficient development process that is applicable to conventional and third-party RISC-V soft cores that are compatible with the Xilinx toolchain.
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Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of integrated circuit design and development, and particularly relates to a RISC-V soft core development method compatible with Xilinx tool chain. BACKGROUND
[0002] With the rapid development of semiconductor technology, especially the increasing demand for customized chip design, RISC-V, as an open instruction set architecture (ISA), has gradually gained widespread attention in academia and industry. Compared with traditional instruction set architectures such as ARM and x86, RISC-V has flexibility, customizability and open source characteristics, making its application gradually expand in the fields of embedded systems, processor design and high-performance computing.
[0003] In the field of FPGA (Field Programmable Gate Array), using RISC-V architecture-based soft core (hereinafter referred to as RISC-V soft core) for system design not only improves development efficiency, but also reduces development cost and shortens product launch cycle. However, due to the openness of RISC-V architecture, there are multiple versions of RISC-V soft core, and these soft cores may have great differences in implementation details and performance optimization, which leads to a series of challenges in integrating third-party RISC-V soft core into FPGA development process and ensuring its compliance with XSA (Xilinx Software Archive) standards. This not only prolongs the development cycle, but also increases the compatibility risk and the possibility of system integration errors, thereby adversely affecting the development progress, quality and final delivery of the product.
[0004] The traditional development process of RISC-V soft core mainly has the following two solutions: (1) using Xilinx's official Microblaze soft core and relying on Xilinx Vitis development tools. This way has rich IP resources and mature development documents, but since Microblaze is a closed-source commercial product, it lacks flexibility and the function extension is limited (such as unable to perform instruction extension), which makes it difficult to meet the increasingly personalized customization needs of RISC-V soft core. (2) Through self-developed RISC-V soft core, combined with self-developed SDK and Eclipse-based tool chain for development, please refer to Figure 1The flowchart shown includes starting the processing flow by using the Vivado tool, packaging the RISC-V soft core file through the IP Manager, and importing the packaged soft core into the Vivado development environment. Subsequently, the Block Design is designed in Vivado, the system architecture is constructed, and the bitstream file is generated, and finally the bitstream is written to the FPGA chip. Then, the BSP (Board Support Package) and SDK (Software Development Kit) development based on the RISC-V architecture is carried out, and efficient driver programs, initialization code and hardware abstraction layer interfaces are written to provide direct and fast hardware access and control interfaces for the upper software. After completing the BSP and SDK development, a third-party IDE (Integrated Development Environment) is further introduced to fully promote the development and debugging process, and finally the complete landing of the FPGA application based on the third-party RISC-V soft core is realized. This method can realize more flexible customization requirements compared to the first method, but it needs to migrate the existing Microblaze software stack to RISC-V, which brings a lot of additional testing work and greatly increases the learning cost of users, significantly hindering the promotion and application of RISC-V soft core. SUMMARY
[0005] The present application is directed to the above problems and technical needs, and proposes a RISC-V soft core development method compatible with Xilinx tool chain. The technical solution of the present application is as follows:
[0006] A RISC-V soft core development method compatible with Xilinx tool chain, the RISC-V soft core development method comprises:
[0007] Pretreat the RISC-V soft core file in the Vivado development environment according to the Microblaze V soft core specification to obtain a compatibility soft core conforming to the XSA standard;
[0008] Import the compatibility soft core conforming to the XSA standard into the Vivado development environment, and construct a Block Design based on the compatibility soft core according to business requirements to generate an XSA file of the Xilinx platform;
[0009] Import the generated XSA file into the Vitis development environment, and use the Vitis development environment to parse the system hardware information carried by the XSA file and generate a BSP compatible with the Xilinx tool chain of the Xilinx platform;
[0010] With the generated BSP compatible with the Xilinx tool chain as the underlying support, software development is carried out by using the Vitis development environment, and an FPGA application of the RISC-V soft core conforming to the XSA standard is made.
[0011] A further technical solution is to obtain a compatible soft core conforming to the XSA standard, which includes:
[0012] The RISC-V soft core file is packaged to obtain an XML file by using the IP manager of the Vivado development environment under the condition that the bus name is consistent with the Microblaze V soft core specification.
[0013] The XML file obtained after the packaging operation is edited and modified according to the Microblaze V soft core specification to obtain a compatible soft core conforming to the XSA standard.
[0014] A further technical solution is to edit and modify the XML file obtained after the packaging operation according to the Microblaze V soft core specification, which includes:
[0015] The parameter information in the XML file is modified according to the Microblaze V soft core specification, and the BD file under the micorblaze V path is added, and the soft core name definition code is added in the BD file.
[0016] A further technical solution is to modify the parameter information in the XML file according to the Microblaze V soft core specification, which includes:
[0017] The parameter name and the supplier information in the XML file are modified to match the Microblaze V soft core specification.
[0018] A further technical solution is to obtain a compatible soft core conforming to the XSA standard, which includes:
[0019] When the obtained RISC-V soft core file conforms to the XSA standard, the obtained RISC-V soft core file is directly used as a compatible soft core;
[0020] When the obtained RISC-V soft core file does not conform to the XSA standard, the step of preprocessing the RISC-V soft core file in the Vivado development environment according to the Microblaze V soft core specification is performed to obtain a compatible soft core conforming to the XSA standard.
[0021] A further technical solution is that the RISC-V soft core development method further includes:
[0022] The debugging interface of the compatible soft core is connected by using the Xilinx BSCAN IP.
[0023] Further technical solutions are that the Vitis development environment is used to generate the BSP compatible with the Xilinx tool chain, and the BSP compatible with the Xilinx tool chain includes:
[0024] The system hardware information carried in the XSA file is parsed by using the Vitis development environment, and a built-in library file and an optimization module are called to generate the BSP compatible with the Xilinx tool chain according to the system hardware information, and the generated BSP includes a driver program, a hardware abstraction layer interface, system initialization code and related library files.
[0025] Further technical solutions are that the Vitis development environment is used to generate the BSP compatible with the Xilinx tool chain, and the BSP compatible with the Xilinx tool chain includes:
[0026] The Vitis development environment is used for software development, performance optimization and problem troubleshooting by using code editing, compiling, debugging and performance analysis tools, the program developed and debugged in the Vitis development environment is deployed on the FPGA and is debugged through the JTAG interface, and the FPGA application of the RISC-V soft core conforming to the XSA standard is determined after the program debugging.
[0027] The beneficial technical effects of the present application are:
[0028] The present application discloses a RISC-V soft core development method compatible with the Xilinx tool chain, which imports the Vivado to generate a file conforming to the XSA standard after realizing the compatibility of the RISC-V soft core file and the Microblaze V soft core, and the generated XSA file can be reused to automatically generate a soft core BSP in the Vitis development environment for software development, so that the traditional BSP and SDK development can be skipped and the application software construction link can be directly entered, the compatibility with the Xilinx platform is deeply excavated and strengthened, the deployment of the soft core design based on the RISC-V architecture on the Xilinx FPGA is more smooth, and the development efficiency and product quality are significantly improved.
[0029] Whether it is a regular type or a third-party RISC-V soft core compatible with the Xilinx tool chain, the method can provide standardized and rigorous guidance. Through in-depth optimization and meticulous development process, the development errors caused by the chaotic process are effectively reduced, and the accuracy and reliability of the development are fundamentally improved. At the same time, considering that the non-standard and compatibility problems of the development process have become a bottleneck restricting the development of technology, the method constructs a development process system with standardization and high efficiency, thereby systematically solving these problems, and providing a new and effective path for the development of the RISC-V soft core on the FPGA platform. BRIEF DESCRIPTION OF DRAWINGS
[0030] Figure 1is a traditional RISC-V soft core development flowchart.
[0031] Figure 2 is a RISC-V soft core development flowchart of one embodiment of the present application.
[0032] Figure 3 is a method flowchart for obtaining a compatible soft core in accordance with the XSA standard in one embodiment of the present application. DETAILED DESCRIPTION
[0033] The specific embodiments of the present application will be further described below in conjunction with the accompanying drawings.
[0034] The present application discloses a RISC-V soft core development method compatible with Xilinx tool chain, please refer to Figure 2 the flowchart, the RISC-V soft core development method includes the following steps:
[0035] Step 1, in the Vivado development environment, the RISC-V soft core file is pretreated according to the Microblaze V soft core specification, and a compatible soft core in accordance with the XSA standard is obtained.
[0036] First, the developer needs to obtain the RISC-V soft core file from a third party, and then adapt it to the compatibility of the Microblaze V soft core. The Microblaze V soft core is a riscv version of the Microblaze soft core. In this process, the parameters and interfaces of the RISC-V soft core file need to be adjusted to ensure that it can be seamlessly connected to the Microblaze V. This compatibility preprocessing includes the following processes, please refer to Figure 3 the flowchart:
[0037] (1) Use the IP manager of the Vivado development environment to package the RISC-V soft core file to obtain an XML file under the condition that the bus name is consistent with the Microblaze V soft core specification. That is, in the packaging process, a key point is to ensure that the bus name is strictly consistent with the Microblaze V soft core to meet the compatibility requirements.
[0038] (2) After packaging, the obtained XML file is edited and modified according to the Microblaze V soft core specification to obtain a compatible soft core in accordance with the XSA standard. This editing and modification mainly includes the following two aspects:
[0039] The parameter name in the XML file and the supplier information are modified to match the Microblaze V soft core specification. Ensure that the parameter name described in the XML file exactly matches the Microblaze V, which is one of the factors to ensure that the soft core can be correctly identified and configured in the Xilinx platform software tool chain. In addition, the modification is made to make the soft core comply with the supplier information.
[0040] (3) Add the BD file under the Micorblaze V path and add the soft core name definition code in the BD file. The added soft core name definition code must comply with the xilinx specification, and the soft core name can be named according to the user's needs.
[0041] The compatible soft core obtained through the above series of modification operations fully complies with the XSA standard, and can be successfully imported into the Vivado development environment.
[0042] In addition, this method can be applied to both regular and third-party RISC-V soft cores that have been compatible with the Xilinx tool chain, so when the RISC-V soft core file is obtained, first determine whether it meets the XSA standard. When the obtained RISC-V soft core file meets the XSA standard, directly use the obtained RISC-V soft core file as the compatible soft core and enter step 2. When the obtained RISC-V soft core file does not meet the XSA standard, first perform the above preprocessing step to obtain a compatible soft core that meets the XSA standard, and then enter step 2.
[0043] Step 2, import the compatible soft core that meets the XSA standard into the Vivado development environment, and construct a Block Design based on the compatible soft core according to the business needs, ensure that the constructed Block Design can meet the business needs, and after the design is completed, the XSA file of the Xilinx platform can be obtained.
[0044] The obtained XSA file is a hardware description file of the Xilinx platform, which carries the system hardware information, and is the core file to ensure cooperation with the Xilinx tool chain. The system hardware information carried by the XSA file at least includes system hardware architecture, interface definition, resource allocation and configuration parameters.
[0045] In addition, in order to facilitate subsequent debugging work, use Xilinx BSCAN IP to connect the debugging interface of the compatible soft core, which is convenient for subsequent downloading of the soft core to the FPGA, and then downloading the program in vitis to the soft core through JTAG for debugging.
[0046] Step 3: Import the generated XSA file into the Vitis development environment, and use the Vitis development environment to parse the system hardware information carried by the XSA file and generate a BSP compatible with the Xilinx tool chain of the Xilinx platform.
[0047] The Vitis development environment automatically identifies the XSA file and parses the system hardware information carried by the XSA file, then calls the built-in library file and optimization module to generate a BSP compatible with the Xilinx tool chain according to the parsed system hardware information. The generated BSP includes a driver, a hardware abstraction layer interface, system initialization code, and related library files, thereby ensuring that the BSP is highly matched with the hardware and software tool chain of the Xilinx platform, greatly simplifying the software development process.
[0048] Step 4: Use the Vitis development environment to develop software based on the generated BSP compatible with the Xilinx tool chain, and produce an FPGA application of the RISC-V soft core that meets the XSA standard.
[0049] The Vitis development environment, as a professional development platform released by Xilinx, provides comprehensive support for projects that meet the XSA standard. Therefore, further development and debugging can be performed with the help of the Vitis development environment, including software development, performance optimization, and problem troubleshooting using the code editing, compilation, debugging, and performance analysis tools of the Vitis development environment, and completing debugging in the Vitis development environment, thereby improving development efficiency and shortening product development cycle.
[0050] Further, to ensure that the RISC-V soft core based on the XSA standard can run stably on the Xilinx platform, step 2 generates a corresponding bitstream in addition to the XSA file after constructing the Block Design based on the compatible soft core. Then, the program developed and debugged in the Vitis development environment is deployed to the FPGA and debugged through the JTAG interface. After the program debugging is completed, it is determined that the FPGA application of the RISC-V soft core that meets the XSA standard is produced, thereby presenting the system functions based on the third-party RISC-V soft core that meets the XSA standard in its entirety, meeting the application requirements under the business scenario, and achieving the expected high-performance system target and application effect.
[0051] The above-described is only a preferred embodiment of the present application, and the present application is not limited to the above embodiments. It can be understood that other improvements and changes directly derived or thought of by those skilled in the art without departing from the spirit and concept of the present application should be considered within the scope of protection of the present application.
Claims
1. A RISC-V soft core development method compatible with the Xilinx toolchain, characterized in that, The RISC-V soft core development method includes: In the Vivado development environment, the RISC-V soft core file is preprocessed according to the Microblaze V soft core specification to obtain a compatible soft core that conforms to the XSA standard; Import the XSA-compliant soft kernel into the Vivado development environment, and build a Block Design based on the compatible soft kernel according to business needs to generate the XSA file for the Xilinx platform; Import the generated XSA file into the Vitis development environment, use the Vitis development environment to parse the system hardware information carried in the XSA file, and generate a BSP compatible with the Xilinx toolchain of the Xilinx platform. Using the generated Xilinx-compatible BSP as the underlying support, and the Vitis development environment for software development, an FPGA application with a RISC-V soft core conforming to the XSA standard is created.
2. The RISC-V soft core development method according to claim 1, characterized in that, Obtaining XSA-compliant compatible soft cores includes: Using the IP manager of the Vivado development environment, the RISC-V soft core files are packaged to obtain XML files, while ensuring that the bus name is consistent with the Microblaze V soft core specification. The XML file obtained after packaging is edited and modified according to the Microblaze V soft core specification to obtain a compatible soft core that conforms to the XSA standard.
3. The RISC-V soft core development method according to claim 2, characterized in that, Editing and modifying the XML file obtained after packaging according to the Microblaze V soft core specification includes: Modify the parameter information in the XML file according to the Microblaze V soft core specification, add the BD file under the microblaze V path, and add the soft core name definition code in the BD file.
4. The RISC-V soft core development method according to claim 3, characterized in that, Modifying the parameter information in the XML file according to the Microblaze V soft core specification includes: Modify the parameter names and supplier information in the XML file to match the Microblaze V soft core specification.
5. The RISC-V soft core development method according to claim 1, characterized in that, Obtaining XSA-compliant compatible soft cores includes: When the obtained RISC-V soft core file conforms to the XSA standard, the obtained RISC-V soft core file is directly used as a compatible soft core; When the obtained RISC-V soft core file does not conform to the XSA standard, the steps of preprocessing the RISC-V soft core file according to the Microblaze V soft core specification are performed in the Vivado development environment to obtain a compatible soft core that conforms to the XSA standard.
6. The RISC-V soft core development method according to claim 1, characterized in that, The RISC-V soft core development method also includes: Use the Xilinx BSCAN IP connection for a compatible soft core's debug interface.
7. The RISC-V soft core development method according to claim 1, characterized in that, Generating a BSP compatible with the Xilinx toolchain using the Vitis development environment includes: The system hardware information carried in the XSA file is obtained by parsing using the Vitis development environment. The built-in library files and optimization modules are then called to generate a BSP compatible with the Xilinx toolchain based on the system hardware information. The generated BSP includes drivers, hardware abstraction layer interfaces, system initialization code, and related library files.
8. The RISC-V soft core development method according to claim 1, characterized in that, Software development using the Vitis development environment includes: Software development, performance optimization, and troubleshooting are carried out using the code editing, compilation, debugging, and performance analysis tools of the Vitis development environment. The developed program, which has been debugged in the Vitis development environment, is deployed to the FPGA and debugged through the JTAG interface. After the program is successfully debugged, the FPGA application of the RISC-V soft core conforming to the XSA standard is confirmed.