Memory element and method of forming memory element

Abstract

A memory device includes a substrate, a capacitor structure, a support layer, and a conductive structure. The capacitor structure is over the substrate. The capacitor structure comprises a lower electrode, a capacitor dielectric layer and an upper electrode. The capacitor dielectric layer is over the lower electrode. The upper electrode is over the capacitor dielectric layer. The support layer is over the substrate and is in contact with an outer surface of the lower electrode of the capacitor structure. The conductive structure contacts the capacitor structure. The conductive structure includes a first epitaxial layer, a second epitaxial layer and a third epitaxial layer. The first epitaxial layer is arranged above the upper electrode. The second epitaxial layer is over the first epitaxial layer. The third epitaxial layer is over the second epitaxial layer. The conductive structure of the memory element may have a lower total resistance while minimizing discontinuity at the interface and improving the electron flow path.

Description

Technical Field

[0001] This invention relates to a memory element and a method for forming a memory element. Background Technology

[0002] Memory cells in dynamic random access memory (DRAM) are constantly shrinking to integrate more memory cells within a unit area. However, this shrinking process can cause some problems during the formation of memory cells.

[0003] For example, to achieve low resistance, the germanium doping concentration of the conductive structure (often referred to as the capacitor silicon anchor layer) located on the capacitor structure in the memory cell is increased. However, this leads to an increase in the grain size of the conductive structure. As the critical dimension of the memory cell shrinks, the increased grain size causes breakpoints at the interface between the conductive and capacitor structures, reducing the electron flow path and making the capacitance unmeasurable.

[0004] Therefore, how to propose a memory element that can solve the above problems and a method for forming the memory element is one of the problems that the industry is currently eager to invest research and development resources to solve. Summary of the Invention

[0005] In view of this, one object of the present invention is to provide a memory element that can solve the above-mentioned problems and a method for forming the memory element.

[0006] One aspect of the present invention relates to a memory element comprising a substrate, a capacitor structure, a support layer, and a conductive structure. The capacitor structure is located above the substrate. The capacitor structure includes a lower electrode, a capacitor dielectric layer, and an upper electrode. The capacitor dielectric layer is located above the lower electrode. The upper electrode is located above the capacitor dielectric layer. The support layer is located above the substrate and contacts the outer surface of the lower electrode of the capacitor structure. The conductive structure is in contact with the capacitor structure. The conductive structure includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer. The first epitaxial layer is located above the upper electrode. The second epitaxial layer is located above the first epitaxial layer. The third epitaxial layer is located above the second epitaxial layer.

[0007] In some embodiments, the germanium concentration of the second epitaxial layer is higher than that of the first epitaxial layer and the third epitaxial layer.

[0008] In some embodiments, the grain size of the second epitaxial layer is larger than the grain size of the first epitaxial layer and the grain size of the third epitaxial layer.

[0009] In some embodiments, the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer comprise a silicon-containing material doped with at least one of germanium and boron.

[0010] In some embodiments, the first epitaxial layer comprises silicon. The second epitaxial layer comprises boron-doped silicon germanium.

[0011] In some embodiments, the lower electrode has a U-shaped profile. The capacitor dielectric layer, the upper electrode, and the first epitaxial layer extend between the two vertical portions of the lower electrode.

[0012] In some embodiments, the lower electrode has a rectangular cross-section. The capacitor dielectric layer has a bottom surface that spans the support layer and over the lower electrode.

[0013] In some embodiments, the conductive structure further includes a fourth epitaxial layer located between the upper electrode and the first epitaxial layer.

[0014] In some implementations, the fourth epitaxial layer comprises polycrystalline silicon.

[0015] In some implementations, the grain size of the fourth epitaxial layer is smaller than that of the first epitaxial layer.

[0016] Another aspect of the present invention relates to a method of forming a memory element, comprising forming a stack over a substrate. The stack includes a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer, and a third support layer. The method further includes forming a trench in the stack. The method further includes forming a capacitor structure in the trench. Forming the capacitor structure includes: forming a lower electrode in the trench; removing the first and second sacrificial layers from the stack; forming a capacitor dielectric layer over the lower electrode; and forming an upper electrode over the capacitor dielectric layer. The method further includes forming a conductive structure in contact with the capacitor structure. Forming the conductive structure includes: forming a first epitaxial layer over the upper electrode; forming a second epitaxial layer over the first epitaxial layer; and forming a third epitaxial layer over the second epitaxial layer.

[0017] In some embodiments, the germanium concentration of the second epitaxial layer is higher than that of the first epitaxial layer and the third epitaxial layer.

[0018] In some embodiments, the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer comprise a silicon-containing material doped with at least one of germanium and boron.

[0019] In some embodiments, the first epitaxial layer comprises silicon. The second epitaxial layer comprises boron-doped silicon germanium.

[0020] In some embodiments, the upper electrode and the first epitaxial layer are formed in the same chamber.

[0021] In some embodiments, a lower electrode is formed such that it liner the trench. A capacitor dielectric layer is formed such that it liner the lower electrode. An upper electrode is formed such that it liner the capacitor dielectric layer. A first epitaxial layer is formed such that it overfills the trench and extends above the top surface of the third support layer.

[0022] In some embodiments, a lower electrode is formed such that the lower electrode fills the trench. A capacitor dielectric layer is formed such that the capacitor dielectric layer has a bottom surface that spans the third support layer and over the lower electrode.

[0023] In some embodiments, forming a conductive structure further includes forming a fourth epitaxial layer in contact with the upper electrode before forming the first epitaxial layer.

[0024] In some implementations, the upper electrode and the fourth epitaxial layer are formed in the same chamber.

[0025] In some implementations, the germanium concentration of the fourth epitaxial layer is lower than that of the first epitaxial layer.

[0026] In summary, in some embodiments of the memory element and the method of forming the memory element of the present invention, the conductive structure above the capacitor structure includes multiple conductive layers, each with a different germanium doping concentration. This variation allows for adjustment of the grain size of the different conductive layers of the conductive structure, thereby optimizing its electrical and mechanical properties. Specifically, the conductive structure includes at least three conductive layers. The first conductive layer has a lower germanium doping concentration to ensure a smaller grain size and better gap-filling capability at the interface with the underlying capacitor structure. The second conductive layer formed above the first conductive layer has the highest germanium doping concentration to reduce the total resistance of the conductive structure. The third conductive layer formed above the second conductive layer has a lower germanium doping concentration, thus having a smaller grain size, thereby increasing the conductive area and providing a stable foundation for the connection of subsequent structures. In this way, the conductive structure of the formed memory element can have a lower total resistance while minimizing discontinuities at the interface and improving the electron flow pathway.

[0027] These and other aspects of the invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, but variations and modifications may be made therein without departing from the spirit and scope of the novel concept of the invention. Attached Figure Description

[0028] The accompanying drawings illustrate one or more embodiments of the invention and, together with the written description, serve to explain the principles of the invention. Throughout the drawings, the same reference numerals are used wherever possible to refer to similar or identical elements of the embodiments, wherein: Figure 1 This is a circuit diagram of a memory cell of a memory element according to an embodiment of the present invention.

[0029] Figure 2A This is a top view of an intermediate stage of a method for forming a memory element according to an embodiment of the present invention.

[0030] Figure 2B As an intermediate stage of the method for forming a memory element according to an embodiment of the present invention, along Figure 2A The line segment BB represents a partial cross-sectional view.

[0031] Figure 3A This is a top view of an intermediate stage of a method for forming a memory element according to an embodiment of the present invention.

[0032] Figure 3B As an intermediate stage of the method for forming a memory element according to an embodiment of the present invention, along Figure 3A The line segment BB represents a partial cross-sectional view.

[0033] Figure 4 This is a partial cross-sectional view of an intermediate stage of a method for forming a memory element according to an embodiment of the present invention.

[0034] Figure 5A This is a top view of an intermediate stage of a method for forming a memory element according to an embodiment of the present invention.

[0035] Figure 5B As an intermediate stage of the method for forming a memory element according to an embodiment of the present invention, along Figure 5A The line segment BB represents a partial cross-sectional view.

[0036] Figure 6A This is a top view of an intermediate stage of a method for forming a memory element according to an embodiment of the present invention.

[0037] Figure 6B As an intermediate stage of the method for forming a memory element according to an embodiment of the present invention, along Figure 6A The line segment BB represents a partial cross-sectional view.

[0038] Figure 7 and Figure 8 This is a partial cross-sectional view of an intermediate stage of a method for forming a memory element according to an embodiment of the present invention.

[0039] Figure 9A This is a partial cross-sectional view of an intermediate stage of a method for forming a memory element according to an embodiment of the present invention.

[0040] Figure 9BAs an intermediate stage of the method for forming a memory element according to an embodiment of the present invention, along Figure 9A The line segment CC represents a partial cross-sectional view.

[0041] Figure 10A This is a partial cross-sectional view of an intermediate stage of a method for forming a memory element according to an embodiment of the present invention.

[0042] Figure 10B As an intermediate stage of the method for forming a memory element according to an embodiment of the present invention, along Figure 10A The line segment CC represents a partial cross-sectional view.

[0043] Figure 11 This is a partial cross-sectional view of an intermediate stage of a method for forming a memory element according to another embodiment of the present invention.

[0044] Figure 12A This is a top view of an intermediate stage of a method for forming a memory element according to another embodiment of the present invention.

[0045] Figure 12B An intermediate stage of the method for forming a memory element according to another embodiment of the present invention along Figure 12A The line segment BB represents a partial cross-sectional view.

[0046] Figure 13A This is a top view of an intermediate stage of a method for forming a memory element according to another embodiment of the present invention.

[0047] Figure 13B An intermediate stage of the method for forming a memory element according to another embodiment of the present invention along Figure 13A The line segment BB represents a partial cross-sectional view.

[0048] Figure 14 and Figure 15 This is a partial cross-sectional view of an intermediate stage of a method for forming a memory element according to another embodiment of the present invention.

[0049] Figure 16A This is a partial cross-sectional view of an intermediate stage of a method for forming a memory element according to another embodiment of the present invention.

[0050] Figure 16B An intermediate stage of the method for forming a memory element according to another embodiment of the present invention along Figure 16A The line segment CC represents a partial cross-sectional view.

[0051] Figure 17A This is a partial cross-sectional view of an intermediate stage of a method for forming a memory element according to another embodiment of the present invention.

[0052] Figure 17B An intermediate stage of the method for forming a memory element according to another embodiment of the present invention along Figure 17A The line segment CC represents a partial cross-sectional view. Detailed Implementation

[0053] The following disclosure will be described more fully with reference to the accompanying drawings and references, some of which illustrate exemplary embodiments. The invention may be embodied in different forms and should not be limited to the embodiments mentioned below. However, these embodiments are provided to aid in a more complete understanding of the invention and to fully convey its scope to those skilled in the art. The same reference numerals will refer to similar elements throughout the text.

[0054] Figure 1 A circuit diagram illustrating a memory cell of a memory element 100 according to an embodiment of the present invention is shown. In some embodiments, the memory element 100 is a dynamic random access memory (DRAM) element. The memory element 100 includes a transistor 100T, a capacitor 100C, a word line WL, and a bit line BL. The transistor 100T is electrically connected to the word line WL and also electrically connected to the bit line BL, which is perpendicular to the word line WL. One side of the capacitor 100C is electrically connected to the transistor 100T, while the other side of the capacitor 100C is grounded. The operation of the element can be realized using the word line WL and the bit line BL, and data can be stored by controlling the charge in the capacitor 100C. Charge transfer on the capacitor 100C can be determined by controlling the transistor 100T. The transistor 100T can be manipulated by the bit line BL and the word line WL to characterize the reading and writing of signals.

[0055] Figures 2A to 9B This illustrates the formation according to an embodiment of the present invention. Figure 1 The various intermediate stages of the method for the memory element 100 shown. Although Figures 2A to 9B The description is a series of actions, but it should be understood that these actions are not limited thereto; the order of the actions may be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions described and / or illustrated may be omitted, in whole or in part.

[0056] Please refer to Figure 2A and Figure 2B . Figure 2A A top view of an intermediate stage of the method for forming memory element 100. Figure 2B For along Figure 2A The line segment BB represents a partial cross-sectional view.

[0057] The figure shows substrate 110. In some embodiments, substrate 110 can be a suitable semiconductor material, such as silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), germanium (Ge), indium antimonide (InSb), indium phosphide (InP), indium arsenide (InAs), or the like. Substrate 110 may also be doped with suitable dopants. In some embodiments, a gate structure can be formed in substrate 110 (in... Figure 2A and Figure 2B (Not shown in the diagram). The gate structure may include a gate dielectric layer, a gate electrode, and a gate cap. The substrate 110 may include doped regions located on opposite sides of the gate structure. The gate structure, the doped regions, and portions of the substrate 110 along the surface of the gate structure (e.g., channel regions) may together form a structure as shown in the diagram. Figure 1 The memory element 100 shown is a transistor 100T. In some embodiments, the doped region can serve as the source / drain region of the transistor 100T.

[0058] The dielectric layer 112 may be formed over or within the substrate 110. In some embodiments, the dielectric layer 112 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or the like. In some embodiments, the dielectric layer 112 may be formed by, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable methods. The dielectric layer 112 may also be referred to as an interlayer dielectric (ILD).

[0059] Contact plugs 114 may be formed in dielectric layer 112. In some embodiments, contact plugs 114 may be formed to electrically connect to the aforementioned doped regions of substrate 110. In some embodiments, contact plugs 114 may comprise doped polysilicon (doped poly-Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), copper (Cu), aluminum (Al), or alloys thereof. In some embodiments, contact plugs 114 may be formed by, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable methods.

[0060] A stack comprising a support layer 122, a sacrificial layer 130, a support layer 124, a sacrificial layer 138, and a support layer 126 is formed over a substrate 110. The support layer 122 is formed over the dielectric layer 112 and the contact plug 114. The sacrificial layer 130 is formed over the support layer 122. The support layer 124 is formed over the sacrificial layer 130. The sacrificial layer 138 is formed over the support layer 124. The support layer 126 is formed over the sacrificial layer 138.

[0061] The material of the support layer can be different from the material of the sacrificial layer. Specifically, support layers 122, 124, and 126 can be made of materials exhibiting different etching properties than sacrificial layers 130 and 138. Similarly, the material of sacrificial layer 130 can be different from the material of sacrificial layer 138. For example, support layers 122, 124, and 126 comprise silicon nitride. Sacrificial layer 130 comprises borophosphosilicate glass (BPSG). Sacrificial layer 138 comprises oxides such as silicon oxide. In some embodiments, support layers 122, 130, 124, 138, and 126 can be deposited using, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable methods.

[0062] In embodiments where the sacrificial layer 130 comprises borosilicate glass (BPSG), dopants such as boron (B), phosphorus (P), or combinations thereof are doped into the sacrificial layer 130. The dopants can weaken the silicate bonds in the sacrificial layer 130. Therefore, by adjusting the doping concentration, the sacrificial layer 130 can have more desirable etching characteristics in subsequent etching processes. Specifically, the sacrificial layer 130 may include multiple sub-layers vertically stacked between the support layer 122 and the support layer 124. For example, such as... Figure 2B As shown, sublayers 132, 134, and 136 are sequentially stacked on top of support layer 122. The doping concentration of sublayer 132 is higher than that of sublayer 134. Therefore, the silicon oxide bonding in sublayer 132 is weakened more than in sublayer 134, making sublayer 132 more susceptible to etching than sublayer 134. Similarly, the doping concentration of sublayer 134 is higher than that of sublayer 136. Therefore, the silicon oxide bonding in sublayer 134 is weakened more than in sublayer 136, making sublayer 134 more susceptible to etching than sublayer 136.

[0063] Please refer to Figure 3A and Figure 3B . Figure 3A A top view of an intermediate stage of the method for forming memory element 100. Figure 3B For along Figure 3A The line segment BB represents a partial cross-sectional view.

[0064] Using a suitable photolithography process, a plurality of trenches T are formed in a stack including support layer 122, sacrificial layer 130, support layer 124, sacrificial layer 138, and support layer 126. In some embodiments, the trenches T may be formed using an anisotropic dry etching process. After the trenches T are formed, the top surface of the contact plug 114 is exposed.

[0065] Please refer to Figure 4 This is a partial cross-sectional view of an intermediate stage in the method of forming memory element 100.

[0066] After the trench T is formed, a conductive material 140A is formed and lining the top surface of the trench T and the support layer 126. Furthermore, the formed conductive material 140A contacts the top surface of the contact plug 114. In some embodiments, the conductive material 140A comprises a titanium-based material, such as titanium silicon nitride (TiSiN) or titanium nitride (TiN). In other embodiments, the conductive material 140A comprises platinum (Pt).

[0067] Please refer to Figure 5A and Figure 5B. Figure 5A A top view of an intermediate stage of the method for forming memory element 100. Figure 5B For along Figure 5A The line segment BB represents a partial cross-sectional view.

[0068] A planarization process, such as chemical mechanical planarization (CMP), is performed to flush the conductive material 140A with the top surface of the support layer 126. Specifically, multiple portions of the conductive material 140A above the support layer 126 are removed to expose the top surface of the support layer 126. The remaining portions of the conductive material 140A are designated as lower electrodes 140. Thus, lower electrodes 140 are formed in trenches T and contact corresponding contact plugs 114. Therefore, lower electrodes 140 can be electrically connected to doped regions in the substrate 110. Lower electrodes 140 contact the sidewalls of the support layer 122, sacrificial layer 130, support layer 124, sacrificial layer 138, and support layer 126. Figure 5B In the cross-section, each lower electrode 140 has a U-shaped cross-section.

[0069] Please refer to Figure 6A and Figure 6B . Figure 6A A top view of an intermediate stage of the method for forming memory element 100. Figure 6B For along Figure 6A The line segment BB represents a partial cross-sectional view.

[0070] After the lower electrode 140 is formed, an etching process is performed to remove multiple portions of the support layer 122, sacrificial layer 130, support layer 124, sacrificial layer 138, and support layer 126 to form a groove R. For example, as Figure 6A As shown, the groove R is surrounded by four lower electrodes 140 and exposes the dielectric layer 112 above the substrate 110. In some embodiments, the etching process can be performed using a patterned mask. The patterned mask is formed above the support layer 126 and has an opening defining the location of the groove R.

[0071] Next, another etching process, such as wet etching, is performed through the groove R to remove sacrificial layers 130 and 138 from the stack including support layer 122, sacrificial layer 130, support layer 124, sacrificial layer 138, and support layer 126. Therefore, support layers 124 and 126 are suspended above the substrate 110, as... Figure 6B As shown in the diagram. Specifically, the top surfaces of support layers 122, 124, and 126 are exposed, as are the bottom surfaces of support layers 124 and 126. Furthermore, the outer surface of the U-shaped lower electrode 140 is partially exposed.

[0072] Next, please refer to Figure 7 and Figure 8 This is a partial cross-sectional view of an intermediate stage in the method of forming memory element 100.

[0073] like Figure 7 As shown, a capacitor dielectric layer 150 is formed above the lower electrode 140. Specifically, the capacitor dielectric layer 150 is formed lining the support layers 122, 124, 126, and the exposed surfaces of the lower electrode 140. For example, the capacitor dielectric layer 150 is formed above the top surfaces of the support layers 122, 124, and 126. The capacitor dielectric layer 150 is also formed above the bottom surfaces of the support layers 124 and 126. The capacitor dielectric layer 150 is also formed above the exposed outer and inner surfaces of the U-shaped lower electrode 140. In some embodiments, the capacitor dielectric layer 150 may be made of zirconium oxide (ZrO), hafnium oxide (HfO), aluminum oxide (Al2O3), silicon oxide, or the like.

[0074] like Figure 8 As shown, an upper electrode 160 is formed above and liner the capacitor dielectric layer 150. In some embodiments, the upper electrode 160 may be made of the same material as the lower electrode 140. For example, the upper electrode 160 may include titanium silicon nitride (TiSiN), titanium nitride (TiN), or platinum (Pt). In this way, the lower electrode 140, the capacitor dielectric layer 150, and the upper electrode 160 together constitute a capacitor structure. In some embodiments, such as Figure 8 As shown, after the upper electrode 160 is formed, the trench T is not yet fully filled.

[0075] Please refer to Figure 9A and Figure 9B . Figure 9A A partial cross-sectional view of an intermediate stage of a method for forming memory element 100. Figure 9B For along Figure 9A The line segment CC represents a partial cross-sectional view.

[0076] like Figure 9A As shown, a conductive structure 170 is formed in contact with the capacitor structure. For example, the conductive structure 170 includes a conductive layer 172, a conductive layer 174, and a conductive layer 176. The conductive layer 172 may be formed above and in contact with the upper electrode 160. In some embodiments, such as... Figure 9A and Figure 9BAs shown, conductive layer 172 overfills trench T and extends above the top surface of upper electrode 160. Furthermore, conductive layer 172 extends above the top surface of support layer 126. Conductive layer 174 may be formed above conductive layer 172. Conductive layer 176 may be formed above conductive layer 174.

[0077] In some embodiments, conductive layers 172, 174, and 176 comprise silicon-containing materials doped with at least one of germanium and boron, such as boron-doped silicon germanium (SiGe:B), boron-doped silicon (Si:B), or the like. In other embodiments, conductive layers 172 and / or 176 may be made of polysilicon, while conductive layer 174 may be made of boron-doped silicon germanium (SiGe:B). In these embodiments, the polysilicon-containing conductive layer 172 may be formed in the same chamber as the upper electrode 160 comprising titanium silicon nitride (TiSiN) or titanium nitride (TiN). In some embodiments, conductive layers 172, 174, and 176 may also be referred to as epitaxial layers. The conductive structure 170 is commonly referred to as a cellpoly.

[0078] Applying dopants such as germanium helps reduce the total resistance of the conductive structure 170. However, materials with higher germanium concentrations have larger grain sizes. Larger grain sizes create voids and gaps within the material, which negatively impacts its gap-filling ability and reduces its effective conductive area. Therefore, the conductivity of the conductive structure 170 is affected. This affects the performance and reliability of the formed memory element 100. To address this issue, in some embodiments of the invention, the germanium concentration of conductive layer 174 is higher than that of conductive layer 172 and conductive layer 176, resulting in a lower total resistance for the conductive structure 170. Simultaneously, because conductive layers 172 and 176 have lower germanium concentrations, they have smaller grain sizes compared to conductive layer 174. This allows conductive layer 172 to densely fill the trench T, and conductive layer 176 to provide a larger conductive area for the structure formed above it.

[0079] For example, in some embodiments, conductive layers 172 and 176 are made of boron-doped silicon germanium (SiGe:B) or boron-doped silicon (Si:B) with a germanium concentration of less than 50%, while conductive layer 174 is made of boron-doped silicon germanium (SiGe:B) with a germanium concentration between 50% and 90%. Therefore, the grain size of conductive layer 172 and conductive layer 176 can be less than 150 nanometers, while the grain size of conductive layer 174 can be greater than 150 nanometers.

[0080] In some embodiments, the thickness of conductive layer 172 is between 1 nanometer and 20 nanometers, the thickness of conductive layer 174 is between 100 nanometers and 300 nanometers, and the thickness of conductive layer 176 is between 1 nanometer and 20 nanometers.

[0081] like Figure 9A and Figure 9B As shown, the formed memory element 100 includes a substrate 110, a plurality of support layers located above the substrate 110, a capacitor structure located above the substrate 110, and a conductive structure 170 in contact with the capacitor structure.

[0082] The substrate 110 can be any suitable semiconductor material and can be doped with suitable dopants. As previously mentioned, the gate structure ( Figure 9A and Figure 9B (Not shown) can be formed in the substrate 110. The dielectric layer 112 can be formed above or inside the substrate 110. The contact plug 114 can be formed in the dielectric layer 112 and electrically connected to the doped region of the substrate 110.

[0083] The plurality of support layers located above the substrate 110 include support layer 122, support layer 124, and support layer 126. Support layer 122 is located above dielectric layer 112. Support layer 124 is located above support layer 122. Support layer 126 is located above support layer 124. In some embodiments, support layer 122, support layer 124, and support layer 126 comprise silicon nitride.

[0084] The capacitor structure is located above the substrate 110 and includes a lower electrode 140, a capacitor dielectric layer 150 located above the lower electrode 140, and an upper electrode 160 located above the capacitor dielectric layer 150.

[0085] The lower electrode 140 is disposed above its corresponding contact plug 114 and contacts the top surface of the corresponding contact plug 114 to be electrically connected to the doped region of the substrate 110. The lower electrode 140 has a U-shaped cross-section. The top surface of the lower electrode 140 is flush with the top surface of the support layer 126. The outer surfaces of the two vertical portions of the U-shaped lower electrode 140 contact the support layers 122, 124, and 126.

[0086] The capacitor dielectric layer 150 is located above and lining the lower electrode 140. Since the lower electrode 140 has a U-shaped profile, the capacitor dielectric layer 150 extends from the top surface of the lower electrode 140 to between the two vertical portions of the U-shaped lower electrode 140. Furthermore, the capacitor dielectric layer 150 is partially located above the top surfaces of the support layers 122, 124, and 126. The capacitor dielectric layer 150 is also located above the bottom surfaces of the support layers 124 and 126. The capacitor dielectric layer 150 also extends along the outer surface of the lower electrode 140.

[0087] The upper electrode 160 is located above and liner the capacitor dielectric layer 150. Similarly, the upper electrode 160 extends between the two vertical portions of the U-shaped lower electrode 140. Furthermore, the upper electrode 160 is partially located above the top surfaces of the support layers 122, 124, and 126. The upper electrode 160 is also located above the bottom surfaces of the support layers 124 and 126. The upper electrode 160 also extends along the outer surface of the lower electrode 140.

[0088] The conductive structure 170 includes a conductive layer 172, a conductive layer 174, and a conductive layer 176. For example... Figure 9A As shown, the conductive layer 172 extends downward from the top surface of the support layer 126 through the support layer 126. Furthermore, the conductive layer 172 extends between the two vertical portions of the U-shaped lower electrode 140 and fills... Figure 8 The remaining space in the structure shown. Conductive layers 174 and 176 are located above conductive layer 172 and the capacitor structure.

[0089] As described above, the germanium concentration of conductive layer 174 is higher than that of conductive layer 172 and conductive layer 176. For example, conductive layer 172 and / or conductive layer 176 can be made of boron-doped silicon germanium (SiGe:B), boron-doped silicon (Si:B), or polycrystalline silicon with a germanium concentration of less than 50%, while conductive layer 174 can be made of boron-doped silicon germanium (SiGe:B) with a germanium concentration between 50% and 90%. In this way, the grain size of conductive layer 172 and the grain size of conductive layer 176 can be smaller than the grain size of conductive layer 174. Therefore, conductive structure 170 has a lower total resistance, good gap-filling capability, and a large conductive area at its top and bottom, providing reliable and efficient electrical connections.

[0090] Please refer to Figure 10A and Figure 10B . Figure 10A A partial cross-sectional view of an intermediate stage of a method for forming memory element 100'. Figure 10B For along Figure 10A The line segment CC represents a partial cross-sectional view.

[0091] like Figure 10A and Figure 10B As shown, in some embodiments, the conductive structure 170 of the memory element 100' further includes a conductive layer 178 located between the upper electrode 160 and the conductive layer 172. The conductive layer 178 contacts the upper electrode 160. The conductive layer 172 is spaced apart from the upper electrode 160 by the conductive layer 178. In some embodiments, the germanium concentration of the conductive layer 178 is lower than that of the conductive layer 172. In some embodiments, the conductive layer 178 is made of polysilicon. The grain size of the conductive layer 178 may be smaller than that of the conductive layer 172, which facilitates a more dense filling of the trench T. Accordingly, the conductive layer 178 is formed prior to the formation of the conductive layer 172. In some embodiments, the conductive layer 178 is formed lining the upper electrode 160. In some embodiments, the conductive layer 178 comprising polysilicon may be formed in the same chamber as the upper electrode 160 comprising titanium silicon nitride (TiSiN) or titanium nitride (TiN). The conductive layer 178 can serve as a seed layer for the subsequent epitaxial growth of the conductive layer 172. In some embodiments, the conductive layer 178 may also be referred to as an epitaxial layer.

[0092] Figures 11 to 16B This illustrates an intermediate stage of a method for forming a memory element 200 according to another embodiment of the present invention.

[0093] Please refer to Figure 11 This is a partial cross-sectional view of an intermediate stage in the method of forming memory element 200. In some embodiments, after forming trench T, a conductive material 140A is formed to overfill trench T and extend above the top surface of support layer 126. The formed conductive material 140A contacts the top surface of contact plug 114. In some embodiments, the conductive material 140A includes titanium silicon nitride (TiSiN), titanium nitride (TiN), or platinum (Pt).

[0094] Please refer to Figure 12A and Figure 12B . Figure 12A A top view of an intermediate stage in the method of forming memory element 200. Figure 12B For along Figure 12A The line segment BB represents a partial cross-sectional view.

[0095] Similar to the method for forming memory element 100, a planarization process such as chemical mechanical planarization (CMP) is performed to flush the conductive material 140A with the top surface of the support layer 126. The remaining portion of the conductive material 140A is designated as the lower electrode 140. Thus, the lower electrode 140 is formed in trenches T and contacts corresponding contact plugs 114. The lower electrode 140 contacts the sidewalls of the support layer 122, sacrificial layer 130, support layer 124, sacrificial layer 138, and support layer 126. Figure 12B In the cross-section, each lower electrode 140 has a rectangular cross-section and forms a solid cylindrical structure. Specifically, each lower electrode 140 forms a solid cylinder without an internal cavity. In this way, the lower electrode 140 can still maintain structural rigidity after the sacrificial layer is removed later.

[0096] Please refer to Figure 13A and Figure 13B . Figure 13A A top view of an intermediate stage in the method of forming memory element 200. Figure 13B For along Figure 13A The line segment BB represents a partial cross-sectional view.

[0097] Similar to the method for forming memory element 100, after forming the lower electrode 140, an etching process is performed to remove multiple portions of the support layer 122, sacrificial layer 130, support layer 124, sacrificial layer 138, and support layer 126 to form a recess R. For example, as Figure 13A As shown, the recess R is surrounded by four lower electrodes 140 and exposes the dielectric layer 112 located above the substrate 110. Next, another etching process, such as wet etching, is performed through the recess R to remove the sacrificial layers 130 and 138 from the stack including the support layer 122, sacrificial layer 130, support layer 124, sacrificial layer 138, and support layer 126. Therefore, the support layers 124 and 126 are suspended above the substrate 110, as... Figure 13B As shown in the diagram. Specifically, the top surfaces of support layers 122, 124, and 126 are exposed, as are the bottom surfaces of support layers 124 and 126. Furthermore, the outer surface of the cylindrical lower electrode 140 is partially exposed.

[0098] Next, please refer to Figure 14 and Figure 15 This shows a partial cross-sectional view of an intermediate stage of the method for forming memory element 200.

[0099] like Figure 14 As shown, a capacitor dielectric layer 150 is formed above the lower electrode 140. Specifically, the capacitor dielectric layer 150 is formed above the top surface of the lower electrode 140 and the top surface of the support layer 126. More specifically, as... Figure 14As shown, the capacitor dielectric layer 150 has a substantially flat bottom surface. The bottom surface of the capacitor dielectric layer 150 spans over the support layer 126 and the lower electrode 140. Furthermore, the capacitor dielectric layer 150 is formed above the top surfaces of the support layers 122 and 124. The capacitor dielectric layer 150 is also formed above the bottom surfaces of the support layers 124 and 126. The capacitor dielectric layer 150 is also formed above the exposed outer surface of the cylindrical lower electrode 140. In some embodiments, the capacitor dielectric layer 150 may be made of zirconium oxide (ZrO), hafnium oxide (HfO), aluminum oxide (Al2O3), silicon oxide, or the like.

[0100] like Figure 15 As shown, an upper electrode 160 is formed above the capacitor dielectric layer 150. Similarly, the upper electrode 160 has a substantially flat bottom surface. The bottom surface of the upper electrode 160 spans the support layer 126 and over the lower electrode 140. In some embodiments, the upper electrode 160 may include titanium silicon nitride (TiSiN), titanium nitride (TiN), or platinum (Pt). The lower electrode 140, the capacitor dielectric layer 150, and the upper electrode 160 together constitute the capacitor structure.

[0101] Please refer to Figure 16A and Figure 16B . Figure 16A A partial cross-sectional view of an intermediate stage of a method for forming a memory element 200. Figure 16B For along Figure 16A The line segment CC represents a partial cross-sectional view.

[0102] like Figure 16A As shown, a conductive structure 170 is formed in contact with the capacitor structure. The conductive structure 170 includes a conductive layer 172, a conductive layer 174, and a conductive layer 176. The conductive layer 172 may be formed above and in contact with the upper electrode 160. Furthermore, the conductive layer 172 spans across the lower electrode 140 and the support layer 126. The conductive layer 174 may be formed above the conductive layer 172. The conductive layer 176 may be formed above the conductive layer 174.

[0103] In some embodiments, conductive layers 172, 174, and 176 comprise silicon-containing materials doped with at least one of germanium and boron. In other embodiments, conductive layers 172 and / or 176 may be made of polycrystalline silicon, while conductive layer 174 may be made of boron-doped silicon-germanium (SiGe:B). In these embodiments, the polycrystalline silicon conductive layer 172 may be formed in the same chamber as the upper electrode 160 comprising titanium silicon nitride (TiSiN) or titanium nitride (TiN). In some embodiments, conductive layers 172, 174, and 176 may also be referred to as epitaxial layers. The conductive structure 170 is generally referred to as a capacitor silicon fixing layer.

[0104] Similarly, the germanium concentrations of conductive layers 172, 174, and 176 are deliberately chosen to reduce the overall resistance of the conductive structure 170 while maintaining the gap-filling capability and effective conductive area of ​​conductive layers 172 and 176. Specifically, the germanium concentrations of conductive layers 172 and 176 are lower than that of conductive layer 174, resulting in smaller grain sizes for conductive layers 172 and 176 compared to conductive layer 174. This provides a larger conductive area for interfacing with capacitor structures and other subsequent structures formed on the conductive structure 170.

[0105] For example, conductive layer 172 and / or conductive layer 176 can be made of boron-doped silicon germanium (SiGe:B), boron-doped silicon (Si:B), or silicon with a germanium concentration of less than 50%, while conductive layer 174 can be made of boron-doped silicon germanium (SiGe:B) with a germanium concentration between 50% and 90%. In this way, the grain size of conductive layer 172 and conductive layer 176 can be less than 150 nanometers, while the grain size of conductive layer 174 can be greater than 150 nanometers.

[0106] In some embodiments, the thickness of conductive layer 172 is between 1 nanometer and 20 nanometers, the thickness of conductive layer 174 is between 100 nanometers and 300 nanometers, and the thickness of conductive layer 176 is between 1 nanometer and 20 nanometers.

[0107] like Figure 16A and Figure 16B As shown, one of the differences between memory element 200 and memory element 100 is that the lower electrode 140 of memory element 200 has a rectangular cross-section. Therefore, the capacitor dielectric layer 150, the upper electrode 160, and the conductive structure 170 form a stack of multiple horizontal layers above the lower electrode 140 and the support layer 126.

[0108] Please refer to Figure 17A and Figure 17B . Figure 17A A partial cross-sectional view of an intermediate stage of a method for forming memory element 200'. Figure 17B For along Figure 17A The line segment CC represents a partial cross-sectional view.

[0109] like Figure 17A and Figure 17BAs shown, in some embodiments, the conductive structure 170 of the memory element 200' further includes a conductive layer 178 located between the upper electrode 160 and the conductive layer 172. The conductive layer 178 contacts the upper electrode 160. The conductive layer 172 is spaced apart from the upper electrode 160 by the conductive layer 178. In some embodiments, the germanium concentration of the conductive layer 178 is lower than that of the conductive layer 172. In some embodiments, the conductive layer 178 is made of polysilicon. The grain size of the conductive layer 178 may be smaller than that of the conductive layer 172, which facilitates a more dense filling of the trench T. Accordingly, the conductive layer 178 is formed prior to the formation of the conductive layer 172. In some embodiments, the conductive layer 178 is formed lining the upper electrode 160. In some embodiments, the conductive layer 178 comprising polysilicon may be formed in the same chamber as the upper electrode 160 comprising titanium silicon nitride (TiSiN) or titanium nitride (TiN). The conductive layer 178 can serve as a seed layer for the epitaxial growth of the subsequently formed conductive layer 172. In some embodiments, the conductive layer 178 may also be referred to as an epitaxial layer.

[0110] From the detailed description of specific embodiments of the present invention above, it is evident that in some embodiments of the memory element and the method of forming the memory element, the conductive structure above the capacitor structure comprises multiple conductive layers, each with a different germanium doping concentration. This variation allows for adjustment of the grain size of different conductive layers in the conductive structure, thereby optimizing its electrical and mechanical properties. Specifically, the conductive structure comprises at least three conductive layers. The first conductive layer has a lower germanium doping concentration to ensure a smaller grain size and better gap-filling capability at the interface with the underlying capacitor structure. The second conductive layer formed above the first conductive layer has the highest germanium doping concentration to reduce the total resistance of the conductive structure. The third conductive layer formed above the second conductive layer has a lower germanium doping concentration, thus having a smaller grain size, thereby increasing the conductive area and providing a stable foundation for the connection of subsequent structures. In this way, the conductive structure of the formed memory element can have a lower total resistance while minimizing discontinuities at the interface and improving electron flow paths.

[0111] The foregoing description is only intended to illustrate and describe exemplary embodiments of the present invention and is not intended to exhaustively describe or limit the precise forms of the invention disclosed herein. The above teachings may be modified or varied.

[0112] The selected and illustrated embodiments are intended to explain the content of the invention and their practical application, thereby inspiring others skilled in the art to utilize the invention and various embodiments, and to make various modifications to suit specific intended uses. Alternative embodiments will be apparent to those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention is determined by the appended claims, and not by the foregoing description and the exemplary embodiments described therein.

[0113] [Symbol Explanation] 100, 100', 200, 200': Memory elements 100C: Capacitor 100T: Transistor 110: Substrate 112: Dielectric layer 114: Contact plug 122, 124, 126: Support layer 130, 138: Sacrificial Layer 132, 134, 136: Sub-layers 140: Lower electrode 140A: Conductive material 150: Capacitor dielectric layer 160: Upper electrode 170: Conductive structure 172, 174, 176, 178: Conductive layers BB, CC: line segments BL: Bitline R: Groove T: Trench WL: Character line.

Claims

1. A memory element characterized by, A capacitor structure is formed over a substrate and includes: a lower electrode; a capacitor dielectric layer over the lower electrode; and an upper electrode over the capacitor dielectric layer. A support layer is formed over the substrate and contacts an outer surface of the lower electrode of the capacitor structure. A conductive structure is formed in contact with the capacitor structure and includes: a first epitaxial layer over the upper electrode; a second epitaxial layer over the first epitaxial layer; and a third epitaxial layer over the second epitaxial layer. The second epitaxial layer has a higher germanium concentration than the first epitaxial layer and the third epitaxial layer. The second epitaxial layer has a larger grain size than the first epitaxial layer and the third epitaxial layer. The first, second, and third epitaxial layers include a silicon-containing material doped with at least one of germanium and boron. The first epitaxial layer includes silicon, and the second epitaxial layer includes boron-doped silicon germanium. The lower electrode has a U-shaped cross-section, and the capacitor dielectric layer, the upper electrode, and the first epitaxial layer extend between two perpendicular portions of the lower electrode.

2. The memory element of claim 1, wherein, The lower electrode has a rectangular cross-section, and the capacitor dielectric layer has a bottom surface spanning over the support layer and the lower electrode.

3. The memory element of claim 1, wherein, The conductive structure further includes a fourth epitaxial layer between the upper electrode and the first epitaxial layer.

4. The memory element of claim 1, wherein, The fourth epitaxial layer includes polysilicon.

5. The memory element of claim 1, wherein, The fourth epitaxial layer has a smaller grain size than the first epitaxial layer.

6. The memory element of claim 1, wherein, A capacitor structure is formed over a substrate and includes:

7. The memory element of claim 1, wherein, a lower electrode; 8. The memory element of claim 1, wherein, a capacitor dielectric layer over the lower electrode; and 9. The memory element of claim 8, wherein, an upper electrode over the capacitor dielectric layer.

10. The memory element of claim 8, wherein, A support layer is formed over the substrate and contacts an outer surface of the lower electrode of the capacitor structure.

11. A method of forming a memory element, comprising: A conductive structure is formed in contact with the capacitor structure and includes: a first epitaxial layer over the upper electrode; a second epitaxial layer over the first epitaxial layer; and a third epitaxial layer over the second epitaxial layer. The second epitaxial layer has a higher germanium concentration than the first epitaxial layer and the third epitaxial layer. The first, second, and third epitaxial layers include a silicon-containing material doped with at least one of germanium and boron. The first epitaxial layer includes silicon, and the second epitaxial layer includes boron-doped silicon germanium. The upper electrode and the first epitaxial layer are formed in the same chamber. wherein: the lower electrode is formed such that the lower electrode lines the trench, the capacitor dielectric layer is formed such that the capacitor dielectric layer lines the lower electrode, the upper electrode is formed such that the upper electrode lines the capacitor dielectric layer, and the first epitaxial layer is formed such that the first epitaxial layer overfills the trench and extends over a top surface of the third support layer. ​ ​ 12. The method of claim 11, wherein, ​ 13. The method of claim 11, wherein, ​ 14. The method of claim 11, wherein, ​ 15. The method of claim 11, wherein, ​ 16. The method of claim 11, wherein, ​ ​ ​ ​ ​ 17. The method of claim 11, wherein, forming the lower electrode such that the lower electrode fills the trench, and forming the capacitor dielectric layer such that the capacitor dielectric layer has a bottom surface across the third support layer and over the lower electrode.

18. The method of claim 11, wherein, forming the conductive structure further includes, prior to forming the first epitaxial layer, forming a fourth epitaxial layer in contact with the upper electrode.

19. The method of claim 18, wherein, the upper electrode and the fourth epitaxial layer are formed in the same chamber.

20. The method of claim 18, wherein, a germanium concentration of the fourth epitaxial layer is lower than a germanium concentration of the first epitaxial layer.

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