Display panel
By introducing dummy electrodes and segmenting semiconductor layers in the transistors of the display panel, the leakage problem under high pixel density was solved, achieving high-quality display in a limited area.
Patent Information
- Application Number
- CN202410785238.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-18
- Publication Date
- 2025-12-23
AI Technical Summary
In high pixel density display panels, how can leakage current be effectively suppressed within a limited transistor size to maintain excellent display quality?
Dummy electrodes are introduced into the transistors of the display panel, the semiconductor layer is divided into two parts, and dummy electrodes are placed between the source and drain. This increases the channel length and improves the impedance through the design of dummy electrodes, thereby reducing leakage current.
It effectively suppressed leakage current, maintained the display quality of the display panel, and ensured sufficient storage capacitance without significantly increasing the transistor area, thus avoiding image quality problems during low-frequency driving.
Smart Images
Figure CN121194516A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a display panel, and more particularly to a display panel with transistors having low leakage current. Background Technology
[0002] In high pixel density (PPI) display panels, the small area of each subpixel limits the size of the transistors. Therefore, one of the objectives of this invention is to effectively suppress leakage current within the limited transistor size, thereby achieving superior display quality. Summary of the Invention
[0003] The technical problem to be solved by the present invention is how to effectively suppress leakage current and enable the display panel to have preferred display quality within the limited size of transistors.
[0004] To address the aforementioned technical problems, the present invention provides a display panel comprising a substrate and a sub-pixel. The sub-pixel is disposed on the substrate, wherein the sub-pixel includes a transistor, and the transistor includes a gate, a semiconductor layer, a drain, a source, and a dummy electrode. The gate is disposed on the substrate. The semiconductor layer is disposed on the gate, wherein the semiconductor layer includes a first portion and a second portion, and the first portion and the second portion are separate. The drain is disposed on and electrically connected to the first portion of the semiconductor layer. The source is disposed on and electrically connected to the second portion of the semiconductor layer. The dummy electrode is disposed on the substrate, wherein in a direction perpendicular to the substrate, the dummy electrode partially overlaps with the first portion and the second portion of the semiconductor layer, respectively. The dummy electrode is disposed between the source and the drain, and is separate from both the source and the drain, and is electrically floating.
[0005] In the display panel of this invention, the transistor of the sub-pixel has a dummy electrode disposed between the source and drain, which increases the channel length of the transistor and thus suppresses leakage current. Furthermore, the design of dividing the semiconductor layer of the transistor into separate first and second parts also reduces leakage current. On the other hand, a portion of the semiconductor layer can be shielded by the dummy electrode, reducing the amount of light received by the semiconductor layer and thus reducing leakage current. Although the transistor further includes a dummy electrode, the area of the transistor is not significantly increased, ensuring sufficient area is reserved in the sub-pixel for the pixel electrode, thereby providing sufficient storage capacitance and preventing image quality from being affected by insufficient capacitance during low-frequency driving. Attached Figure Description
[0006] Figure 1 This is a top view of the sub-pixels of the display panel according to the first embodiment of the present invention.
[0007] Figure 2 This is an enlarged schematic diagram of the transistors in the display panel according to the first embodiment of the present invention.
[0008] Figure 3 This is a cross-sectional schematic diagram of the transistors in the display panel according to the first embodiment of the present invention.
[0009] Figure 4 This is an enlarged schematic diagram of the transistors in the display panel according to the second embodiment of the present invention.
[0010] Explanation of reference numerals in the attached drawings: 10-Display panel; 100-Substrate; 202, 206-Conductive layers; 204-Gate insulating layer; C1, M1-First part; C2, M2-Second part; CH-Semiconductor layer; CL-Common signal line; CO1, CO2-Contact hole; D-Drain; DL-Data line; DM-Dummy electrode; DR1, DR2, DR3-Direction; FE, CE-Electrode; G-Gate; GL-Scan line; M3-Connection part; RE-Reflective electrode; S-Source; SP-Sub-pixel; SW-Transistor; TE-Transparent electrode; W1-First width; W2-Second width; W3-Third width. Detailed Implementation
[0011] To enable those skilled in the art to further understand the present invention, preferred embodiments are described below, and the composition and desired effects of the invention are explained in detail with reference to the accompanying drawings. It should be noted that the drawings are simplified schematic diagrams; therefore, only elements and combinations related to the present invention are shown to provide a clearer description of the basic structure or implementation method of the invention. Actual elements and layouts may be more complex. Furthermore, for ease of explanation, the elements shown in the various drawings are not drawn to scale according to the actual number, shape, and size; the detailed scale can be adjusted according to design requirements.
[0012] The attached diagram shows three directions: DR1, DR2, and DR3. Direction DR3 can be the normal direction or the top-view direction, such as... Figure 3 The direction DR3 can be perpendicular to the upper surface of the substrate. For example... Figure 1 Directions DR1 and DR2 can be horizontal and perpendicular to direction DR3. Directions DR1 and DR2 can be different; for example, direction DR1 can be perpendicular to direction DR2. The following figures can be used to describe the spatial relationships of the structure based on directions DR1, DR2, and DR3.
[0013] Please refer to Figures 1 to 3 , Figure 1 This is a top view schematic diagram of the sub-pixels of the display panel according to the first embodiment of the present invention. Figure 2 This is an enlarged schematic diagram of the transistors in the display panel according to the first embodiment of the present invention. Figure 3 This is a cross-sectional schematic diagram of the transistors in the display panel according to the first embodiment of the present invention. The display panel in this embodiment is an example of a reflective type or a transflective type display panel, but the present invention is not limited thereto. Figure 1 As shown, the display panel 10 includes a substrate 100, a scan line GL, and a data line DL. The substrate 100 may include a rigid substrate such as a glass substrate, a plastic substrate, a quartz substrate, or a sapphire substrate, but is not limited thereto. The substrate 100 may also include a flexible substrate such as a polyimide (PI) substrate or a polyethylene terephthalate (PET) substrate, but is not limited thereto.
[0014] Scan lines GL and data lines DL are disposed on substrate 100. Scan lines GL extend along direction DR1, and data lines DL extend along direction DR2. A sub-pixel SP is disposed on substrate 100 and may correspond to scan lines GL and data lines DL. Furthermore, display panel 10 may include a plurality of scan lines GL and a plurality of data lines DL, and the scan lines GL and data lines DL may intersect to form multiple sub-pixels SP.
[0015] Subpixel SP includes a transistor SW, and the transistor SW is disposed on substrate 100. The transistor SW may be, for example, a bottom-gate thin film transistor, but is not limited thereto. The design concept of the present invention also applies to top-gate thin film transistors. Furthermore, the transistor SW may be a low-temperature poly-silicon (LTPS) thin film transistor, an indium gallium zinc oxide (IGZO) thin film transistor, or an amorphous silicon (a-Si) thin film transistor, but is not limited thereto.
[0016] The transistor SW includes a gate G, a source S, a drain D, a semiconductor layer CH, and a gate insulating layer 204. The scan line GL is electrically connected to the gate G of the transistor SW, and can provide a switching signal to the gate G of the transistor SW via the scan line GL to control the switching of the transistor SW, thereby controlling the update of the display screen. The data line DL is electrically connected to the source S of the transistor SW, and can provide the grayscale signal of the display screen to the source S of the transistor SW via the data line DL.
[0017] like Figure 3A gate G is disposed on the substrate 100, a semiconductor layer CH is disposed on the gate G, and a gate insulating layer 204 is disposed between the gate G and the semiconductor layer CH. The semiconductor layer CH includes a first portion C1 and a second portion C2, and the first portion C1 and the second portion C2 are separate. The design of dividing the semiconductor layer CH into a separate first portion C1 and a second portion C2 can reduce the leakage current of the transistor SW, thereby enabling the display panel to have preferred display quality.
[0018] The source (S) and drain (D) are disposed on the semiconductor layer CH, and as follows: Figure 2 and Figure 3 As shown, the drain D is disposed on the first part C1 of the semiconductor layer CH and is electrically connected to the first part C1 of the semiconductor layer CH, while the source S is disposed on the second part C2 of the semiconductor layer CH and is electrically connected to the second part C2 of the semiconductor layer CH.
[0019] In addition, such as Figure 2 As shown, the area of the gate G is larger than the area of the first part C1 and the second part C2 of the semiconductor layer CH. The semiconductor layer CH can be completely blocked from below by the gate G. Therefore, the light from below can be blocked by the gate G, thereby reducing the amount of light received by the lower surface of the semiconductor layer CH and the leakage current generated.
[0020] The transistor SW also includes a dummy electrode DM disposed on the substrate 100, such as Figure 2 and Figure 3 As shown, in the direction DR3 perpendicular to the substrate 100, the dummy electrode DM partially overlaps with the first portion C1 and the second portion C2 of the semiconductor layer CH, and the dummy electrode DM is electrically connected to the first portion C1 and the second portion C2 of the semiconductor layer CH. The dummy electrode DM is disposed between the source S and the drain D, and the dummy electrode DM is separate from the source S and the drain D. In addition, the dummy electrode DM is electrically floating. For example, when the transistor SW is turned on, electrons can be transported from the source S through the second portion C2 of the semiconductor layer CH, the dummy electrode DM, and the first portion C1 of the semiconductor layer CH to the drain D.
[0021] The dummy electrode DM includes a first portion M1, a second portion M2, and a connecting portion M3. The first portion M1 of the dummy electrode DM is located at one end of the dummy electrode DM and is disposed near the drain electrode D, and is electrically connected to the first portion C1 of the semiconductor layer CH. The first portion M1 of the dummy electrode DM is disposed on one end of the first portion C1 of the semiconductor layer CH, and a portion of the first portion C1 of the semiconductor layer CH is covered by the first portion M1 of the dummy electrode DM. This reduces the exposed area of the upper surface of the first portion C1 of the semiconductor layer CH and reduces leakage current generated due to light reception on the upper surface of the first portion C1 of the semiconductor layer CH. The drain electrode D is disposed at the other end of the first portion C1 of the semiconductor layer CH, and the remaining portion of the first portion C1 of the semiconductor layer CH is covered by the drain electrode D.
[0022] The second portion M2 of the dummy electrode DM is located at the other end of the dummy electrode DM and is positioned close to the source electrode S. The second portion M2 of the dummy electrode DM is electrically connected to the second portion C2 of the semiconductor layer CH. The second portion M2 of the dummy electrode DM is disposed at one end of the second portion C2 of the semiconductor layer CH, and a portion of the second portion C2 of the semiconductor layer CH is covered by the second portion M2 of the dummy electrode DM. This reduces the exposed area of the upper surface of the second portion C2 of the semiconductor layer CH and reduces leakage current generated due to light reception on the upper surface of the second portion C2 of the semiconductor layer CH. The source electrode S is disposed at the other end of the second portion C2 of the semiconductor layer CH, and another portion of the second portion C2 of the semiconductor layer CH is covered by the source electrode S.
[0023] The dummy electrode DM has a connecting portion M3 positioned between the first portion M1 and the second portion M2. The connecting portion M3 connects the first portion M1 and the second portion M2, and in the direction DR3, the connecting portion M3 does not overlap with the first portion C1 and the second portion C2 of the semiconductor layer CH. In this embodiment (e.g.) Figure 2 The dummy electrode DM can be H-shaped, but is not limited thereto. Furthermore, in this invention, the first portion M1, the second portion M2, and the connecting portion M3 of the dummy electrode DM all overlap with the gate electrode G.
[0024] The first part M1 of the dummy electrode DM has a first width W1, the second part M2 of the dummy electrode DM has a second width W2, and the connecting part M3 of the dummy electrode DM has a third width W3. The third width W3 is smaller than the first width W1 and smaller than the second width W2.
[0025] In known transistors, the current is not completely shut off when the gate is turned off; some leakage paths still exist in the semiconductor layer, causing transistor leakage. According to the following equation (1), the amount of leakage is inversely proportional to the channel length of the transistor.
[0026]
[0027] In equation (1), I off Vt is the leakage current (unit: nanoampere (nA)), W is the channel width, L is the channel length, Vt is the threshold voltage, and S is the subthreshold swing.
[0028] In this invention, the dummy electrode DM, positioned between the source (S) and drain (D), increases the channel length of the transistor SW. As the channel length of the transistor SW increases, the electron leakage path lengthens, making it less likely for electrons to reach the other electrode, thus suppressing leakage. Furthermore, the design of the dummy electrode DM increases its impedance, further reducing the leakage current. Therefore, this invention reduces leakage current in the transistor SW through the dummy electrode DM, thereby enabling the display panel to achieve superior display quality.
[0029] like Figure 1 As shown, the sub-pixel SP includes an electrode FE, which may be disposed on one side of the transistor SW and electrically connected to the drain D of the transistor SW. The sub-pixel SP includes a transparent electrode TE (shown as a thick black line), which is disposed on the electrode FE and electrically connected to the electrode FE. For example, an insulating layer may be disposed between the transparent electrode TE and the electrode FE, the insulating layer may have a contact hole CO1, and the transparent electrode TE may be electrically connected to the electrode FE through the contact hole CO1, but this is not a limitation.
[0030] Sub-pixel SP includes a reflective electrode RE (represented by a slightly thicker black line) disposed on and electrically connected to a transparent electrode TE. For example, an insulating layer may be disposed between the reflective electrode RE and the transparent electrode TE, the insulating layer may have a contact hole CO2, and the reflective electrode RE may be electrically connected to the transparent electrode TE through the contact hole CO2, but this is not a limitation. The reflective electrode RE, the transparent electrode TE, and the electrode FE are electrically connected to each other and together electrically connected to the drain D of the transistor SW; therefore, the reflective electrode RE, the transparent electrode TE, and the electrode FE can together serve as a single pixel electrode.
[0031] In other words, the sub-pixel SP includes a pixel electrode, which is disposed on the substrate 100 and electrically connected to the drain D of the transistor SW, and the pixel electrode includes an electrode FE, a transparent electrode TE, and a reflective electrode RE.
[0032] Subpixel SP includes an electrode CE, which is disposed between electrode FE and substrate 100. Display panel 10 includes a common signal line CL extending in direction DR1. Electrode CE is electrically connected to common signal line CL, and common signal line CL can provide a common voltage to electrode CE.
[0033] In this invention, although the transistor SW further includes a dummy electrode DM, the area of the transistor SW is not significantly increased. This ensures that the sub-pixel SP still retains sufficient area to accommodate pixel electrodes (such as electrode FE, transparent electrode TE, and reflective electrode RE) and common electrodes (such as electrode CE), thereby providing sufficient storage capacitance. Therefore, image quality can be avoided due to insufficient capacitance during low-frequency driving.
[0034] On the other hand, such as Figure 3 The display panel 10 includes a conductive layer 202 and a conductive layer 206. The conductive layer 202 is disposed on the substrate 100, and the conductive layer 202 may include... Figure 1 The transistor SW includes a gate G, scan line GL, electrode CE, and common signal line CL, but is not limited thereto. A gate insulating layer 204 is disposed on the conductive layer 202, and a semiconductor layer CH is disposed on the gate insulating layer 204. A conductive layer 206 is disposed on the semiconductor layer CH and the gate insulating layer 204, and the conductive layer 206 may include... Figure 1 The data line DL, electrode FE, and source S, drain D, and dummy electrode DM of transistor SW are included, but not limited thereto. Therefore, the dummy electrode DM, source S, and drain D can be formed from the same conductive layer, and the materials of the dummy electrode DM, source S, and drain D can be the same, but not limited thereto. In some embodiments, another conductive layer may also be disposed on conductive layer 206 and between conductive layer 206 and transparent electrode TE, but not limited thereto.
[0035] The gate insulating layer 204 or other insulating layers may include, but are not limited to, inorganic or organic insulating materials. Conductive layers 202 and 206 may include single metal layers such as aluminum, copper, titanium, or tungsten, or composite metal layers such as molybdenum / aluminum / molybdenum, titanium / aluminum / titanium, titanium / copper / titanium, titanium / copper, etc., but are not limited to these. The transparent electrode TE may include transparent conductive materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), or aluminum zinc oxide (AZO), but are not limited to these. The reflective electrode RE may include suitable reflective metallic materials such as silver; the reflective electrode RE may also include a single metal layer or a composite metal layer, but is not limited to these.
[0036] The display panel of the present invention is not limited to the above embodiments. Other embodiments of the present invention will be disclosed below; however, in order to simplify the description and highlight the differences between the embodiments, the same reference numerals are used to refer to the same components, and repeated parts will not be described again.
[0037] Please refer to Figure 4 , Figure 4 This is an enlarged schematic diagram of the transistor in the display panel according to the second embodiment of the present invention. The shape of the dummy electrode DM in this embodiment differs from that in the first embodiment. In this embodiment, the dummy electrode DM has a bent and meandering shape, similar to the shape of a water pipe, but is not limited thereto. The bent design of the dummy electrode DM in this embodiment increases the length of the current path, thereby increasing the impedance of the dummy electrode DM. The third width W3 of the connection portion M3 of the dummy electrode DM is smaller than the first width W1 of the first portion M1, and the third width W3 is also smaller than the second width W2 of the second portion M2. This design also increases the impedance of the dummy electrode DM. Therefore, the dummy electrode DM in this embodiment can be used to reduce the leakage current of the transistor SW, thereby enabling the display panel to have good display quality. In addition, the dummy electrode DM can have different resistance values by adjusting the bending angle and adjusting the width.
[0038] In summary, in the display panel of the present invention, the transistor of the sub-pixel has a dummy electrode disposed between the source and drain, which increases the channel length of the transistor and thus suppresses leakage current. Furthermore, the impedance of the dummy electrode can be further increased through its shape design to suppress leakage current. In addition, the design of the semiconductor layer of the transistor into separate first and second parts also reduces leakage current. On the other hand, a portion of the semiconductor layer can be shielded by the dummy electrode, reducing the amount of light received by the semiconductor layer and thus reducing leakage current. Although the transistor further includes a dummy electrode, the area of the transistor is not significantly increased, ensuring sufficient area is reserved in the sub-pixel for the pixel electrode, thereby providing sufficient storage capacitance and preventing image quality from being affected by insufficient capacitance during low-frequency driving.
[0039] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A display panel, characterized in that, include: One substrate; as well as A sub-pixel is disposed on the substrate, wherein the sub-pixel includes a transistor, and the transistor includes: A gate is disposed on the substrate; A semiconductor layer is disposed on the gate, wherein the semiconductor layer includes a first portion and a second portion, and the first portion and the second portion are separate; A drain electrode is disposed on the first portion of the semiconductor layer and electrically connected to the first portion of the semiconductor layer; A source electrode is disposed on the second portion of the semiconductor layer and electrically connected to the second portion of the semiconductor layer; and A dummy electrode is disposed on the substrate, wherein, in a direction perpendicular to the substrate, the dummy electrode partially overlaps with both the first and second portions of the semiconductor layer. The dummy electrode is disposed between the source and the drain, the dummy electrode is separate from the source, the dummy electrode is separate from the drain, and the dummy electrode is electrically floating.
2. The display panel according to claim 1, characterized in that, The dummy electrode includes: A first portion is located at one end of the dummy electrode and close to the drain electrode, and the first portion of the dummy electrode is electrically connected to the first portion of the semiconductor layer; A second portion, located at the other end of the dummy electrode and close to the source electrode, and electrically connected to the second portion of the semiconductor layer; and A connecting portion is disposed between the first portion and the second portion.
3. The display panel according to claim 2, characterized in that, The first portion, the second portion, and the connection portion of the dummy electrode all overlap with the gate.
4. The display panel according to claim 2, characterized in that, A portion of the first portion of the semiconductor layer is covered by the first portion of the dummy electrode.
5. The display panel according to claim 2, characterized in that, A portion of the second portion of the semiconductor layer is covered by the second portion of the dummy electrode.
6. The display panel according to claim 2, characterized in that, The connection portion of the dummy electrode does not overlap with the first and second portions of the semiconductor layer.
7. The display panel according to claim 2, characterized in that, The first portion of the dummy electrode has a first width, the second portion of the dummy electrode has a second width, and the connecting portion of the dummy electrode has a third width, the third width being smaller than the first width and the third width being smaller than the second width.
8. The display panel according to claim 1, characterized in that, The sub-pixel also includes: A scan line is disposed on the substrate and electrically connected to the gate of the transistor; A data line is disposed on the substrate and electrically connected to the source of the transistor; and A pixel electrode is disposed on the substrate and electrically connected to the drain of the transistor.
9. The display panel according to claim 8, characterized in that, The pixel electrode includes: An electrode is disposed on one side of the transistor and electrically connected to the drain of the transistor; A transparent electrode is disposed on the electrode and electrically connected to the electrode; and A reflective electrode is disposed on the transparent electrode and electrically connected to the transparent electrode.