Three-dimensional semiconductor device

Abstract

A three-dimensional semiconductor device includes: a semiconductor pattern spaced apart from a substrate, extending in a first direction parallel to a bottom surface of the substrate; a word line at least partially surrounding the semiconductor pattern and extending in a second direction parallel to the bottom surface of the substrate and orthogonal to the first direction; and a bit line on the first side surface of the semiconductor pattern, extending in a third direction perpendicular to the bottom surface of the substrate. The word line includes a gate dielectric layer at least partially surrounding the semiconductor pattern and a gate electrode on the gate dielectric layer, the gate electrode may include a metal liner pattern and a gate electrode pattern on a side surface of the metal liner pattern. The metal liner pattern may have a U-shaped structure.

Description

Technical Field

[0001] This disclosure relates to three-dimensional semiconductor devices and methods for manufacturing the same, and more specifically, to three-dimensional semiconductor devices with improved reliability and high integration density. Background Technology

[0002] Due to their small size, versatility, and / or low cost, semiconductor devices are considered essential components in the electronics industry. Semiconductor devices are classified into semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices that include both storage and logic elements.

[0003] With the recent trend towards higher speeds and lower power consumption in electronic devices, semiconductor devices in these devices are also required to have high operating speeds and / or low operating voltages. To meet these requirements, the integration density of semiconductor devices needs to be increased. However, as the integration density of semiconductor devices increases, they may suffer from degraded electrical characteristics and lower manufacturing yields. Therefore, much research is underway to improve the electrical characteristics and manufacturing yield of semiconductor devices. Summary of the Invention

[0004] One embodiment of the present invention provides a three-dimensional semiconductor device with improved reliability.

[0005] According to one embodiment of the present invention, a three-dimensional semiconductor device includes: a semiconductor pattern spaced apart from a substrate and extending in a first direction parallel to a bottom surface of the substrate; a word line at least partially surrounding the semiconductor pattern and extending in a second direction parallel to the bottom surface of the substrate and orthogonal to the first direction; and a bit line on a first side surface of the semiconductor pattern, the bit line extending upward in a third direction perpendicular to the bottom surface of the substrate. The word line includes a gate dielectric layer at least partially surrounding the semiconductor pattern and a gate electrode on the gate dielectric layer, the gate electrode including a metal pad pattern and a gate electrode pattern on a side surface of the metal pad pattern. The metal pad pattern has a U-shaped structure.

[0006] According to one embodiment of the present invention, a three-dimensional semiconductor device includes: a semiconductor pattern spaced apart from a substrate and extending in a first direction parallel to a bottom surface of the substrate; a word line at least partially surrounding the semiconductor pattern and extending in a second direction parallel to the bottom surface of the substrate and orthogonal to the first direction; and a bit line extending upward on a first side surface of the semiconductor pattern in a third direction perpendicular to the bottom surface of the substrate. The word line includes a gate dielectric layer at least partially surrounding the semiconductor pattern and a gate electrode on the gate dielectric layer. The gate electrode includes a metal pad pattern and a gate electrode pattern on a side surface of the metal pad pattern. The gate electrode pattern includes a material having a higher work function than the metal pad pattern, and the gate electrode pattern may have a uniform grain size.

[0007] According to one embodiment of the present invention, a three-dimensional semiconductor device includes a first stack and a second stack, and a data storage pattern between the first stack and the second stack. The first stack and the second stack are on a substrate and adjacent to each other in a first direction parallel to the bottom surface of the substrate. The first stack may include: a first semiconductor pattern, spaced apart from the substrate and extending in the first direction; a first word line, at least partially surrounding the first semiconductor pattern and extending in a second direction parallel to the bottom surface of the substrate and orthogonal to the first direction; a first second line, on a first side surface of the first semiconductor pattern and extending upward in a third direction perpendicular to the bottom surface of the substrate; and a cover pattern, on one side of the first word line. The first word line may include a gate dielectric layer at least partially surrounding the first semiconductor pattern and a first gate electrode on the gate dielectric layer. The first gate electrode includes a first metal pad pattern having a first work function and a first gate electrode pattern having a second work function on a side surface of the first metal pad pattern. The first metal pad pattern extends from the top surface of the gate dielectric layer to the bottom surface of the gate dielectric layer via the side surface of the cover pattern, and the second work function is greater than the first work function. Attached Figure Description

[0008] Figure 1 This is a schematic diagram illustrating a three-dimensional semiconductor device according to an embodiment of the concept of the present invention.

[0009] Figure 2A , Figure 2B and Figure 2C This is a perspective view schematically illustrating a three-dimensional semiconductor device according to an embodiment of the concept of the present invention.

[0010] Figure 3 This is a plan view illustrating a three-dimensional semiconductor device according to an embodiment of the concept of the present invention.

[0011] Figure 4This is a perspective view showing the semiconductor pattern, word lines, bit lines, and data storage pattern of a three-dimensional semiconductor device according to an embodiment of the present invention.

[0012] Figure 5A It is along Figure 3 A cross-sectional view taken from line A-A'.

[0013] Figure 5B It is along Figure 3 The cross-sectional view taken by line B-B'.

[0014] Figure 5C It is along Figure 3 The cross-sectional view taken from line C-C'.

[0015] Figure 6 It is shown Figure 5A A magnified view of part "P1".

[0016] Figure 7A This illustrates another embodiment of the three-dimensional semiconductor device according to the concept of the present invention and corresponds to Figure 3 A cross-sectional view of line A-A'.

[0017] Figure 7B This illustrates another embodiment of the three-dimensional semiconductor device according to the concept of the present invention and corresponds to Figure 3 A cross-sectional view of line B-B'.

[0018] Figure 7C This illustrates another embodiment of the three-dimensional semiconductor device according to the concept of the present invention and corresponds to Figure 3 A cross-sectional view of line C-C'.

[0019] Figure 8 It is shown Figure 7A A magnified view of part "P1".

[0020] Figure 9 , Figure 10 , Figure 11A , Figure 11B , Figure 12 , Figure 13A , Figure 13B , Figure 14 , Figure 15 , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 17C , Figure 18 , Figure 19A , Figure 19B , Figure 19C , Figures 20 to 22 , Figure 23A , Figure 23B , Figures 24A to 24C , Figure 25 , Figure 26A , Figure 26B , Figure 26C and Figures 27 to 29 This is a diagram illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0021] Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, which illustrate example embodiments. In the drawings, the same reference numerals refer to the same elements, and repeated descriptions thereof are omitted. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should be noted that aspects described with respect to one embodiment may be incorporated into different embodiments, although not specifically described therein. That is, features of all and / or any embodiment may be combined in any manner and / or combination.

[0022] Figure 1 This is a schematic diagram illustrating a three-dimensional semiconductor device according to an embodiment of the concept of the present invention.

[0023] Reference Figure 1 The three-dimensional semiconductor device may include a memory cell array 1, a row decoder 2, a sensing amplifier 3, a column decoder 4, and control logic 5.

[0024] The memory cell array 1 may include word lines WL, bit lines BL, source lines SL, and memory cells MC. The memory cells MC may be arranged in three dimensions, and each memory cell MC may be connected to one of the word lines WL, one of the bit lines BL, and one of the source lines SL. In one embodiment, each memory cell MC may include a transistor, which includes a memory layer or a data storage layer.

[0025] The row decoder 2 can be configured to decode address information input from an external source (e.g., outside the three-dimensional semiconductor device) and select one of the word lines WL of the memory cell array 1 based on the decoded address information. The address information decoded by the row decoder 2 can be provided to the row driver (not shown), in which case the row driver can provide corresponding voltages to the selected word line and the unselected word line in the word line WL in response to control by the control circuit.

[0026] The sensing amplifier 3 can be configured to sense, amplify, and output the voltage difference between a bit line and a reference bit line selected based on address information decoded by the column decoder 4 in the bit line BL.

[0027] The column decoder 4 can be configured to establish a data transmission path between the sense amplifier 3 and an external device (e.g., a memory controller). The column decoder 4 can be configured to decode address information input from an external source (e.g., outside a three-dimensional semiconductor device) and select one of the bit lines BL based on the decoded address information.

[0028] Control logic 5 can be configured to generate control signals for controlling data write operations or data read operations on memory cell array 1.

[0029] Figure 2A , Figure 2B and Figure 2C This is a perspective view schematically illustrating a three-dimensional semiconductor device according to an embodiment of the concept of the present invention.

[0030] Reference Figure 2A The three-dimensional semiconductor device may include a substrate 100, a peripheral circuit structure PS on the substrate 100, and a cell array structure CS on the peripheral circuit structure PS.

[0031] The peripheral circuit structure PS may include core circuitry and peripheral circuitry formed on substrate 100. The core circuitry and peripheral circuitry may include reference circuitry. Figure 1 The row decoder 2 and column decoder 4, the sensing amplifier 3, and the control logic 5 are described.

[0032] The substrate 100 may be a plate-like structure extending parallel to the plane defined by the first direction D1 and the second direction D2. The first direction D1 and the second direction D2 may be parallel to the bottom surface of the substrate 100 and may not be parallel to each other. As an example, the first direction D1 and the second direction D2 may be horizontal directions orthogonal to each other. The peripheral circuit structure PS and the cell array structure CS may be stacked sequentially on the substrate 100 in a third direction D3 perpendicular to the bottom surface of the substrate 100.

[0033] The cell array structure CS may include bit lines BL, source lines SL, word lines WL, and memory cells MC between them. Each memory cell MC may be electrically connected to one of the word lines WL, one of the bit lines BL, and one of the source lines SL.

[0034] Reference Figure 2B The semiconductor device may include a cell array structure CS on the substrate 100 and a peripheral circuit structure PS on the cell array structure CS. The cell array structure CS may be disposed between the substrate 100 and the peripheral circuit structure PS. The peripheral circuit structure PS may include core circuitry and peripheral circuitry.

[0035] Reference Figure 2CThe semiconductor device can have a chip-to-chip (C2C) structure. The peripheral circuit structure PS can include a first substrate 100a. A lower metal pad LMP can be provided at the top of the peripheral circuit structure PS. The lower metal pad LMP can be electrically connected to the core circuit and the peripheral circuit. The lower metal pad LMP can be bonded to the upper metal pad UMP of the cell array structure CS.

[0036] The cell array structure CS may include a second substrate 200a, and an upper metal pad UMP may be provided at the bottom of the cell array structure CS. The upper metal pad UMP may be electrically connected to the bit line BL, the source line SL, and the word line WL. The upper metal pad UMP may be electrically connected to the memory cell MC.

[0037] Figure 3 This is a plan view illustrating a three-dimensional semiconductor device according to an embodiment of the concept of the present invention. Figure 4 This is a perspective view showing the semiconductor pattern, word lines, bit lines, and data storage pattern of a three-dimensional semiconductor device according to an embodiment of the present invention. Figure 5A It is along Figure 3 A cross-sectional view taken from line A-A'. Figure 5B It is along Figure 3 The cross-sectional view taken by line B-B'. Figure 5C It is along Figure 3 The cross-sectional view taken from line C-C'.

[0038] Reference Figures 3 to 5C The three-dimensional semiconductor device may include a substrate 100. The substrate 100 may be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor substrate may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate 100 may be a plate-like structure extending in a first direction D1 and a second direction D2.

[0039] A cell array structure CS can be provided on the substrate 100. The cell array structure CS may include a first stack ST1 and a second stack ST2 adjacent to each other in a first direction D1, and a data storage pattern DSP between the first stack ST1 and the second stack ST2. In one embodiment, although not shown, the cell array structure CS may include a plurality of cell array structures CS adjacent to each other in the first direction D1. For the sake of brevity, only one cell array structure CS will be described below, but other cell array structures CS may also have substantially the same features as described below.

[0040] Each of the first stack ST1 and the second stack ST2 may include a semiconductor pattern SP, a word line WL, a bit line BL, a first overlay pattern CP1, a second overlay pattern CP2, and a gap-filling insulating pattern 110. In one embodiment, the first stack ST1 and the second stack ST2 may be provided to have mirror symmetry with respect to the data storage pattern DSP.

[0041] The semiconductor pattern SP can extend on the substrate 100 in a first direction D1. In one embodiment, the semiconductor pattern SP can be a strip pattern extending in the first direction D1. The semiconductor pattern SP can be spaced apart from the substrate 100. That is, the semiconductor pattern SP can be floated from the substrate 100.

[0042] A semiconductor pattern SP may include a first edge portion EA1 and a second edge portion EA2 spaced apart from each other in a first direction D1, and a channel region CH provided between the first edge portion EA1 and the second edge portion EA2. The channel region CH of the semiconductor pattern SP may be at least partially surrounded by word lines WL, such as... Figure 5B and Figure 5C As shown. The first edge portion EA1 of the semiconductor pattern SP can be adjacent to the bit line BL. The first edge portion EA1 can contact and be electrically connected to the bit line BL. The second edge portion EA2 can be adjacent to the data storage pattern DSP. The second edge portion EA2 can contact and be electrically connected to the data storage pattern DSP.

[0043] The semiconductor pattern SP may have a first side surface S1 and a second side surface S2 that are opposite to each other. The first side surface S1 may be a side surface of a first edge portion EA1, and the second side surface S2 may be a side surface of a second edge portion EA2. The first side surface S1 of the semiconductor pattern SP may be in contact with a bit line BL, and the second side surface S2 may be in contact with a data storage pattern DSP.

[0044] The semiconductor pattern SP can include at least one of single-crystal semiconductor materials, polycrystalline semiconductor materials, oxide semiconductor materials, and / or two-dimensional materials. In one embodiment, the single-crystal semiconductor material can be single-crystal silicon. In one embodiment, the polycrystalline semiconductor material can be polycrystalline silicon. In one embodiment, the oxide semiconductor material can be indium gallium zinc oxide (IGZO). In one embodiment, the two-dimensional material can be MoS2, WS2, MoSe2, or WSe2.

[0045] In one embodiment, each of the first edge portion EA1 and the second edge portion EA2 of the semiconductor pattern SP may include an impurity region doped with impurities (e.g., n-type or p-type impurities). The impurity region may constitute the source / drain region of a transistor.

[0046] In one embodiment, a plurality of semiconductor patterns SP can be provided. The semiconductor patterns SP can be adjacent to each other in the second direction D2 and the third direction D3. The semiconductor patterns SP that are adjacent to each other in the third direction D3 can overlap each other perpendicularly (in the D3 direction). The semiconductor patterns SP that are adjacent to each other in the third direction D3 can have side surfaces aligned with each other.

[0047] The semiconductor pattern SP may include a first semiconductor pattern SPa provided in a first stack ST1 and a second semiconductor pattern SPb provided in a second stack ST2. The first semiconductor pattern SPa may be adjacent to the second semiconductor pattern SPb in a first direction D1. A first edge portion EA1 and a second edge portion EA2 of the first semiconductor pattern SPa may be sequentially arranged in the first direction D1. The first edge portion EA1 and the second edge portion EA2 of the second semiconductor pattern SPb may be sequentially arranged in the opposite direction to the first direction D1.

[0048] Word lines WL can extend in the second direction D2 to surround the channel region CH of the semiconductor pattern SP. In one embodiment, the word line WL can have a structure in cross-sectional view that completely surrounds the channel region CH of the semiconductor pattern SP (i.e., a gate full-around structure). The word line WL can be provided as a channel region CH surrounding each of the semiconductor patterns SP that are adjacent to each other in the second direction D2. In one embodiment, multiple word lines WL can be provided. Each word line WL can be provided as a channel region CH surrounding at least partially one of the semiconductor patterns SP that are adjacent to each other in the third direction D3, and can extend in the second direction D2.

[0049] The word line WL may include a first word line WLa and a second word line WLb, wherein the first word line WLa is provided in the first stack ST1 to at least partially surround the channel region CH of the first semiconductor pattern SPb, and the second word line WLb is provided in the second stack ST2 to at least partially surround the channel region CH of the second semiconductor pattern SPb.

[0050] The word line WL may include a gate dielectric layer Gox and a gate electrode GE, wherein the gate dielectric layer Gox is provided to at least partially surround a channel region CH of a semiconductor pattern SP, and the gate electrode GE is provided on the gate dielectric layer Gox to at least partially surround the channel region CH of the semiconductor pattern SP.

[0051] In one embodiment, the gate dielectric layer Gox may be formed or comprise at least one of a high-k dielectric material, silicon oxide, silicon nitride, and / or silicon nitride, and may be provided as a single-layer or multi-layer structure. In this specification, a high-k dielectric material may be defined as a material having a higher dielectric constant than silicon oxide.

[0052] The gate electrode GE may include a metal pad pattern SML having a first work function and a gate electrode pattern GEP provided on the side surface of the metal pad pattern SML to have a second work function. The metal pad pattern SML may be adjacent to a second edge portion EA2 of the semiconductor pattern SP, and the gate electrode pattern GEP may be adjacent to a first edge portion EA1 of the semiconductor pattern SP.

[0053] In one embodiment, the first work function of the metal pad pattern SML can be less than the second work function of the gate electrode pattern GEP. Furthermore, when the three-dimensional semiconductor device operates, gate-induced drain leakage (GIDL) in the semiconductor pattern SP can be reduced. As a result, the amount of holes accumulated in the semiconductor pattern SP can be reduced, and leakage current caused by holes can be reduced. Therefore, the reliability of the three-dimensional semiconductor device can be improved.

[0054] The metal pad pattern SML may include a first material having a first work function. The gate electrode pattern GEP may include a second material having a second work function. The first material may include a material different from the second material. The work function of the first material may be less than the work function of the second material.

[0055] In one embodiment, the first material may include at least one of Li, Na, K, Cs, Rb, Sr, Ba, Ca, Ce, Sm, Eu, Mg, Sc, Y, Hf, Tl, As, La, Nd, Gd, Tb, Lu, Th, U, Mn, Al, Ga, In, Pb, Cd, Bi, Zr, Ti, TiN, and / or n-type doped polycrystalline silicon. The second material may include Ti, TiN, TiSiN, TiON, W, WN, Mo, Ru, MoN, and MoO. x N y At least one of Ta, TaN and / or polycrystalline silicon.

[0056] The gate electrode GE may include: a first metal pad pattern SMLa and a first gate electrode pattern GEPa, providing a channel region CH in the first stack ST1 to at least partially surround the first semiconductor pattern SPb; and a second metal pad pattern SMLb and a second gate electrode pattern GEPb, providing a channel region CH in the second stack ST2 to at least partially surround the second semiconductor pattern SPb.

[0057] In the following text, reference will be made to Figure 6 The first metal pad pattern SMLa and the first gate electrode pattern GEPa are described according to an embodiment of the present invention.

[0058] Reference Figure 6 The first metal pad pattern SMLa can extend along the top or bottom surface of the gate dielectric layer Gox. Specifically, the first metal pad pattern SMLa can extend from the top surface of the gate dielectric layer Gox to the bottom surface of the gate dielectric layer Gox via the side surface of the first cover pattern CP1. The first metal pad pattern SMLa can be in contact with the gate dielectric layer Gox and the first cover pattern CP1. The first metal pad pattern SMLa can be a seed layer for forming the first gate electrode pattern GEPa.

[0059] When viewed in a cross-sectional view, the first metal pad pattern SMLa can have a U-shaped structure. Specifically, the first metal pad pattern SMLa can be a U-shaped pad pattern. The first metal pad pattern SMLa can be formed conformally. The first metal pad pattern SMLa can have a first thickness TH_S in the third direction D3. For example, the first thickness TH_S can be in the range of 1 Å to 50 Å. Although not shown, when viewed in a cross-sectional view, the second metal pad pattern SMLb can have a U-shaped structure. For example, the second metal pad pattern SMLb can have a U-shaped structure opposite to that of the first metal pad pattern SMLa. The second metal pad pattern SMLb can have a constant second thickness, which can be equal to the first thickness TH_S.

[0060] The first gate electrode pattern GEPa can be a conductive pattern formed using a first metal pad pattern SMLa as a seed layer. The first gate electrode pattern GEPa can be located within and at least partially fill the internal region of the first metal pad pattern SMLa, which has a U-shaped structure. Specifically, the first gate electrode pattern GEPa can include a first portion at least partially surrounded by the first metal pad pattern SMLa and a second portion at least partially surrounded by the gate dielectric layer Gox. The height of the second portion can be greater than the height of the first portion. The height can be defined as the vertical distance between the top and bottom surfaces measured in a third direction D3. The first metal pad pattern SMLa may not be provided on the top and bottom surfaces of the second portion.

[0061] The first gate electrode pattern GEPa can have a uniform grain size. The first gate electrode pattern GEPa can be formed of or comprise a second material having a uniform and continuous orientation. For example, the first gate electrode pattern GEPa can have an orientation in a first direction D1. Orientation can be defined as the ratio of the content of the second material included in the first gate electrode pattern GEPa and oriented in a specific direction (e.g., in the first direction D1) to the total content of several materials in the first gate electrode pattern GEPa. Here, in the case where the second material is formed of polycrystalline material, orientation can be defined as the orientation distribution of the grains.

[0062] According to one embodiment of the present invention, since the first gate electrode pattern GEPa is formed by growing a layer in a specific direction using a first metal pad pattern SMLa as a seed layer, pattern defects in the gate electrode can be reduced. As a result, the interconnect resistance of the gate electrode can be reduced, and thus the reliability of the three-dimensional semiconductor device can be improved.

[0063] Return to reference Figures 3 to 5C Bit lines BL can be provided on the first side surface S1 of the semiconductor pattern SP (i.e., the side surface of the first edge portion EA1). Bit lines BL can extend on the first side surface S1 of the semiconductor pattern SP in a third direction D3. Therefore, each bit line BL can contact and be electrically connected to the first side surface S1 of each of the semiconductor patterns SP that are adjacent to each other in the third direction D3. In one embodiment, multiple bit lines BL can be provided. Bit lines BL can be adjacent to each other in a second direction D2.

[0064] The bit line BL can be a single layer made of a single material or a composite layer comprising two or more materials. In one embodiment, the bit line BL can be formed from at least one or more metallic materials (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, or Co), one or more metal nitride materials (e.g., containing Ti, Mo, W, Cu, Al, Ta, Ru, Ir, or Co), and / or one or more metal silicide materials (e.g., containing Ti, Mo, W, Cu, Al, Ta, Ru, Ir, or Co), or include said one or more metallic materials, said one or more metal nitride materials, and / or said one or more metal silicide materials.

[0065] Bit line BL may include a first bit line BLa and a second bit line BLb. The first bit line BLa is provided in the first stack ST1 and on the first side surface S1 of the first semiconductor pattern SPb, and the second bit line BLb is provided in the second stack ST2 and on the first side surface S1 of the second semiconductor pattern SPb.

[0066] The data storage pattern DSP can be inserted between the first stack ST1 and the second stack ST2. The data storage pattern DSP can be inserted between the first semiconductor pattern SPa and the second semiconductor pattern SPb. The data storage pattern DSP can contact and be electrically connected to the first semiconductor pattern SPa via the second side surface S2 (i.e., the side surface of the second edge portion EA2). The data storage pattern DSP can contact and be electrically connected to the second semiconductor pattern SPb via the second side surface S2.

[0067] The data storage pattern DSP may include a storage electrode SE, a plate electrode PE, and a capacitor dielectric layer CIL interposed between the storage electrode SE and the plate electrode PE. In one embodiment, the three-dimensional semiconductor device may be a dynamic random access memory (DRAM) device, where the data storage pattern DSP can function as a capacitor. The storage electrode SE may be spaced from the plate electrode PE by the capacitor dielectric layer CIL.

[0068] Each of the storage electrode SE and the plate electrode PE may include a conductive material. In one embodiment, each of the storage electrode SE and the plate electrode PE may be formed of at least one of doped silicon (Si), doped silicon germanium (SiGe), metallic materials (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag), metal nitride materials (e.g., nitride materials comprising Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag), titanium silicon nitrides (e.g., TiSiN), titanium aluminum nitrides (e.g., TiAlN), tantalum aluminum nitrides (e.g., TaAlN), conductive oxide materials (e.g., PtO, RuO2, IrO2, SrRuO3 (SRO), (Ba,Sr)RuO3 (BSRO), CaRuO3 (CRO), and LSCo), and / or metal silicide materials, or include at least one of the above materials. Each of the storage electrode SE and the plate electrode PE can be a single layer made of a single material, or a composite layer comprising two or more materials.

[0069] In one embodiment, the capacitor dielectric layer (CIL) may include at least one of a metal oxide material (e.g., HfO2, ZrO2, Al2O3, La2O3, Ta2O3, and TiO2) and / or a perovskite dielectric material (e.g., SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, PZT, and PLZT).

[0070] In another embodiment, the data storage pattern DSP can be a variable resistance pattern whose resistance can be switched to one of at least two states by an electrical pulse applied thereto. For example, the data storage pattern DSP can be formed of or include at least one of phase change materials, perovskite compounds, transition metal oxides, magnetic materials, ferromagnetic materials and / or antiferromagnetic materials, and the crystal state of the phase change material can be changed according to the amount of current applied thereto.

[0071] The storage electrode SE may extend in the first direction D1 on the second side surface S2 of the first semiconductor pattern SPb. The storage electrode SE may also extend in the opposite direction D1 on the second side surface S2 of the second semiconductor pattern SPb. Although not shown, a silicide pattern (not shown) may be provided between the storage electrode SE and the first semiconductor pattern SPb, and between the storage electrode SE and the second semiconductor pattern SPb. The silicide pattern may be formed of one or more metal silicide materials (e.g., comprising Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and / or Co), or may include said one or more metal silicide materials. In one embodiment, a plurality of storage electrodes SE may be provided, wherein the storage electrodes SE may be adjacent to each other in the third direction D3.

[0072] The plate electrode PE may include a first region and a second region, the first region extending in a third direction D3, and the second region extending from the first region to protrude in a first direction D1 or the opposite direction of the first direction D1. The second region of the plate electrode PE may be interposed between adjacent storage electrodes SE in the third direction D3.

[0073] A gap-filling insulating pattern 110 may be provided on the substrate 100. The gap-filling insulating pattern 110 may be on and at least partially cover the side surface of the cell array structure CS. The gap-filling insulating pattern 110 may be interposed between bit lines BL and word lines WL, between semiconductor patterns SP adjacent to each other in the third direction D3, between the first edge portions EA1 of semiconductor patterns SP adjacent to each other in the second direction D2, and between word lines WL adjacent to each other in the third direction D3. The gap-filling insulating pattern 110 may include a single layer or a composite layer comprising insulating material.

[0074] A cover pattern CP can be provided in the cell array structure CS. The cover pattern CP can be interposed between word lines WL and data storage patterns DSP. The cover pattern CP can be interposed between adjacent semiconductor patterns SP on the third direction D3. The cover pattern CP can be interposed between the second edge portions EA2 of adjacent semiconductor patterns SP on the second direction D2.

[0075] The overlay pattern CP may include a first overlay pattern CP1 that at least partially surrounds a second edge portion EA2 of the semiconductor pattern SP and a second overlay pattern CP2 on the first overlay pattern CP1. The first overlay pattern CP1 may conformally at least partially cover the second edge portion EA2 of the semiconductor pattern SP and the side surface of the word line WL. Each of the first overlay pattern CP1 and the second overlay pattern CP2 may include an insulating material. The second overlay pattern CP2 may include a single layer or a composite layer.

[0076] A protective layer PL may be provided on the cell array structure CS. The protective layer PL may be on and at least partially cover the top surfaces of the first stack ST1, the second stack ST2, and the data storage pattern DSP. The protective layer PL may comprise a single layer or a composite layer containing insulating material. The protective layer PL may include a plurality of upper interconnects (not shown) provided therein. Some of these upper interconnects may be electrically connected to the bit line BL and the data storage pattern DSP, respectively. Furthermore, although not shown, word line pads (not shown) may be provided on the side surfaces of the cell array structure CS and may be electrically connected to the word line WL.

[0077] Figures 7A to 7C This illustrates one embodiment of the concept according to the present invention and corresponds to... Figures 5A to 5C Cross-sectional views of three-dimensional semiconductor devices with different implementations. Figure 7A It is along Figure 3 A cross-sectional view taken from line A-A'. Figure 7B This illustrates another embodiment of the three-dimensional semiconductor device according to the concept of the present invention and corresponds to Figure 3 A cross-sectional view of line B-B'. Figure 7C This illustrates another embodiment of the three-dimensional semiconductor device according to the concept of the present invention and corresponds to Figure 3 A cross-sectional view of line C-C'. Figure 8 It is shown Figure 7A An enlarged view of part "P1". In the following description, for the sake of brevity, previously described elements may be identified by the same reference numerals without repeating their overlapping descriptions.

[0078] Reference Figures 7A to 7C and Figure 8The word line WL may extend in the second direction D2 to at least partially surround the channel region CH of the semiconductor pattern SP. In one embodiment, the word line WL may have a structure in cross-sectional view that completely surrounds the channel region CH of the semiconductor pattern SP (i.e., a gate full-around structure). The word line WL may be provided as at least partially surrounding the channel region CH of each of the semiconductor patterns SP that are adjacent to each other in the second direction D2. In one embodiment, multiple word lines WL may be provided. Each word line WL may be provided as surrounding the channel region CH of a corresponding one of the semiconductor patterns SP that are adjacent to each other in the third direction D3, and may extend in the second direction D2.

[0079] The first metal pad pattern SMLa of the first letter line WLa can be provided on the top surface or the bottom surface of the first gate electrode pattern GEPa by the manufacturing method described below. That is, the first metal pad pattern SMLa can have a strip structure extending in the first direction D1, instead of a U-shaped structure.

[0080] The first metal pad pattern SMLa can be provided on a portion of the top or bottom surface of the gate dielectric layer Gox, so that the channel region CH is interposed between them.

[0081] In the following text, reference will be made to Figure 9 , Figure 10 , Figure 11A , Figure 11B , Figure 12 , Figure 13A , Figure 13B , Figure 14 , Figure 15 , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 17C , Figure 18 , Figure 19A , Figure 19B , Figure 19C , Figures 20 to 22 , Figure 23A , Figure 23B , Figures 24A to 24C , Figure 25 , Figure 26A , Figure 26B , Figure 26C and Figures 27 to 29 A method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention will be described in more detail. In the following description, for the sake of brevity, previously described elements may be identified by the same reference numerals without repeating their overlapping descriptions.

[0082] Figure 9 , Figure 10 , Figure 11A , Figure 11B , Figure 12 , Figure 13A , Figure 13B , Figure 14 , Figure 15 , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 17C , Figure 18 , Figure 19A , Figure 19B , Figure 19C , Figures 20 to 22 , Figure 23A , Figure 23B , Figures 24A to 24C , Figure 25 , Figure 26A , Figure 26B , Figure 26C and Figures 27 to 29 This is a diagram illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. Specifically, Figure 10 , Figure 12 , Figure 14 , Figure 18 and Figure 21 This is a plan view illustrating a three-dimensional semiconductor device according to an embodiment of the present invention. Figure 11A , Figure 13A , Figure 15 , Figure 16A , Figure 17A , Figure 19A , Figure 20 , Figure 22 , Figure 23A , Figure 24A , Figure 26A , Figure 27 and Figure 29 It is along Figure 3 A cross-sectional view taken from line A-A'. Figure 11B , Figure 13B , Figure 16B , Figure 17B , Figure 19B , Figure 23B , Figure 24B and Figure 26B It is along Figure 3 The cross-sectional view taken by line B-B'. Figure 17C , Figure 19C , Figure 24C and Figure 26C It is along Figure 3 The cross-sectional view taken from line C-C'.

[0083] Reference Figure 3 and Figure 9A substrate 100 can be fabricated. The sacrificial layer SAL and the active layer ACL can be formed and alternately stacked on the substrate 100. Each of the sacrificial layer SAL and the active layer ACL can be formed of or comprise a semiconductor material. The sacrificial layer SAL can comprise a material with etch selectivity relative to the active layer ACL. Therefore, in subsequent processes that remove the sacrificial layer SAL, the removal of the active layer ACL can be reduced or minimized. In one embodiment, the active layer ACL and the sacrificial layer SAL can be formed of or comprise at least one of silicon (Si), germanium (Ge), and / or silicon-germanium (SiGe), but the material of the sacrificial layer SAL can be different from the material of the active layer ACL. In one embodiment, the active layer ACL can be formed of or comprise silicon (Si), and the sacrificial layer SAL can be formed of or comprise silicon-germanium (SiGe). When measured on a third-party direction D3, the thickness of the sacrificial layer SAL can be greater than the thickness of the active layer ACL.

[0084] Reference Figures 10 to 11B A first via HL1 can be formed on substrate 100 by partially removing each of the sacrificial layer SAL and the active layer ACL. The first via HL1 can be formed to be adjacent to each other in a first direction D1 and a second direction D2. A portion of the top surface of substrate 100 can be exposed to the outside through the first via HL1. As a result of the removal process, the sacrificial layer SAL and the active layer ACL can be formed to include portions extending in the first direction D1 and portions extending in the second direction D2.

[0085] The first initial fill pattern PF1 may be formed on and at least partially covers the exposed portion of the top surface of the substrate 100, and at least partially fills the first hole HL1. In one embodiment, the first initial fill pattern PF1 may include an insulating material. The first initial fill pattern PF1 may be formed adjacent to each other in the first direction D1 and the second direction D2.

[0086] Some of the sacrificial layer SAL and active layer ACL that extend in the second direction D2 can be removed to form a second hole HL2 on the substrate 100. The second hole HL2 can be formed to extend in the second direction D2. The opposite side surfaces of the sacrificial layer SAL and active layer ACL can be exposed to the outside through the second hole HL2. During the formation of the second hole HL2, the upper part of the substrate 100 can be partially recessed to a certain depth. A portion of the top surface of the substrate 100 can be exposed to the outside through the second hole HL2.

[0087] Reference Figures 12 to 13BThe exposed opposing side surfaces of the sacrificial layer SAL can be selectively removed through the second aperture HL2. Therefore, a first internal region INR1 can be formed between adjacent active layers ACL on the third direction D3. Each first initial fill pattern PF1 can also be partially removed during the removal process. The side surfaces of the first initial fill pattern PF1 can be aligned with the side surfaces of the sacrificial layer SAL.

[0088] A second initial fill pattern PF2 may be formed in the first internal region INR1. The second initial fill pattern PF2 may be formed to at least partially fill the empty region formed by partially removing the first initial fill pattern PF1 and the internal space of the second via HL2. The second initial fill pattern PF2 may at least partially surround and cover the portion of the active layer ACL that does not overlap with the sacrificial layer SAL. The second initial fill pattern PF2 may comprise a single layer or a composite layer containing insulating material. In one embodiment, the second initial fill pattern PF2 may be formed of or include at least one of silicon oxide and / or silicon nitride.

[0089] Reference Figure 14 and Figure 15 A third via HL3 can be formed on substrate 100 by removing portions of the sacrificial layer SAL and the active layer ACL extending in the second direction D2. During the formation of the third via HL3, each active layer ACL can be divided into semiconductor patterns SP adjacent to each other in the first direction D1. The semiconductor patterns SP may include a first semiconductor pattern SPa and a second semiconductor pattern SPb adjacent to each other in the first direction D1. In the process of forming the third via HL3, the sacrificial layer SAL can be at least partially exposed to the outside.

[0090] The exposed sacrificial layer SAL can be completely removed from the substrate 100 through the third via HL3. Therefore, the second internal region INR2 can be formed between regions of the active layer ACL that do not overlap with the second initial fill pattern PF2. During the removal process, the first initial fill pattern PF1 can be removed from the region on the substrate 100. Next, a third initial fill pattern PF3 can be formed to at least partially fill the second internal region INR2, the empty region formed by removing the first initial fill pattern PF1, and the third via HL3. The third initial fill pattern PF3 may comprise a single layer or a composite layer containing an insulating material. In one embodiment, the third initial fill pattern PF3 may be formed of or include at least one of silicon oxide and / or silicon nitride.

[0091] Reference Figure 16A and Figure 16BThe second initial fill pattern PF2 can be partially removed from the substrate 100. Next, a gate dielectric layer Gox and initial metal pad layers PSMLa and PSMLb can be sequentially formed in the empty area formed by removing the second initial fill pattern PF2. The gate dielectric layer Gox and the initial metal pad layers PSMLa and PSMLb can be sequentially formed to conformally cover a portion of the semiconductor pattern SP and a portion of the second initial fill pattern PF2. The gate dielectric layer Gox and the initial metal pad layers PSMLa and PSMLb can be formed to cover a portion of the semiconductor pattern SP and a portion of the second initial fill pattern PF2. One of the gate dielectric layer Gox and the initial metal pad layers PSMLa and PSMLb can be formed to surround and cover a portion of each of the semiconductor patterns SP adjacent to each other in the second direction D2 and the third direction D3.

[0092] Reference Figures 17A to 17C Hard mask layers SOHa and SOHb can be formed on the initial metal pad layers PSMLa and PSMLb. Specifically, hard mask layers SOHa and SOHb can be formed to partially fill the region between the initial metal pad layers PSMLa and PSMLb. The hard mask layers SOHa and SOHb can be inorganic or organic hard mask layers, and in one embodiment, they can be carbon-based hard mask layers (e.g., carbon-based SOH layers). The hard mask layers SOHa and SOHb can protect portions of the initial metal pad layers PSMLa and PSMLb during subsequent etching processes and can inhibit or prevent the removal of such portions of the initial metal pad layers PSMLa and PSMLb.

[0093] After forming the hard mask layers SOHa and SOHb, an etching process can be performed to remove the exposed portions of the initial metal pad layers PSMLa and PSMLb. The remaining portions of the initial metal pad layers PSMLa and PSMLb protected by the hard mask layers SOHa and SOHb and not removed can be used to form the metal pad patterns SMLa and SMLb. In one embodiment, the initial metal pad layers PSMLa and PSMLb on the second initial fill pattern PF2 can also be removed by an etching process.

[0094] The metal pad patterns SMLa and SMLb may include a first metal pad pattern SMLa that at least partially surrounds a first semiconductor pattern SPa and a second metal pad pattern SMLb that at least partially surrounds a second semiconductor pattern SPb.

[0095] Reference Figure 18 and Figures 19A to 19CThe hard mask layers SOHa and SOHb on the metal pad patterns SMLa and SMLb can be removed by performing an ashing or stripping process. After removing the hard mask layers SOHa and SOHb, the metal pad patterns SMLa and SMLb can be used as seed layers to form the initial gate electrode patterns PGEa and PGEb. Specifically, the initial gate electrode patterns PGEa and PGEb can be formed by a selective growth method that selectively grows layers from the seed layer in a specific direction (e.g., a first direction D1 or the opposite direction of the first direction D1).

[0096] When the initial gate electrode patterns PGEa and PGEb are selectively grown in a specific direction, the metallic or conductive material in the initial gate electrode patterns PGEa and PGEb can be formed with a uniform grain size. Furthermore, because the initial gate electrode patterns PGEa and PGEb are grown in a specific direction, they can be formed with a uniform orientation. Therefore, pattern defects (such as voids or seams) in the initial gate electrode patterns PGEa and PGEb can be prevented or suppressed, thereby improving the reliability of the three-dimensional semiconductor device.

[0097] The initial gate electrode patterns PGEa and PGEb may include a first initial gate electrode pattern PGEa adjacent to the first semiconductor pattern SPa and a second initial gate electrode pattern PGEb adjacent to the second semiconductor pattern SPb.

[0098] The gate dielectric layer Gox and one of the initial gate electrode patterns PGEa and PGEb can be formed to at least partially surround and cover a portion of each of the adjacent semiconductor patterns SP on the second direction D2 and the third direction D3. Next, a second initial fill pattern PF2 between the initial gate electrode patterns PGEa or PGEb can be removed, and a gap-filled insulating pattern 110 can be formed in the first internal region INR1 and the empty region formed by removing the second initial fill pattern PF2.

[0099] Bit line BL can be formed to penetrate or extend through the gap-filled insulating pattern 110 and contact the side surface of the semiconductor pattern SP. Bit line BL may include a first bit line BLa in contact with the first semiconductor pattern SPa and a second bit line BLb in contact with the second semiconductor pattern SPb.

[0100] Reference Figure 3 and Figure 20The third initial fill pattern PF3 can be removed from the substrate 100. A portion of the gate dielectric layer Gox can also be removed by a removal process. In this case, the metal pad patterns SMLa and SMLb and the initial gate electrode patterns PGEa and PGEb can remain unremoved, and therefore, the metal pad patterns SMLa and SMLb can have a U-shaped structure. Thus, each gate dielectric layer Gox can be divided into a plurality of gate dielectric layers Gox, which are adjacent to each other in the second direction D2 and the third direction D3. Each gate dielectric layer Gox can be provided to at least partially surround a corresponding one of the semiconductor patterns SP. After removing the third initial fill pattern PF3, the initial gate electrode patterns PGEa and PGEb can form gate electrode patterns GEa and GEb. Each of the gate electrode patterns GEa and GEb can be provided to at least partially surround a corresponding one of the semiconductor patterns SP.

[0101] During the removal process, the second internal region INR2 can be exposed to the outside (outside of the structure). The side surfaces of the gate dielectric layer Gox and the gap-filling insulating pattern 110 can be exposed to the outside (outside of the structure) through the second internal region INR2.

[0102] The gate electrode patterns GEa and GEb may include a first gate electrode pattern GEa that at least partially surrounds a first semiconductor pattern SPa and a second gate electrode pattern GEb that at least partially surrounds a second semiconductor pattern SPb.

[0103] Reference Figure 21 and Figure 22 The overlay pattern CP can be formed to at least partially fill the second internal region INR2 and the empty region formed by removing the third initial fill pattern PF3. The overlay pattern CP can include a first overlay pattern CP1 and a second overlay pattern CP2, wherein the first overlay pattern CP1 is provided to conformally cover the second internal region INR2 and the second edge portion EA2 of the semiconductor pattern SP, and the second overlay pattern CP2 is provided to at least partially fill the remaining portion of the second internal region INR2 and surround the second edge portion EA2 of the semiconductor pattern SP.

[0104] Next, a portion of the cover pattern CP can be removed to form a fourth hole HL4 on the substrate 100. The fourth hole HL4 can be formed to extend in the second direction D2. The second edge portion EA2 of the semiconductor pattern SP can be exposed to the outside (outside of the structure) through the fourth hole HL4.

[0105] The removal process can be performed on the exposed second edge portion EA2 of the semiconductor pattern SP through the fourth hole HL4. Alternatively, a removal process can be performed on a portion of the first overlay pattern CP1.

[0106] The storage electrode SE can be formed on the second edge portion EA2 of the semiconductor pattern SP. In one embodiment, the formation of the storage electrode SE may include forming a silicide pattern (not shown) on the second edge portion EA2 of the semiconductor pattern SP and forming the storage electrode SE using a SEG process that uses the silicide pattern as a seed layer.

[0107] Return to reference Figures 3 to 5C A removal process can be performed on a portion of the second overlay pattern CP2. In one embodiment, the side surface of the second overlay pattern CP2 can be aligned with the side surface of the second edge portion EA2 of the semiconductor pattern SP. Thereafter, a capacitor dielectric layer CIL can be formed to conformally at least partially cover the storage electrode SE. The plate electrode PE can be formed to at least partially fill the reference. Figure 21 and Figure 22 The area between the storage electrodes SE and the remainder of the fourth hole HL4 are described. The storage electrodes SE, the capacitor dielectric layer CIL, and the plate electrode PE can constitute the data storage pattern DSP. Subsequently, the protective layer PL can be formed to at least partially cover the cell array structure CS.

[0108] Figures 23A to 29 This is a diagram illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the concept of the present invention. Figures 23A to 29 Showing with Figures 16A to 22 The manufacturing methods in the embodiments are different from those in the following description. In the following description, for the sake of brevity, previously described elements may be identified by the same reference numerals without repeating their overlapping descriptions.

[0109] Reference Figure 23A and Figure 23B The second initial fill pattern PF2 can be removed from the substrate 100. Next, a gate dielectric layer Gox and metal pad patterns SMLa and SMLb can be sequentially formed in the first internal region INR1. The gate dielectric layer Gox and the metal pad patterns SMLa and SMLb can be sequentially formed to conformally at least partially cover a portion of the semiconductor pattern SP. The gate dielectric layer Gox and the metal pad patterns SMLa and SMLb can be formed to surround and cover a portion of the semiconductor pattern SP. Each of the gate dielectric layers Gox and each of the metal pad patterns SMLa and SMLb can be formed to surround and cover a portion of each of the semiconductor patterns SP adjacent to each other in the second direction D2 and the third direction D3. Thereafter, a gap-filling insulating pattern 110 can be formed in the first internal region INR1 and the empty region formed by removing the second initial fill pattern PF2.

[0110] Reference Figures 24A to 24CHard mask layers SOHa and SOHb can be formed on the metal pad patterns SMLa and SMLb. Specifically, hard mask layers SOHa and SOHb can be formed to partially fill the area between the metal pad patterns SMLa and SMLb. The hard mask layers SOHa and SOHb can be inorganic or organic hard mask layers, and in one embodiment, they can be carbon-based hard mask layers (e.g., a carbon-based SOH layer). The hard mask layers SOHa and SOHb can protect portions of the metal pad patterns SMLa and SMLb during subsequent etching processes and can inhibit or prevent the removal of those portions.

[0111] After forming the hard mask layers SOHa and SOHb, an etching process can be performed to remove the exposed portions of the metal pad patterns SMLa and SMLb. The remaining portions of the metal pad patterns SMLa and SMLb protected by the hard mask layers SOHa and SOHb and not removed can then be used to form the metal pad patterns SMLa and SMLb.

[0112] The metal pad patterns SMLa and SMLb may include a first metal pad pattern SMLa that at least partially surrounds a first semiconductor pattern SPa and a second metal pad pattern SMLb that at least partially surrounds a second semiconductor pattern SPb.

[0113] Reference Figure 25 and Figures 26A to 26C The hard mask layers SOHa and SOHb on the metal pad patterns SMLa and SMLb can be removed by performing an ashing or stripping process. After removing the hard mask layers SOHa and SOHb, the metal pad patterns SMLa and SMLb can be used as seed layers to form the initial gate electrode patterns PGEa and PGEb. Specifically, the initial gate electrode patterns PGEa and PGEb can be formed by a selective growth method that selectively grows layers from the seed layers in a specific direction (e.g., a first direction D1 or the opposite direction of the first direction D1). The metal pad patterns SMLa and SMLb can have a U-shaped structure.

[0114] When the initial gate electrode patterns PGEa and PGEb are selectively grown in a specific direction, the metallic or conductive material in the initial gate electrode patterns PGEa and PGEb can be formed with a uniform grain size. Furthermore, because the initial gate electrode patterns PGEa and PGEb are grown in a specific direction, they can be formed with a uniform orientation. Therefore, pattern defects (such as voids or seams) in the initial gate electrode patterns PGEa and PGEb can be prevented or suppressed, thereby improving the reliability of the three-dimensional semiconductor device.

[0115] The initial gate electrode patterns PGEa and PGEb may include a first initial gate electrode pattern PGEa adjacent to the first semiconductor pattern SPa and a second initial gate electrode pattern PGEb adjacent to the second semiconductor pattern SPb.

[0116] Each of the gate dielectric layer Gox and each of the initial gate electrode patterns PGEa and PGEb can be formed as a portion surrounding and covering each of the semiconductor patterns SP adjacent to each other on the second direction D2 and the third direction D3. Thereafter, a gap-filling insulating pattern 110 can be formed in the first internal region INR1 and the empty region formed by removing the second initial fill pattern PF2.

[0117] Bit line BL can be formed to penetrate or extend through the gap-filled insulating pattern 110 and contact the side surface of the semiconductor pattern SP. Bit line BL may include a first bit line BLa in contact with the first semiconductor pattern SPa and a second bit line BLb in contact with the second semiconductor pattern SPb.

[0118] Reference Figure 3 and Figure 27 The third initial fill pattern PF3 can be removed from the substrate 100. The gate dielectric layer Gox and the initial gate electrode patterns PGEa and PGEb can also be removed by a removal process. Therefore, each gate dielectric layer Gox can be divided into multiple gate dielectric layers Gox, which are adjacent to each other in the second direction D2 and the third direction D3. Furthermore, each of the initial gate electrode patterns PGEa and PGEb can be divided into multiple initial gate electrode patterns PGEa and PGEb adjacent to each other in the second direction D2 and the third direction D3. Additionally, the side surfaces of the U-shaped metal pad patterns SMLa and SMLb can also be removed, thus the metal pad patterns SMLa and SMLb can be divided into metal pad patterns SMLa and SMLb adjacent to each other in the second direction D2 and the third direction D3.

[0119] Each gate dielectric layer Gox may at least partially surround a corresponding one of the semiconductor patterns SP. After partially removing the third initial fill pattern PF3, the gate dielectric layer Gox, and the initial gate electrode patterns PGEa and PGEb, the initial gate electrode patterns PGEa and PGEb may form gate electrode patterns GEa and GEb. Each of the gate electrode patterns GEa and GEb may be provided to at least partially surround a corresponding one of the semiconductor patterns SP.

[0120] During the removal process, the second internal region INR2 can be exposed to the outside (outside the structure). The side surfaces of the gate electrode patterns GEa and GEb, as well as the side surfaces of the metal pad patterns SMLa and SMLb, can be exposed to the outside (outside the structure) through the second internal region INR2.

[0121] After the removal process, a first metal pad pattern SMLa can be provided on the top or bottom surface of the first gate electrode pattern GEa. That is, the first metal pad pattern SMLa can have a strip structure extending in the first direction D1, instead of a U-shaped structure. A second metal pad pattern SMLb can be provided on the top or bottom surface of the second gate electrode pattern GEb. That is, the second metal pad pattern SMLb can have a strip structure extending in the first direction D1, instead of a U-shaped structure.

[0122] Each of the first metal pad pattern SMLa and the second metal pad pattern SMLb can be formed on a portion of the top or bottom surface of the gate dielectric layer Gox, with the channel region CH interposed between them.

[0123] The gate electrode patterns GEa and GEb may include a first gate electrode pattern GEa that at least partially surrounds a first semiconductor pattern SPa and a second gate electrode pattern GEb that at least partially surrounds a second semiconductor pattern SPb.

[0124] Reference Figure 28 and Figure 29 A cover pattern CP can be formed to at least partially fill the second internal region INR2 and the empty region formed by removing the third initial fill pattern PF3. The cover pattern CP may include a first cover pattern CP1 and a second cover pattern CP2, wherein the first cover pattern CP1 is provided to conformally at least partially cover the second internal region INR2 and the second edge portion EA2 of the semiconductor pattern SP, and the second cover pattern CP2 is provided to at least partially fill the remaining portion of the second internal region INR2 and at least partially surround the second edge portion EA2 of the semiconductor pattern SP.

[0125] Next, a portion of the cover pattern CP can be removed to form a fourth hole HL4 on the substrate 100. The fourth hole HL4 can be formed to extend in the second direction D2. The second edge portion EA2 of the semiconductor pattern SP can be at least partially exposed to the outside (exterior of the structure) through the fourth hole HL4.

[0126] A removal process can be performed on the exposed second edge portion EA2 of the semiconductor pattern SP through the fourth hole HL4. Here, a removal process can also be performed on a portion of the first overlay pattern CP1.

[0127] The storage electrode SE can be formed on the second edge portion EA2 of the semiconductor pattern SP. In one embodiment, the formation of the storage electrode SE may include forming a silicide pattern (not shown) on the second edge portion EA2 of the semiconductor pattern SP and forming the storage electrode SE using a SEG process that uses the silicide pattern as a seed layer.

[0128] Return to reference Figure 3 and Figures 7A to 7C A removal process can be performed on a portion of the second overlay pattern CP2. In one embodiment, the side surface of the second overlay pattern CP2 can be aligned with the side surface of the second edge portion EA2 of the semiconductor pattern SP. Thereafter, a capacitor dielectric layer CIL can be formed to conformally at least partially cover the storage electrode SE. A plate electrode PE can be formed to at least partially fill the reference. Figure 28 and Figure 29 The area between the storage electrodes SE and the remainder of the fourth hole HL4 are described. The storage electrodes SE, the capacitor dielectric layer CIL, and the plate electrode PE can constitute the data storage pattern DSP. Subsequently, the protective layer PL can be formed to at least partially cover the cell array structure CS.

[0129] According to embodiments of the present invention, word lines may include a metal pad pattern and a gate electrode on the metal pad pattern, the gate electrode being formed from the metal pad pattern by a selective growth process. Therefore, the gate electrode can have a uniform grain size and uniform orientation, which allows for the reduction of pattern defects (e.g., voids or seams) in the word lines. Consequently, the resistance of the word lines can be reduced.

[0130] Furthermore, when operating a three-dimensional semiconductor device, gate-induced drain leakage (GIDL) in the semiconductor pattern can be reduced. As a result, the amount of holes accumulating in the semiconductor pattern can be reduced, and leakage current caused by holes can be reduced.

[0131] Therefore, the reliability of three-dimensional semiconductor devices can be improved.

[0132] Although exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that variations in form and detail may be made therein without departing from the spirit and scope of the appended claims.

[0133] This application claims priority to Korean Patent Application No. 10-2024-0139761, filed on October 14, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A three-dimensional semiconductor device, comprising: A semiconductor pattern, spaced apart from the substrate, extends in a first direction parallel to the bottom surface of the substrate; The letter lines at least partially surround the semiconductor pattern and extend in a second direction, which is parallel to the bottom surface of the substrate and orthogonal to the first direction; as well as Bit lines extend upward on a third surface perpendicular to the bottom surface of the substrate on a first side surface of the semiconductor pattern. The word line includes a gate dielectric layer that at least partially surrounds the semiconductor pattern and a gate electrode on the gate dielectric layer. The gate electrode includes a metal pad pattern and a gate electrode pattern on the side surface of the metal pad pattern, and The metal liner pattern has a U-shaped structure.

2. The three-dimensional semiconductor device according to claim 1, further comprising a cover pattern on one side of the word line. The metal pad pattern extends from the top surface of the gate dielectric layer to the bottom surface of the gate dielectric layer via the side surface of the overlay pattern.

3. The three-dimensional semiconductor device of claim 1, wherein the metal pad pattern is a pad pattern conformally formed on the gate dielectric layer.

4. The three-dimensional semiconductor device of claim 3, wherein the metal pad pattern has a thickness in the range of 1 Å to 50 Å.

5. The three-dimensional semiconductor device of claim 1, wherein the gate electrode pattern comprises a first portion at least partially surrounded by the metal pad pattern and a second portion at least partially surrounded by the gate dielectric layer.

6. The three-dimensional semiconductor device of claim 5, wherein in the third direction, the height of the second portion is greater than the height of the first portion.

7. The three-dimensional semiconductor device of claim 5, wherein the top and bottom surfaces of the second portion are free of the metal pad pattern.

8. The three-dimensional semiconductor device according to claim 1, wherein the work function of the metal pad pattern is less than the work function of the gate electrode pattern.

9. The three-dimensional semiconductor device according to claim 1, wherein the metal pad pattern comprises at least one of Li, Na, K, Cs, Rb, Sr, Ba, Ca, Ce, Sm, Eu, Mg, Sc, Y, Hf, Tl, As, La, Nd, Gd, Tb, Lu, Th, U, Mn, Al, Ga, In, Pb, Cd, Bi, Zr, Ti, TiN, and n-type doped polycrystalline silicon.

10. The three-dimensional semiconductor device according to claim 1, wherein the gate electrode pattern comprises Ti, TiN, TiSiN, TiON, W, WN, Mo, Ru, MoN, MoO x N y At least one of Ta, TaN, and polycrystalline silicon.

11. The three-dimensional semiconductor device according to claim 1, wherein the semiconductor pattern comprises at least one of single-crystal semiconductor material, polycrystalline semiconductor material, oxide semiconductor material, and two-dimensional material.

12. The three-dimensional semiconductor device of claim 1, further comprising a data storage pattern on a second side surface of the semiconductor pattern opposite to the first side surface.

13. A three-dimensional semiconductor device, comprising: A semiconductor pattern, spaced apart from the substrate, extends in a first direction parallel to the bottom surface of the substrate; The letter lines at least partially surround the semiconductor pattern and extend in a second direction, which is parallel to the bottom surface of the substrate and orthogonal to the first direction; as well as Bit lines extend upward on a third surface perpendicular to the bottom surface of the substrate on a first side surface of the semiconductor pattern. The word line includes a gate dielectric layer that at least partially surrounds the semiconductor pattern and a gate electrode on the gate dielectric layer. The gate electrode comprises a metal pad pattern and a gate electrode pattern on the side surface of the metal pad pattern. The gate electrode pattern comprises a material having a higher work function than the metal pad pattern, and The gate electrode pattern thereon has a uniform grain size.

14. The three-dimensional semiconductor device of claim 13, wherein the material in the gate electrode pattern has a uniform and continuous orientation.

15. The three-dimensional semiconductor device of claim 13, wherein the material in the gate electrode pattern comprises Ti, TiN, TiSiN, TiON, W, WN, Mo, Ru, MoN, MoO x N y At least one of Ta, TaN, and polycrystalline silicon.

16. The three-dimensional semiconductor device of claim 13, wherein the material in the metal pad pattern comprises at least one of Li, Na, K, Cs, Rb, Sr, Ba, Ca, Ce, Sm, Eu, Mg, Sc, Y, Hf, Tl, As, La, Nd, Gd, Tb, Lu, Th, U, Mn, Al, Ga, In, Pb, Cd, Bi, Zr, Ti, TiN, and n-type doped polycrystalline silicon.

17. The three-dimensional semiconductor device of claim 13, further comprising a data storage pattern on a second side surface of the semiconductor pattern opposite to the first side surface.

18. A three-dimensional semiconductor device, comprising: The first stack and the second stack are adjacent to each other on the substrate and in a first direction parallel to the bottom surface of the substrate; and Data storage pattern, between the first stack and the second stack, The first stack includes: A first semiconductor pattern is spaced apart from the substrate and extends in the first direction; A first letter line, at least partially surrounding the first semiconductor pattern and extending in a second direction, the second direction being parallel to the bottom surface of the substrate and orthogonal to the first direction; The first line extends upward on a first side surface of the first semiconductor pattern and on a third side perpendicular to the bottom surface of the substrate; and The overlay pattern is located on one side of the first letter line. The first word line includes a gate dielectric layer that at least partially surrounds the first semiconductor pattern and a first gate electrode on the gate dielectric layer. The first gate electrode includes a first metal pad pattern having a first work function and a first gate electrode pattern having a second work function on the side surface of the first metal pad pattern. The first metal pad pattern extends from the top surface of the gate dielectric layer to the bottom surface of the gate dielectric layer via the side surface of the overlay pattern, and The second work function is greater than the first work function.

19. The three-dimensional semiconductor device of claim 18, wherein the second stack comprises: A second semiconductor pattern is spaced apart from the substrate and extends in the first direction; The second letter line at least partially surrounds the second semiconductor pattern and extends in the second direction; as well as The second bit line extends upward on the side surface of the second semiconductor pattern and upward on the third.

20. The three-dimensional semiconductor device of claim 18, wherein the first metal pad pattern comprises at least one selected from Li, Na, K, Cs, Rb, Sr, Ba, Ca, Ce, Sm, Eu, Mg, Sc, Y, Hf, Tl, As, La, Nd, Gd, Tb, Lu, Th, U, Mn, Al, Ga, In, Pb, Cd, Bi, Zr, Ti, TiN, and n-type doped polycrystalline silicon, and The first gate electrode pattern includes Ti, TiN, TiSiN, TiON, W, WN, Mo, Ru, MoN, and MoO. x N y At least one of Ta, TaN, and polycrystalline silicon.

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