Semiconductor device and method of manufacturing the same

Abstract

The purpose of the present invention is to reduce recovery loss and suppress surge voltage in an RC-IGBT. A semiconductor device has: an n-type field stop region distributed across an IGBT region and a diode region; a p-type collector region disposed in the IGBT region on the lower side of the field stop region; a plurality of n-type cathode regions disposed in the diode region on the lower side of the field stop region; and a plurality of p-type surge suppression regions disposed below the field stop region in the diode region. Each of the cathode regions has: a first cathode region in contact with the lower electrode and having an n-type impurity concentration of 1 * 1019 cm-3 or more; and a second cathode region disposed between the first cathode region and the field stop region and having an activation rate of n-type impurities of 85% or less.

Description

Technical Field

[0001] (Cross-reference to related applications) This application is a related application to Japanese Patent Application No. 2023-078489, filed on May 11, 2023, and claims priority based on that Japanese patent application, incorporating all the contents of that Japanese patent application as part of this specification.

[0002] The technology disclosed in this specification relates to semiconductor devices and methods for manufacturing the same. Background Technology

[0003] Japanese Patent Application Publication No. 2015-211149 (hereinafter referred to as Patent Document 1) discloses a method for manufacturing a semiconductor device having an insulated-gate bipolar transistor and a diode. Hereinafter, an insulated-gate bipolar transistor is sometimes referred to as an IGBT (i.e., Insulated Gate Bipolar Transistor). Additionally, hereafter, a semiconductor device having an IGBT and a diode is sometimes referred to as an RC-IGBT. In the manufacturing method of Patent Document 1, an n-type cathode region is formed by ion implantation of n-type impurities. Then, crystal defects are formed in the cathode region by irradiating a semiconductor substrate with helium ions. By forming crystal defects in the cathode region, snapback can be suppressed when the IGBT is turned on. Summary of the Invention

[0004] When the applied voltage to the diode switches from forward to reverse, the holes present inside the diode are expelled to the anode electrode. This causes the recovery current to flow in the diode in the reverse direction. In the RC-IGBT of Patent Document 1, the crystal defects in the cathode region function as recombination centers. Therefore, during recovery, holes disappear through recombination at the crystal defects, and the recovery current decays earlier. This reduces the diode's recovery loss.

[0005] There are situations where the applied voltage to a diode changes rapidly. When the applied voltage to a diode switches rapidly from a forward voltage to a reverse voltage, surge voltages can sometimes occur due to the excessively rapid decay of the recovery current. If crystal defects exist in the cathode region, the recovery current decays easily, thus easily generating surge voltages.

[0006] As explained above, the presence of crystal defects in the cathode region can reduce recovery losses; however, surge voltages are easily generated under rapidly changing voltage conditions. This specification proposes techniques for reducing recovery losses and suppressing surge voltages in RC-IGBTs.

[0007] The semiconductor device disclosed in this specification includes: a semiconductor substrate having an IGBT region and a diode region; an upper electrode, connected to the upper surface of the semiconductor substrate within the IGBT region and the diode region; a lower electrode, connected to the lower surface of the semiconductor substrate within the IGBT region and the diode region; and a gate. The semiconductor substrate has an emitter region, an upper p-type region, a drift region, a field-stop region, a collector region, multiple cathode regions, and multiple surge suppression regions. The emitter region is an n-type region connected to the upper electrode within the IGBT region. The upper p-type region is distributed across the IGBT region and the diode region, and is connected to the upper electrode within the IGBT region and the diode region. The drift region is disposed below the upper p-type region, distributed across the IGBT region and the diode region, and is an n-type region separated from the emitter region by the upper p-type region. The field cutoff region is an n-type region, disposed below the drift region, and has a higher n-type impurity concentration than the drift region. It exhibits a ridge-shaped distribution of n-type impurity concentration along the thickness direction of the semiconductor substrate, spanning the IGBT region and the diode region. The collector region is a p-type region, disposed within the IGBT region and below the field cutoff region, connected to the lower electrode. Multiple cathode regions are n-type regions, disposed within the diode region and below the field cutoff region, connected to the lower electrode. Multiple surge suppression regions are p-type regions, disposed within the diode region and below the field cutoff region, connected to the lower electrode. The gate is separated from the upper p-type region between the emitter region and the drift region by a gate insulating film. Within the diode region, multiple cathode regions and multiple surge suppression regions are alternately arranged along a specific direction on the lower surface of the semiconductor substrate. Each of the cathode regions has: a first cathode region, connected to the lower electrode, having a size of 1×10 19 cm -3 The above-mentioned n-type impurity concentration; and a second cathode region, disposed between the first cathode region and the field cutoff region, wherein the activation rate of the n-type impurities is 85% or less.

[0008] Furthermore, in this specification, the upper p-type region can be any p-type region as long as it is distributed across the IGBT region and the diode region and is connected to the upper electrode within both the IGBT region and the diode region. For example, the concentration distribution of p-type impurities in the upper p-type region within the IGBT region and the upper p-type region within the diode region can be equal or different.

[0009] In this semiconductor device, the upper electrode functions as the emitter of the IGBT and the anode of the diode. The lower electrode functions as the collector of the IGBT and the cathode of the diode. The cathode region includes a first cathode region and a second cathode region. The first cathode region has a size of 1×102 19 cm -3 The above-mentioned n-type impurity concentration results in a low contact resistance between the first cathode region and the lower electrode. Therefore, losses are less likely to occur when the diode is turned on. Furthermore, the activation rate of n-type impurities in the second cathode region is below 85%, resulting in a large number of unactivated n-type impurities. These unactivated n-type impurities in the second cathode region constitute crystal defects and thus function as recombination centers for holes. Additionally, a p-type surge suppression region is arranged next to the cathode region within the diode region. When the applied voltage to the diode rapidly switches from forward to reverse, a recovery current flows through the diode. The crystal defects in the second cathode region (i.e., unactivated n-type impurities) function to decay the recovery current. On the other hand, when the applied voltage to the diode rapidly switches from forward to reverse, holes are injected from the surge suppression region into the drift region. If holes are injected into the drift region in this way, the recovery current is difficult to decay. Therefore, when the applied voltage to the diode rapidly switches from forward to reverse, the rapid decay of the recovery current is suppressed, and the generation of surge voltage is suppressed. Furthermore, when the applied voltage to the diode switches from forward to reverse at a normal rate, almost no holes are injected from the surge suppression region to the drift region. Therefore, in this case, crystal defects in the second cathode region cause the recovery current to decay prematurely. Thus, recovery losses can be reduced. In this way, according to this semiconductor device, recovery losses can be reduced during normal recovery operation, and surge voltage can be suppressed when the applied voltage switches rapidly. Attached Figure Description

[0010] Figure 1 This is a cross-sectional view of the semiconductor device of Example 1.

[0011] Figure 2 It means Figure 1 A graph showing the distribution of impurity concentration at the location of line AA.

[0012] Figure 3 It means Figure 1 A graph showing the distribution of impurity concentration at the locations of the BB and CC lines.

[0013] Figure 4 This is a graph representing the recovery characteristics under the condition of slow voltage Vak switching speed.

[0014] Figure 5This is a graph representing the recovery characteristics under conditions of fast voltage (Vak) switching speed.

[0015] Figure 6 This is an explanatory diagram of the manufacturing process of the semiconductor device in Example 1.

[0016] Figure 7 This is an explanatory diagram of the manufacturing process of the semiconductor device in Example 1.

[0017] Figure 8 This is an explanatory diagram of the manufacturing process of the semiconductor device in Example 1.

[0018] Figure 9 This is an explanatory diagram of the manufacturing process of the semiconductor device in Example 1.

[0019] Figure 10 This is a graph showing the impurity concentration distribution at the location of the AA line in the semiconductor device of Example 2.

[0020] Figure 11 This is a graph showing the impurity concentration distribution at the locations of the BB line and CC line of the semiconductor device in Example 3. Detailed Implementation

[0021] According to one example disclosed in this specification, the second cathode region may have a mountain-shaped distribution in the n-type impurity concentration distribution along the thickness direction of the semiconductor substrate.

[0022] By increasing the concentration of n-type impurities in the second cathode region, the activation rate in the second cathode region can be further reduced. Therefore, recovery loss can be suppressed more effectively.

[0023] It is possible that the mountain-shaped distribution within the second cathode region has a ratio of 1×10 18 cm -3 Higher and than 1×10 19 cm -3 Low peak value.

[0024] Any of the aforementioned semiconductor devices can be manufactured using the following method. This method may include an ion implantation step and a laser irradiation step. In the ion implantation step, p-type and n-type impurities are ion implanted into the lower surface of the semiconductor substrate to form the collector region, the cathode region, and the surge suppression region. In the laser irradiation step, after the formation of the collector region, the cathode region, and the surge suppression region, a laser is irradiated onto the lower surface of the semiconductor substrate. In the laser irradiation step, a heating zone of 950°C or higher can be formed in the surface layer near the lower surface of the semiconductor substrate. The thickness of the heating zone can be thinner than the thickness of the cathode region.

[0025] According to this manufacturing method, the activation rate of n-type impurities in the second cathode region can be reduced.

[0026] Example 1 Figure 1 The semiconductor device 10 of Embodiment 1 shown has a semiconductor substrate 12. The semiconductor substrate 12 is made of silicon. However, the semiconductor substrate 12 may also be made of a semiconductor material other than silicon. The semiconductor substrate 12 has an IGBT region 30 and a diode region 40. An IGBT is provided in the IGBT region 30, and a diode is provided in the diode region 40. That is, the semiconductor device 10 is an RC-IGBT.

[0027] Multiple trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 14 extends parallel to the others on the upper surface 12a. Multiple trenches 14 are also provided in the IGBT region 30 and the diode region 40. The inner surface of each trench 14 is covered by a gate insulating film 18. An electrode 16 is disposed within each trench 14. Each electrode 16 is insulated from the semiconductor substrate 12 by the gate insulating film 18. The electrode 16 in the IGBT region 30 is a gate 16a. Each gate 16a is connected to a gate pad (not shown). The gate pad is connected to an external circuit. The potential of each gate 16a is controlled by the external circuit. The electrode 16 in the diode region 40 is a dummy electrode 16b. Each dummy electrode 16b may be connected to a gate pad or may not be connected to a gate pad but connected to other electrodes (e.g., the upper electrode 22). When each dummy electrode 16b is connected to a gate pad, each dummy electrode 16b has the same potential as the gate 16a. When each dummy electrode 16b is not connected to the gate pad, the potential of each dummy electrode 16b is independent of the gate 16a.

[0028] An interlayer insulating film 20 and an upper electrode 22 are provided on the upper part of the semiconductor substrate 12. The interlayer insulating film 20 covers the upper surface of the gate electrode 16a and the dummy electrode 16b. A plurality of contact holes 20a are provided in the interlayer insulating film 20. Each contact hole 20a is disposed at a position where there is no trench 14. A plurality of contact holes 20a are provided in the IGBT region 30 and the diode region 40, respectively. The upper electrode 22 covers the interlayer insulating film 20 and the upper surface 12a of the semiconductor substrate 12. The upper electrode 22 is in contact with the upper surface 12a of the semiconductor substrate 12 in each contact hole 20a. Therefore, the upper electrode 22 is in contact with the upper surface 12a in the IGBT region 30 and the diode region 40, respectively.

[0029] A lower electrode 24 is provided at the bottom of the semiconductor substrate 12. The lower electrode 24 covers the entire area of ​​the lower surface 12b of the semiconductor substrate 12. Therefore, the lower electrode 24 is connected to the lower surface 12b in the IGBT region 30 and the diode region 40, respectively.

[0030] Multiple n-type emitter regions 52 are provided within the IGBT region 30. Each emitter region 52 has a high n-type impurity concentration. Each emitter region 52 is disposed in the region between trenches 14 (hereinafter referred to as the inter-trench region). The arrangement range of each emitter region 52 includes the upper surface 12a of the semiconductor substrate 12. Each emitter region 52 makes ohmic contact with the upper electrode 22 at the corresponding contact hole 20a. Each emitter region 52 is connected to the gate insulating film 18 at the upper end of the side of the corresponding trench 14.

[0031] An upper p-type region is provided across the IGBT region 30 and the diode region 40. Hereinafter, the upper p-type region in the IGBT region 30 will be referred to as the body region 54, and the upper p-type region in the diode region 40 will be referred to as the anode region 56. The upper p-type region is connected to the upper electrode 22 at each contact hole 20a in the IGBT region 30 and the diode region 40.

[0032] Body region 54 has a low-concentration region 54b and multiple contact regions 54a. Each contact region 54a has a higher p-type impurity concentration than the low-concentration region 54b. Each contact region 54a is disposed in a corresponding inter-trench region. The disposed area of ​​each contact region 54a includes the upper surface 12a of the semiconductor substrate 12. Each contact region 54a makes ohmic contact with the upper electrode 22 at a corresponding contact hole 20a. The low-concentration region 54b is distributed across multiple inter-trench regions. The low-concentration region 54b is disposed below the contact regions 54a and the emitter region 52. Each emitter region 52 is separated from the drift region 58 (described later) by the low-concentration region 54b. The low-concentration region 54b is in contact with the gate insulating film 18 below each emitter region 52. Each gate 16a is opposite the low-concentration region 54b between the emitter region 52 and the drift region 58 through the gate insulating film 18.

[0033] The anode region 56 has a low-concentration region 56b and multiple contact regions 56a. Each contact region 56a has a higher p-type impurity concentration than the low-concentration region 56b. Each contact region 56a is disposed in a corresponding inter-trench region. The disposal area of ​​each contact region 56a includes the upper surface 12a of the semiconductor substrate 12. Each contact region 56a makes ohmic contact with the upper electrode 22 at a corresponding contact hole 20a. The low-concentration region 56b is distributed across multiple inter-trench regions. The low-concentration region 56b is disposed below the contact region 54a.

[0034] An n-type drift region 58 is provided below the upper p-type region (i.e., body region 54 and anode region 56). The n-type impurity concentration in drift region 58 is low. Drift region 58 is distributed across IGBT region 30 and diode region 40. Drift region 58 is connected to body region 54 and anode region 56 from below. Drift region 58 is connected to gate insulating film 18 below body region 54 and anode region 56.

[0035] A field stop region 60 is provided below the drift region 58. The field stop region 60 is an n-type region with a higher n-type impurity concentration than the drift region 58. The field stop region 60 is distributed across the IGBT region 30 and the diode region 40. The field stop region 60 is connected to the drift region 58 from below.

[0036] Within the IGBT region 30, an intermediate n-type region 62 and a collector region 64 are disposed below the field-off region 60. The collector region 64 is a p-type region with a high p-type impurity concentration. The collector region 64 is positioned over the lower surface 12b of the semiconductor substrate 12 and has an ohmic contact with the lower electrode 24. The intermediate n-type region 62 is an n-type region with the same n-type impurity concentration as the drift region 58. Within the IGBT region 30, the intermediate n-type region 62 is disposed between the field-off region 60 and the collector region 64.

[0037] Within the diode region 40, a plurality of intermediate n-type regions 62, a plurality of cathode regions 66, and a plurality of surge suppression regions 70 are disposed below the field cutoff region 60. Each cathode region 66 is an n-type region with a higher n-type impurity concentration than the drift region 58. The arrangement range of each cathode region 66 includes the lower surface 12b of the semiconductor substrate 12. Each surge suppression region 70 is a p-type region with a higher p-type impurity concentration. The p-type impurity concentration of each surge suppression region 70 is approximately equal to the p-type impurity concentration of the collector region 64. The arrangement range of each surge suppression region 70 includes the lower surface 12b of the semiconductor substrate 12. Within the diode region 40, on the lower surface 12b of the semiconductor substrate 12, along a specific direction (in... Figure 1 Multiple cathode regions 66 and multiple surge suppression regions 70 are alternately arranged in a direction orthogonal to each trench 14. Each cathode region 66 and each surge suppression region 70 is in ohmic contact with the lower electrode 24. Within the diode region 40, the intermediate n-type region 62 is disposed between the field cutoff region 60 and the surge suppression region 70.

[0038] Each cathode region 66 has a 1×10 19 cm -3 The first cathode region 66a with the above-mentioned n-type impurity concentration and having a concentration of less than 1×10 19 cm -3 The second cathode region 66b has an n-type impurity concentration. The first cathode region 66a is configured to include the lower surface 12b of the semiconductor substrate 12. The first cathode region 66a is in ohmic contact with the lower electrode 24. The second cathode region 66b is disposed between the first cathode region 66a and the field cutoff region 60. The second cathode region 66b is connected to the field cutoff region 60 from below and to the first cathode region 66a from above.

[0039] Next, the impurity concentration distribution in the drift region 58, the field cutoff region 60, the intermediate n-type region 62, the collector region 64, the cathode region 66, and the surge suppression region 70 will be explained. Figure 2 yes Figure 1 The impurity concentration distribution at line AA, Figure 3 yes Figure 1 The impurity concentration distribution at the BB and CC lines is shown. Furthermore, the impurity concentration distributions at the BB and CC lines are approximately equal. Figure 2 , Figure 3 In the diagram, the horizontal axis represents the position along the thickness of the semiconductor substrate, with the origin corresponding to the position of the lower surface 12b. Additionally, in... Figure 2 , Figure 3 In the diagram, curve N represents the concentration distribution of n-type impurities, and curve P represents the concentration distribution of p-type impurities.

[0040] like Figure 2 , Figure 3 As shown, within the drift region 58, the concentration of n-type impurities is distributed approximately uniformly at a low value.

[0041] like Figure 2 , Figure 3 As shown, within the field-stop region 60, the n-type impurity concentration forms a ridge-shaped distribution M1 along the thickness direction of the semiconductor substrate 12. That is, the region where the ridge-shaped distribution M1 along the thickness direction continuously exists from the IGBT region 30 to the diode region 40 is the field-stop region 60. The peak value of the n-type impurity concentration within the field-stop region 60 is less than 1 × 10⁻⁶. 19 cm -3 .

[0042] like Figure 2 As shown, within the first cathode region 66a, the concentration of n-type impurities is 1×10⁻⁶. 19 cm -3 The above. Within the first cathode region 66a, the concentration of n-type impurities is at a relatively high value (e.g., Figure 2 The middle is 1×10 20 cm -3 The n-type impurities are distributed approximately at a constant level (left to right). In other words, within the first cathode region 66a, the n-type impurities are distributed in a box profile. The second cathode region 66b is the n-type region between the field cutoff region 60 and the first cathode region 66a. The concentration of n-type impurities in the second cathode region 66b is higher than the concentration of n-type impurities at the lower end 60L of the field cutoff region 60 and less than 1 × 10⁻⁶. 19 cm -3 . Figure 2 In the second cathode region 66b, the concentration of n-type impurities increases continuously from the top to the bottom.

[0043] like Figure 3As shown, within the intermediate n-type region 62, collector region 64, and surge suppression region 70, the n-type impurity concentration is uniformly distributed at the same level as in the drift region 58. Within collector region 64 and surge suppression region 70, the p-type impurity concentration is higher than the n-type impurity concentration. Within collector region 64 and surge suppression region 70, p-type impurities are distributed with a box-shaped profile.

[0044] Figure 2 Curve X represents the concentration distribution of activated n-type impurities. That is, curve N represents the concentration distribution of n-type impurities after combining activated and unactivated n-type impurities, while curve X represents the concentration distribution of activated n-type impurities. Furthermore, the value shown by curve X (i.e., the concentration of activated n-type impurities) is a value calculated based on the measurement of the resistance distribution in the semiconductor substrate 12 along the thickness direction. The difference between curve N and curve X corresponds to the concentration of unactivated n-type impurities. Figure 2 As shown, the difference between curve N and curve X is large within the second cathode region 66b. The activation rate of n-type impurities within the second cathode region 66b is below 85%. Furthermore, in this specification, the activation rate refers to the value obtained by dividing the total amount of activated n-type impurities in the target region by the total amount of n-type impurities present in the target region. For example, the activation rate within the second cathode region 66b can be calculated by dividing the value obtained by integrating curve X within the second cathode region 66b by integrating curve N within the second cathode region 66b. Because the activation rate of n-type impurities is low within the second cathode region 66b, unactivated n-type impurities exist at a high concentration within the second cathode region 66b. Unactivated impurities in the semiconductor substrate 12 are a type of crystal defect and function as recombination centers for charge carriers. Therefore, the carrier lifetime is short within the second cathode region 66b. Figure 2 As shown, the activation rate of n-type impurities is higher in the first cathode region 66a than in the second cathode region 66b. For example, the activation rate of n-type impurities in the first cathode region 66a can be higher than 85%.

[0045] Next, the operation of the semiconductor device 10 will be explained. The upper electrode 22 functions as the emitter of the IGBT and as the anode of the diode. The lower electrode 24 functions as the collector of the IGBT and as the cathode of the diode.

[0046] When the semiconductor device 10 operates as an IGBT, a higher potential than that of the upper electrode 22 is applied to the lower electrode 24. When a potential above the gate threshold is applied to the gate 16a, a channel is formed in the low-concentration region 54b adjacent to the gate insulating film 18, connecting the emitter region 52 and the drift region 58 through the channel. Therefore, the IGBT is turned on, and electrons flow from the emitter region 52 into the drift region 58 via the channel. Furthermore, when the IGBT is turned on, holes flow from the collector region 64 into the drift region 58. As a result, the resistance of the drift region 58 decreases, and electrons flow within the drift region 58 with low resistance. After passing through the drift region 58, the electrons flow to the collector region 64.

[0047] In an RC-IGBT, when the IGBT is initially turned on (i.e., when the channel resistance is high), electrons flow from the drift region 58 to the cathode region 66. In this state, the IGBT's on-state voltage is high. Subsequently, as the channel resistance decreases, electrons flow from the drift region 58 to the collector region 64, and the IGBT's on-state voltage decreases. This phenomenon of a temporary increase in on-state voltage at the start of turn-on is called snapback. In the semiconductor device of Embodiment 1, the cathode region 66 and the surge suppression region 70 are alternately provided within the diode region 40, and the area ratio of the cathode region 66 at the lower surface 12b is low. Therefore, when the IGBT is turned on, it is difficult for electrons to flow from the drift region 58 to the cathode region 66. This suppresses snapback.

[0048] When the semiconductor device 10 operates as a diode, a higher potential is applied to the upper electrode 22 than to the lower electrode 24. In this state, electrons flow from the cathode region 66 to the drift region 58. Furthermore, holes flow from the anode region 56 to the drift region 58. As a result, the resistance of the drift region 58 decreases, allowing electrons to flow within it with lower resistance. After passing through the drift region 58, the electrons flow towards the anode region 56. The holes flow towards the cathode region 66 after passing through the drift region 58.

[0049] When the semiconductor device 10 is operating as a diode, the voltage Vak between the upper electrode 22 and the lower electrode 24 sometimes switches from a forward voltage (i.e., a voltage where the potential of the upper electrode 22 is higher than the potential of the lower electrode 24) to a reverse voltage (i.e., a voltage where the potential of the lower electrode 24 is higher than the potential of the upper electrode 22). When the voltage Vak switches in this way, the diode performs a recovery operation. During the diode's recovery operation, holes present in the drift region 58, the field cutoff region 60, and the cathode region 66 are discharged to the upper electrode 22 via the anode region 56. As these holes flow, a reverse current (so-called recovery current) flows instantaneously through the diode. By allowing the recovery current to decay early, recovery losses can be suppressed. On the other hand, if the decay rate of the recovery current is too fast, a surge voltage is generated along with the rapid change in the recovery current. In the semiconductor device of Embodiment 1, the diode's operation changes depending on whether the voltage Vak switching speed is fast or slow, thereby achieving both a reduction in recovery losses and suppression of surges. The operation of the semiconductor device in Example 1 will be described below for both slow and fast voltage Vak switching speeds.

[0050] (Slow voltage switching speed) Figure 4 The recovery characteristics of the diode of Example 1 and the diode of Comparative Example 1 are compared and presented when the switching speed of voltage Vak is slow. The diode of Comparative Example 1 differs from the diode of Example 1 in that the activation rate of the n-type impurity in the second cathode region 66b is high. Figure 4 In the above, the high potential of the cathode (i.e., the lower electrode 24) is set as positive, and the voltage Vak is represented. Figure 4 In the examples, the voltage Vak curves overlap in Example 1 and Comparative Example 1. Figure 4 In the middle, the current I F This indicates the current flowing through the diode. A positive value indicates the current flowing in the forward direction, and a negative value indicates the current flowing in the reverse direction.

[0051] exist Figure 4 In the middle, the current I FWhen the value is negative, it is in the recovery state. In the recovery state, holes present in the drift region 58, the field cutoff region 60, and the cathode region 66 are discharged to the upper electrode 22 via the anode region 56. Holes present closer to the anode region 56 are more easily discharged to the upper electrode 22. Therefore, it takes time for holes present in the cathode region 66 to be discharged to the upper electrode 22. In the diode of Comparative Example 1, since the recovery current flows until the holes present in the cathode region 66 are discharged to the upper electrode 22, the recovery current is difficult to decay. In contrast, in the diode of Example 1, since the activation rate of the n-type impurities in the second cathode region 66b is low, the carrier lifetime in the second cathode region 66b is short. Therefore, in the second cathode region 66b, a large number of holes disappear due to recombination with electrons. Therefore, in the diode of Example 1, the recovery current decays faster than in the diode of Comparative Example 1. Therefore, in the diode of Example 1, recovery losses are less likely to occur. Furthermore, the surge suppression region 70 has almost no effect on the characteristics of the diode when the voltage Vak switching speed is slow.

[0052] (When the voltage Vak switches quickly) Figure 5 The recovery characteristics of the diode of Example 1 and the diode of Comparative Example 2 are compared and presented when the voltage Vak switching speed is fast. In the diode of Comparative Example 2, similar to the diode of Example 1, the activation rate of n-type impurities in the second cathode region 66b is low. The diode of Comparative Example 2 differs from the diode of Example 1 in that it does not have a surge suppression region 70.

[0053] In the diode of Comparative Example 2, the recovery current easily decays because the activation rate of the n-type impurities in the second cathode region 66b is low. Therefore, when the switching speed of voltage Vak is fast, such as Figure 5 As shown, the decay rate of the recovery current becomes extremely fast. Consequently, due to the parasitic inductance of the circuit, a surge voltage Vs is generated during recovery operation. On the other hand, in the diode of Embodiment 1, when the switching speed of voltage Vak is fast, holes flow from the surge suppression region 70 into the drift region 58. Because holes flow into the drift region 58, the decay rate of the recovery current slows down. Therefore, as... Figure 5 As shown, this prevents the recovery current from decaying too quickly and suppresses surge voltage.

[0054] As explained above, in the semiconductor device of Embodiment 1, when the voltage Vak switching speed is slow, the second cathode region 66b promotes the attenuation of the recovery current, thereby reducing recovery losses. Furthermore, in the semiconductor device of Embodiment 1, when the voltage Vak switching speed is fast, the surge suppression region 70 prevents the recovery current from attenuating too quickly, thus suppressing surge voltage.

[0055] Next, the manufacturing method of the semiconductor device 10 will be described. First, as... Figure 6 As shown, the upper surface side of the semiconductor device 10 is structured with a field cutoff region 60. Next, as... Figure 7 As shown, a p-type region 72 is formed in the surface layer near the lower surface 12b by implanting p-type impurities into the entire region of the lower surface 12b of the semiconductor substrate 12. The p-type region 72 corresponds to the p-type region of the collector region 64 and the surge suppression region 70. Next, as... Figure 8 As shown, an n-type impurity is injected into a portion of the lower surface 12b (i.e., the area corresponding to the cathode region 66) at a higher concentration than the p-type impurity concentration in the p-type region 72, thereby forming the cathode region 66. Here, the cathode region 66 is made thicker than the p-type region 72. The p-type region 72 remaining after the formation of the cathode region 66 becomes the collector region 64 and the surge suppression region 70.

[0056] Next, as Figure 9 As shown, laser L is irradiated in a manner that scans the entire lower surface 12b of the semiconductor substrate 12, thereby heating the lower surface 12b of the semiconductor substrate 12. In this embodiment, a green laser with a wavelength of 532 nm is used as laser L. By irradiating with laser L, the surface portion near the lower surface 12b of the semiconductor substrate 12 is heated to a temperature of 950°C or higher. Hereinafter, the range of temperatures heated to 950°C or higher by irradiation with laser L will be referred to as the heating range 94. Within the heating range 94, the semiconductor substrate 12 temporarily melts. When the semiconductor substrate 12 temporarily melts, impurities diffuse uniformly within the heating range 94. As a result, as Figures 1-3 As shown, a first cathode region 66a, a surge suppression region 70, and a current collector region 64 with a box-shaped profile are formed within the heating range 94. Here, the heating range 94 is controlled such that its thickness is thinner than that of the cathode region 66. Consequently, the portion of the cathode region 66 above the heating range 94 becomes a second cathode region 66b with a lower concentration of n-type impurities than the first cathode region 66a. Since the second cathode region 66b is not included within the heating range 94, the n-type impurities within the second cathode region 66b are difficult to activate. Therefore, a second cathode region 66b with a low activation rate is formed.

[0057] After the laser irradiation process, the lower electrode 24 is formed, thus completing the process. Figure 1 The semiconductor device shown. Because the first cathode region 66a, surge suppression region 70 and collector region 64 have high impurity concentrations, these regions contact the lower electrode 24 with low contact resistance.

[0058] In addition, Figure 2In the first cathode region 66a, the activation rate of n-type impurities is not very high because the concentration of n-type impurities in the first cathode region 66a is close to the solid solution limit. In contrast, in the second cathode region 66b, although the concentration of n-type impurities is not very high, the activation rate of n-type impurities is low. This is because the second cathode region 66b is not included in the heating range 94 during the laser irradiation process.

[0059] Example 2 Figure 10 The impurity concentration distribution at the location of the AA line in the semiconductor device of Example 2 is shown. In Example 2, a montage distribution M2 of n-type impurity concentration is formed within the second cathode region 66b. The peak value of the n-type impurity concentration in the montage distribution M2 is higher than 1 × 10⁻⁶. 18 cm -3 And less than 1×10 19 cm -3 The other structures of Example 2 are the same as those of Example 1. In the process of implanting n-type impurities into the cathode region 66, a mountain-shaped distribution M2 can be formed by locally implanting n-type impurities at a high concentration within the depth range of the second cathode region 66b.

[0060] If the mountain-shaped distribution M2 is formed as in Example 2, the concentration of n-type impurities in the second cathode region 66b becomes higher, further reducing the activation rate of n-type impurities in the second cathode region 66b. This further shortens the carrier lifetime in the second cathode region 66b. Consequently, the recovery loss of the diode can be suppressed more effectively.

[0061] Example 3 Figure 11 The impurity concentration distribution at the locations of the BB and CC lines of the semiconductor device of Embodiment 3 is shown. In Embodiment 3, the collector region 64 and the surge suppression region 70 have a mountain-shaped distribution M3 on the upper side of the box-shaped profile. The other structures of Embodiment 3 are the same as those of Embodiment 1. In the p-type impurity implantation process of the collector region 64 and the surge suppression region 70, the mountain-shaped distribution M3 can be formed by implanting p-type impurities in a manner that has a peak value at a position above the heating range 94. By forming the mountain-shaped distribution M3 in this way, the collector region 64 and the surge suppression region 70 can be made thicker than those of Embodiment 1. In Embodiment 1, the thickness of the collector region 64 and the surge suppression region 70 is the same as or thinner than that of the first cathode region 66a. However, according to Embodiment 3, the thickness of the collector region 64 and the surge suppression region 70 can be made thicker than that of the first cathode region 66a.

[0062] Furthermore, in the above embodiments 1 to 3, the gate of the IGBT is trench type, but the gate of the IGBT can also be planar type.

[0063] The embodiments have been described in detail above, but these are merely illustrative and do not limit the scope of the claims. The technology described in the claims includes technologies obtained by various modifications and alterations to the specific examples described above. The technical elements described in this specification or drawings are useful individually or in various combinations, and are not limited to the combinations described in the claims at the time of application. Furthermore, the technology illustrated in this specification or drawings achieves multiple objectives simultaneously, and achieving one of these objectives is itself technically useful.

Claims

1. A semiconductor device characterized by comprising: a semiconductor substrate (12) having an IGBT region (30) and a diode region (40); an upper electrode (22) that interfaces with an upper surface of the semiconductor substrate in the IGBT region and in the diode region; a lower electrode (24) that interfaces with a lower surface of the semiconductor substrate in the IGBT region and in the diode region; and a gate (16a) that opposes the upper p-type region between the emitter region and the drift region via a gate insulating film (18), the semiconductor substrate having: an emitter region (52) of n-type that interfaces with the upper electrode in the IGBT region; upper p-type regions (54, 56) that are distributed across the IGBT region and the diode region, that interface with the upper electrode in the IGBT region and in the diode region; a drift region (58) of n-type that is disposed on a lower side of the upper p-type regions, that is distributed across the IGBT region and the diode region, that is separated from the emitter region by the upper p-type regions; a field stop region (60) of n-type that is disposed on a lower side of the drift region, that has a higher n-type impurity concentration than the drift region, that has a mountain-shaped distribution (Ml) in an n-type impurity concentration distribution along a thickness direction of the semiconductor substrate, that is distributed across the IGBT region and the diode region; a collector region (64) of p-type that is disposed in the IGBT region, and that is disposed on a lower side of the field stop region, that interfaces with the lower electrode; a plurality of cathode regions (66) of n-type that are disposed in the diode region, and that are disposed on a lower side of the field stop region, that interface with the lower electrode; and a plurality of surge suppression regions (70) of p-type that are disposed in the diode region, and that are disposed on a lower side of the field stop region, that interface with the lower electrode, the gate opposing the upper p-type region between the emitter region and the drift region via the gate insulating film (18), in the diode region, a plurality of the cathode regions and a plurality of the surge suppression regions are alternately disposed on the lower surface of the semiconductor substrate along a certain direction, each of the cathode regions having: and The first cathode region (66a) has a n-type impurity concentration of 1 x 10 19 cm -3 above. a second cathode region (66b) that is disposed between the first cathode region and the field stop region, that has an activation rate of n-type impurities of 85% or less.

2. The semiconductor device according to claim 1, characterized in that, in the second cathode region, a mountain-shaped distribution (M2) is provided in an n-type impurity concentration distribution along a thickness direction of the semiconductor substrate.

3. The semiconductor device according to claim 2, characterized in that, 4. A manufacturing method of the semiconductor device according to any one of claims 1 to 3, characterized by comprising: The mountain-shaped distribution disposed within the second cathode region has a peak that is greater than 1 x 10 18 cm -3 and less than 1 x 10 19 cm -3 . a process of ion-implanting p-type impurities and n-type impurities into the lower surface of the semiconductor substrate to form the collector region, the cathode regions, and the surge suppression regions; and a process of irradiating a laser onto the lower surface of the semiconductor substrate after the formation of the collector region, the cathode regions, and the surge suppression regions, in the process of irradiating the laser, a heated range (94) of 950°C or more is formed in a surface layer portion in the vicinity of the lower surface of the semiconductor substrate, ​ ​ The heating range is thinner than the thickness of the cathode region. The heating range is thinner than the thickness of the cathode region.

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