Bit stream random number generator, random multiplication circuit and calculation method

Abstract

The invention discloses a bit stream random number generator, a random multiplication circuit and a calculation method, and belongs to the technical field of integrated circuits. A reverse signal end of a highest-bit D trigger Ln of a linear feedback shift register is respectively connected with a NOR gate and a NAND gate, and output signal ends of n-1 low-bit triggers in the linear feedback shift register are respectively connected with a comparator; a sign bit xn of an n-bit binary number corresponding to the target numerical value is input into the NOR gate and the NAND gate respectively; bits corresponding to the amplitude bits of the n-bit binary number are input to the comparator; the comparator and the NOR gate are connected with the OR gate; the OR gate and the NAND gate are connected with the AND gate. In the application, the two bit stream random number generators can generate two bit streams with low correlation, so that the numerical value shown by the bit stream obtained by carrying out multiplication (namely XNOR operation) on the two bit streams is closer to the product result of two target numerical values.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology and relates to a bitstream random number generator, a random multiplication circuit, and a calculation method. Background Technology

[0002] Randomized computation significantly reduces computational complexity by converting numerical values ​​into bitstreams and performing multiplication using logic gates, overcoming the limitations of power consumption and hardware resources inherent in traditional digital circuits. The paper "Gradient Descent Using Stochastic Circuits for Efficient Training of Learning Machines" discloses a method for converting the target numerical value x... * Existing methods for converting the target value x ∈ [-1,1] into a bitstream via mapping operations first convert the target value x ∈ [-1,1] into a bitstream. * Mapped to (x * +1) / 2, then (x * +1) / 2 is mapped to [0,1], and then converted into a random sequence using a random number generator (SNG). This random sequence is a bitstream. When multiplying two target values ​​using bitstreams generated in this way (e.g., XOR operation), the high correlation between the two bitstreams often leads to a large error between the resulting bitstream and the product of the two target values. Therefore, this application provides a bitstream random number generator, a random multiplication circuit, and a calculation method. Summary of the Invention

[0003] To address the shortcomings and deficiencies in the existing technology, this application proposes a bitstream random number generator, a random multiplication circuit, and a calculation method.

[0004] To achieve the above-mentioned objectives, the present invention adopts the following technical solution: A bitstream random number generator includes a comparator, a NOR gate, a NAND gate, an OR gate, and an AND gate, and a D flip-flop L in the highest bit of a linear feedback shift register. n Inverting signal terminal The first input terminals of the NOR gate and the first input terminals of the NAND gate are respectively connected to the output signal terminals of the n-1 low-order flip-flops in the linear feedback shift register. Separately with comparator (CMP) , … The ports are connected; an n-bit binary number (where n bits represent the target value) is divided into a sign bit and amplitude bits. The sign bit refers to the highest bit of the n-bit binary number represented by the target value, and the amplitude bits refer to the bits other than the highest bit in the n-bit binary number represented by the target value; the sign bit x of the n-bit binary number. n The sign bit x of an n-bit binary number is input to the second input terminal of the NOR gate. n The second input terminal of the NAND gate is used to input the bit corresponding to the amplitude bit of the n-bit binary number. , … respectively through comparators , … The port input is connected to the comparator; the output of the comparator is connected to the first input of the OR gate, and the output of the NOR gate is connected to the second input of the OR gate; the output of the OR gate is connected to the first input of the AND gate, and the output of the NAND gate is connected to the second input of the AND gate; the output of the AND gate is the output of the random number generator, and the bits output by the AND gate in all clock cycles are arranged in the timing order to form a bit stream.

[0005] Preferably, the feedback polynomial of the linear feedback shift register uses a primitive polynomial.

[0006] Preferably, the most significant bit D flip-flop L n This refers to the nth D flip-flop; the (n-1)th low-order flip-flop refers to the (n-1)th D flip-flop. The (n-2)th D flip-flop Up to the first D flip-flop .

[0007] Preferably, the sign bit refers to the highest bit of the n-bit binary number represented by the target value, and the amplitude bit refers to the other bits in the n-bit binary number represented by the target value, excluding the highest bit.

[0008] A method for calculating a random number generator, wherein the random number generator is the aforementioned bitstream random number generator; the method for calculating the random number generator includes the following steps: decomposing the binary number corresponding to the input target value into a sign bit and an amplitude bit; and comparing the output signal terminals of the comparator to the (n-1) low-order flip-flops (n-1 low-order flip-flops refer to the (n-1)th D flip-flop to the 1st D flip-flop) in the linear feedback shift register. The output result is compared with the corresponding bit of the amplitude bit to determine the numerical value; the NOR gate is used to connect the highest bit of the linear feedback shift register's D flip-flop L. n (The highest-order D flip-flop is the nth D flip-flop) inverting signal input The output result and the bit corresponding to the sign bit are subjected to a NOR operation. The NAND gate is used to operate on the highest bit of the linear feedback shift register's D flip-flop L.n Inverting signal terminal The output result and the bit corresponding to the sign bit are subjected to NAND logic operation. The output result of the NOR gate and the output result of the comparator are subjected to OR logic operation using an OR gate. The output result of the OR gate and the output result of the two-input NAND gate are subjected to AND logic operation using an AND gate. The output result of the AND gate is the output result of the bit stream random number generator. The bits output by the AND gate in all clock cycles are arranged in the timing order to form the bit stream.

[0009] Application of a bitstream random number generator in a multiplication circuit.

[0010] A random multiplication circuit based on a bitstream random number generator includes two bitstream random number generators. The outputs of the two bitstream random number generators are respectively connected to the two inputs of an XOR gate. The output of the XOR gate is the output of the random multiplication circuit. The bitstream formed by arranging the bits output by the random multiplication circuit in the timing sequence over all clock cycles corresponds to the target value x. * and target value y * The bit stream of the product result.

[0011] Preferably, the feedback polynomials of the linear feedback shift registers in the two bitstream random number generators are different.

[0012] Preferably, the linear feedback shift registers in the two bitstream random number generators have the same feedback polynomial, but the random seeds (i.e., initial states) of the two linear feedback shift registers are different.

[0013] A method for calculating a random multiplication circuit, wherein the random multiplication circuit is the aforementioned random multiplication circuit based on a bitstream random number generator; the method for calculating the random multiplication circuit includes the following steps: the outputs of two bitstream random number generators are logically operated through a XNOR gate; the bits output by the XNOR gate in all time periods are arranged in timing order to obtain the value corresponding to the target value x. * and target value y * The bit stream of the product result.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: This application decomposes the binary number corresponding to the input target value into a sign bit and an amplitude bit. The sign bit refers to the highest bit of the n-bit binary number represented by the target value, and the amplitude bit refers to the other bits in the n-bit binary number represented by the target value, excluding the highest bit. The comparator outputs signals to the (n-1) low-order flip-flops (n-1 low-order flip-flops refer to the (n-1)th D flip-flop to the 1st D flip-flop) in the linear feedback shift register. The output result is compared with the corresponding bit of the amplitude bit to determine its magnitude; while the OR gate compares the highest bit of the linear feedback shift register's D flip-flop L. n (The highest-order D flip-flop is the nth D flip-flop) inverting signal input The output result and the bit corresponding to the sign bit are subjected to a NOR operation. The NAND gate is used to operate on the highest bit of the linear feedback shift register's D flip-flop L. n Inverting signal terminal The output result and the bit corresponding to the sign bit are subjected to NAND logic operations. The output result of the NOR gate and the output result of the comparator are subjected to OR logic operations using an OR gate. The output result of the OR gate and the output result of the two-input NAND gate are subjected to AND logic operations using an AND gate. The output result of the AND gate is the output result of the bit stream random number generator. The bits output by the AND gate in all clock cycles are arranged in timing order to form the bit stream. The random number generator described in this application can directly generate bit streams, and this application directly uses the highest bit D flip-flop L of the linear feedback shift register. n Inverting signal terminal The output results eliminate the need for additional inverter design, effectively reducing the overhead of gate-level circuits, simplifying the circuit structure, and reducing circuit complexity and power consumption. In addition, tests show that the mean square error (MSE) of the bit stream represented by the random number generator described in this application relative to the target value is also low, indicating that the random number generator described in this application has high calculation accuracy. Furthermore, tests show that the bitstream random number generator described in this application can generate two bitstreams with low correlation before performing multiplication (i.e., XOR operation). This makes the value of the bitstream obtained by multiplying the two bitstreams (i.e., XOR operation) closer to the product of the two target values. In other words, it can reduce the error between the value of the bitstream obtained by multiplying the two bitstreams (i.e., XOR operation) and the product of the two target values. Furthermore, the random multiplication circuit based on a bitstream random number generator constructed in this application includes two bitstream random number generators. The output terminals of the two bitstream random number generators are respectively connected to the two input terminals of an XNOR gate. The XNOR gate performs an XNOR logic operation on the output results of the two bitstream random number generators, and outputs the value corresponding to the target value x. * and target value y * The bitstream representation of the product result; tests show that as the number of bits in the linear feedback shift register (LFSR) increases, the computational accuracy of the random multiplication circuit constructed in this application also increases. Attached Figure Description

[0015] Figure 1 This application discloses a bitstream random number generator; Figure 2 This application provides a random multiplication circuit based on a bitstream random number generator. Detailed Implementation

[0016] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings.

[0017] Example 1: A bitstream random number generator, such as Figure 1 As shown, Figure 1 In this application, an n-bit linear feedback shift register (LFSR) is used for the input signal, the target value represented by the n-bit binary number is also the input signal, and the output bit represents the output signal. The feedback polynomial of the LFSR uses a primitive polynomial. A LFSR using a primitive polynomial can traverse all 2^n bits except when the register output is all zero. N -1 different register states. In this application, N represents the number of bits in the linear feedback shift register, and the value of N is equal to the value of n. The bitstream random number generator includes a comparator (CMP), a NOR gate, a NAND gate, an OR gate, and an AND gate. The highest bit of the linear feedback shift register (LFSR) is a D flip-flop L. n Inverting signal terminal Connect the first input terminals of the NOR gate and the NAND gate respectively, where the most significant bit of the D flip-flop L... n That is, the nth D flip-flop. In a linear feedback shift register (LFSR), the (n-1)th low-order flip-flops are the (n-1)th D flip-flops. The (n-2)th D flip-flop Up to the first D flip-flop 'output signal terminal' Separately with comparator (CMP) , … The ports are connected, and an n-bit binary number (where n bits represent the target value) is divided into a sign bit and amplitude bits. The sign bit refers to the highest bit of the n-bit binary number represented by the target value, and the amplitude bits refer to the bits other than the highest bit in the n-bit binary number represented by the target value. The sign bit x of the n-bit binary number... n The sign bit x of an n-bit binary number is input to the second input terminal of the NOR gate. n The second input terminal of the NAND gate is used to input the bit corresponding to the amplitude bit of the n-bit binary number. , … respectively through comparators , … The port input is connected to the comparator; the output of the comparator is connected to the first input of the OR gate, and the output of the NOR gate is connected to the second input of the OR gate; the output of the OR gate is connected to the first input of the AND gate, and the output of the NAND gate is connected to the second input of the AND gate; the output of the AND gate is the output of the random number generator, and the bits output by the AND gate in all clock cycles are arranged in the timing order to form a bit stream.

[0018] In this application, the linear feedback shift register (LFSR) outputs an N-bit binary number in each clock cycle, and the comparator activates the low-order flip-flops in the linear feedback shift register. , … 'output signal terminal' The output result and the bits corresponding to the amplitude bits of the n-bit binary number. , … The comparison is performed; the NOR gate then applies the highest-order D flip-flop L of the linear feedback shift register. n Inverting signal terminal The output result and the bit corresponding to the sign bit are subjected to a NOR operation. The NAND gate is used to operate on the highest bit of the linear feedback shift register's D flip-flop L. n Inverting signal terminal The output result and the bit corresponding to the sign bit are subjected to NAND logic operations. The output result of the NOR gate and the output result of the comparator are subjected to OR logic operations using an OR gate. The output result of the OR gate and the output result of the two-input NAND gate are subjected to AND logic operations using an AND gate. The output result of the AND gate is the output result of the bit stream random number generator. The bits output by the AND gate in all clock cycles are arranged in timing order to form a bit stream. The bit stream random number generator described in this application can generate random numbers for x. * A bitstream can be generated from values ​​∈ [0,1], and x can be used to generate bitstreams. * Generate a bit stream of values ​​∈ [-1,0].

[0019] In this embodiment, a total of 2 N -1 clock cycle, the linear feedback shift register LFSR will output 2 N -1 different states, these 2 N During one clock cycle, the comparator will test the low-order flip-flops in the linear feedback shift register LFSR. , … 'output signal terminal' The output result and the bits corresponding to the amplitude bits of the n-bit binary number. , … A comparison is then made. Therefore, the bits output by the AND gate in all clock cycles, arranged in timing order, constitute a bitstream of length 2. N -1, the bitstream contains B bits "1" and (2 N -1)-B bits "0"; the value corresponding to the generated bipolar bit can be expressed as (number of "1" bits in the bipolar bit - number of "0" bits) / total length of the bitstream, i.e. This value is approximately equal to the target value x. * .

[0020] In this application, both the target value and the output of the linear shift register LFSR are represented using n-bit two's complement. In the two's complement representation, the two's complement of a positive number is the same as its original code, while the two's complement of a negative number is obtained by inverting the binary representation and adding 1. During the bit generation process in all clock cycles, the above random number generator exhibits the following four different cases: Case (1): When the output of the linear feedback shift register is L in a certain clock cycle, the value represented by the n-bit binary number X is the target value, and both the value represented by L and the target value are positive, the highest bit D flip-flop L of the linear feedback shift register... n When the output signal terminal Q outputs bit 0, that is, the most significant bit of L is 0, the most significant bit of the D flip-flop L in the linear feedback shift register is 0. n Inverting signal terminal Output a binary number with 1 bit and n bits. highest position At this point, the input signals to the NOR gate are n-bit binary numbers. highest position And the highest bit D flip-flop L in the linear feedback shift register n Inverting signal terminal The output bit is 1; therefore, after the NOR gate's logical operation, the NOR gate outputs bit 0; while the NAND gate's input signals are n-bit binary numbers. highest position And the highest bit D flip-flop L in the linear feedback shift register n Inverting signal terminal The output bit is 1. Therefore, after the NAND gate logic operation, the NAND gate outputs bit 1. The comparator is used to operate the low-order D flip-flops in the linear feedback shift register (LFSR). , … 'output signal terminal' The output signal and the bits corresponding to the amplitude bits of the n-bit binary number , … Compare them separately; If the amplitude bits of an n-bit binary number X correspond to the bits... , … Greater than the low-order D flip-flop , … 'output signal terminal' If the output signal is a bit 1, the comparator outputs bit 1. At this time, the OR gate performs a logical operation on the bit 1 output by the comparator and the 0 output by the NOR gate, and outputs bit 1. The AND gate performs a logical operation on the bit 1 output by the OR gate and the bit 1 output by the NAND gate, and outputs bit 1. If the amplitude bits of an n-bit binary number X correspond to the bits... , … Less than the low-order D flip-flop , … 'output signal terminal' The output signal is as follows: the comparator outputs bit 0; the OR gate performs a logical operation on bit 0 output by the comparator and bit 0 output by the NOR gate, and outputs bit 0; the AND gate performs a logical operation on bit 0 output by the OR gate and bit 1 output by the NAND gate, and outputs 0. Case (II): When the output of the linear feedback shift register in a certain clock cycle is L, the value represented by the n-bit binary number X is the target value, and the value represented by L is positive and X is negative, the highest bit D flip-flop L of the linear feedback shift register... n When the output signal terminal Q outputs bit 0, that is, the most significant bit of L is 0, the most significant bit of the D flip-flop L in the linear feedback shift register is 0. n Inverting signal terminal Output bit 1, the most significant bit of the n-bit binary number X. Since the input signals of the NAND gate are n-bit binary numbers... highest position And the highest bit D flip-flop L in the linear feedback shift register n Inverting signal terminal The output bit is 1. Therefore, after the NAND gate logic operation, the NAND gate output bit is 0. Since one input of the AND gate is 0, the other input of the AND gate is no longer affected by the comparator output result, that is, the final output bit of the AND gate is 0. Case (3): When the output of the linear feedback shift register is L in a certain clock cycle, the value represented by the n-bit binary number X is the target value, the value represented by L is negative, and the target value is positive, the highest bit D flip-flop L of the linear feedback shift register... n The output signal terminal Q outputs bit 1, meaning the most significant bit of L is 1. This sets the most significant bit of the linear feedback shift register's D flip-flop L to 1. n Inverting signal terminal Output bit 0, and n-bit binary number highest position At this point, the input signals to the NOR gate are n-bit binary numbers. highest position And the highest bit D flip-flop L in the linear feedback shift register n Inverting signal terminal Since the output bit is 0, after the NOR gate logic operation, the NOR gate outputs bit 1. Since one of the inputs of the OR gate is the bit 1 output by the NOR gate, the other input of the OR gate, which is the output of the comparator, will output bit 1 after the OR gate logic operation, regardless of whether the output of the comparator is 1 or 0. In other words, the output result of the OR gate is not affected by the output result of the comparator, and the output result of the OR gate is bit 1. The input signals of the NAND gate are n-bit binary numbers. highest position And the highest bit D flip-flop L in the linear feedback shift register n Inverting signal terminal The output bit is 0. Therefore, after the NAND gate logic operation, the NAND gate output bit is 1. After performing logical operations on bit 1 output by the AND gate, the OR gate, and the NAND gate, bit 1 is output.

[0021] Case (iv): When the output of the linear feedback shift register is L in a certain clock cycle, the value represented by the n-bit binary number X is the target value, and both the value represented by L and the target value are negative, the highest bit D flip-flop L of the linear feedback shift register... n The output signal terminal Q outputs bit 1, meaning the most significant bit of L is 1. This sets the most significant bit of the linear feedback shift register's D flip-flop L to 1. n Inverting signal terminal The output bit is 0, an n-bit binary number. highest position At this point, the input signals to the NOR gate are n-bit binary numbers. highest position And the highest bit D flip-flop L in the linear feedback shift register n Inverting signal terminal The output bit is 0; therefore, after the NOR gate's logical operation, the NOR gate outputs bit 0. The NAND gate's input signals are n-bit binary numbers. highest position And the highest bit D flip-flop L in the linear feedback shift register n Inverting signal terminal The output bit is 0. Therefore, after the NAND gate logic operation, the NAND gate output bit is 1. The comparator is used to operate the low-order D flip-flops in the linear feedback shift register (LFSR). , … 'output signal terminal' The output signal corresponds to the amplitude bits of the n-bit binary number. , … Compare them separately; If the amplitude bits of an n-bit binary number X correspond to the bits... , … Greater than the low-order D flip-flop , … 'output signal terminal' The comparator outputs bit 1 when the output signal is given. At this time, the OR gate performs a logical operation on bit 1 output by the comparator and bit 0 output by the NOR gate, and outputs bit 1 after performing a logical operation on bit 1 output by the OR gate and bit 1 output by the NAND gate. If the amplitude bits of an n-bit binary number X correspond to the bits... , … Less than the low-order D flip-flop , … 'output signal terminal' If the output signal is zero, the comparator outputs bit 0. At this time, the OR gate performs a logical operation on bit 0 output by the comparator and bit 0 output by the NOR gate, and outputs bit 0. The AND gate performs a logical operation on bit 0 output by the OR gate and bit 1 output by the NAND gate, and outputs bit 0.

[0022] (1) One specific example of using the random number generator described in Example 1 to output a bit stream is referred to as Example 1, and is as follows: In the specific example, the feedback polynomial of the four-bit linear feedback shift register is a four-bit primitive polynomial, P(x) = x. 4 +x 3 +1, this polynomial enables the 4-bit linear shift register LFSR to generate the longest sequence with a period of 2. 4 -1=15, the linear shift register LFSR traverses 15 different states (excluding all zeros) within 15 clock cycles; in this embodiment, the register representation of the linear shift register LFSR is a vector reg=[r1 r2 r3 r4], where r1 is the leftmost bit (i.e., the most significant bit) and r4 is the rightmost bit (i.e., the least significant bit); at each rising edge of the clock, all bits of the register are shifted one bit to the right, and the vacated most significant bit is filled by the feedback bit, that is, the register state is updated from [r1 r2 r3 r4] to [f r1 r2 r3]; in this embodiment, the feedback polynomial corresponding to the four-bit primitive polynomial is x. 4 +x 3 +1, under the above bit order convention, the feedback bit f is the XOR of r4 and r3, that is: f=r4⊕r3; in the specific example, the random seed (i.e. the initial state) of the linear feedback shift register is all 1s, that is, [1 1 1 1]. , The corresponding binary number is 0100, meaning that x4, x3, x2, and x1 in the binary number are 0, 1, 0, and 0 respectively. A simulation experiment was conducted on the random number generator described in Example 1. The output results of the linear feedback shift register in Example 1 during each clock cycle are shown in Table 1. Based on the output results of the linear feedback shift register during each clock cycle, the corresponding cases from Case (I) to Case (IV) were selected for calculation to obtain the output results of the random number generator described in Example 1 during each clock cycle, as shown in Table 1: Table 1 shows the output results of the random number generator described in Example 1 for each clock cycle.

[0023] As shown in Table 1, the bitstream obtained in Example 1 is 011101110101111. The bitstream contains 11 "1" bits and 4 "0" bits. The total length of the bitstream is (11 - 4) / 15 = 0.4667, which is approximately equal to the target value. x * ( x * =0.5).

[0024] (2) Another specific example of using the random number generator described in Example 1 to output a bit stream is called Example 2; the difference between Example 2 and Example 1 is only that in Example 2 The binary number is 1100, meaning that x4, x3, x2, and x1 in the binary number are 1, 1, 0, and 0 respectively. A simulation experiment was conducted on the random number generator described in Example 2. The output results of the linear feedback shift register in Example 2 during each clock cycle are shown in Table 2. Based on the output results of the linear feedback shift register during each clock cycle, the corresponding cases from Case (I) to Case (IV) were selected for calculation to obtain the output results of the random number generator described in Example 2 during each clock cycle, as shown in Table 2. Table 2 shows the output results of the random number generator described in Example 2 during each clock cycle.

[0025] In Tables 1 and 2, 7 / 8 represents the value obtained after normalizing the binary number 0111 output by the linear shift register LFSR in the first clock cycle; similarly, 3 / 8, 1 / 8, -8 / 8, etc., also represent the values ​​obtained after normalizing the binary numbers output by the linear shift register LFSR in a certain clock cycle. As shown in Table 2, the bitstream obtained in Example 2 is 00010010001000. The bitstream contains 4 "1" bits and 11 "0" bits. The total length of the bitstream (i.e., the number of bits in the bitstream) is 15. The ratio of (number of "1" bits to number of "0" bits) to the total length of the bitstream is (4-11) / 15 = -0.4667, which is approximately equal to the target value x. * (x * =-0.5).

[0026] Example 2: The difference between Example 2 and Example 1 is that in Example 2, the linear feedback shift register is a seven-bit linear feedback shift register.

[0027] One specific example of using the random number generator output bitstream described in Example 2 is referred to as Example 3: the feedback polynomial of the seven-bit linear feedback shift register is a seven-bit primitive polynomial, P(x) = x 7 +x 4 +x 3 +x 2 +1, this polynomial enables the 7-bit linear shift register LFSR to produce a sequence of maximum length with a sequence period of 2. 7-1=127, the linear shift register LFSR traverses 127 states (excluding all zeros) within 127 clock cycles; in this embodiment, the register representation of the linear shift register LFSR is a vector reg=[r1 r2 r3 r4 r5 r6 r7], where r1 is the leftmost bit (i.e., the most significant bit) and r7 is the rightmost bit (i.e., the least significant bit); at each rising edge of the clock, all bits of the register are shifted one bit to the right, and the vacated most significant bit is filled by the feedback bit, that is, the register state is updated from [r1 r2 r3 r4 r5 r6 r7] to [f r1 r2 r3 r4r5 r6]; in this embodiment, the seven-bit primitive polynomial corresponds to the polynomial x. 7 +x 4 +x 3 +x 2 +1, under the above bit order convention, the feedback bit f is the XOR of r7, r4, r3 and r2, that is: f = r7⊕r4⊕r3⊕r2; in this specific example 3, the random seed (i.e. the initial state) is all 1s, that is, the random seed (i.e. the initial state) is [1 1 1 1 1 1 1]. , The corresponding binary number is 1100000, meaning that in the binary number x7, x6, x5, x4, x3, x2, and x1 are 1, 1, 0, 0, 0, 0, and 0 respectively.

[0028] A simulation experiment was conducted on the random number generator described in Example 3. The bit stream formed by the bits output by the random number generator in Example 3 in each clock cycle according to the timing sequence is as follows: In the bitstream, the number of "1" bits is 32 and the number of "0" bits is 95. The total length of the bitstream is (32 - 95) / 127 = -0.49606, which is approximately equal to the target value x. * (x * =-0.5).

[0029] Example 3: The difference between Example 3 and Example 1 is that in Example 3, the linear feedback shift register is an eight-bit linear feedback shift register.

[0030] One specific example of using the random number generator output bitstream described in Example 3 is referred to as Example 4: the feedback polynomial of the eight-bit linear feedback shift register adopts an eight-bit primitive polynomial, P(x) = x 8 +x 5 +x 3 +x 1 +1, this polynomial enables the 8-bit linear shift register LFSR to produce a sequence of maximum length with a sequence period of 2. 8 -1=255, the linear shift register LFSR traverses 255 different states (excluding all zeros) within 255 clock cycles; in this embodiment, the register representation of the linear shift register LFSR is a vector reg=[r1 r2 r3 r4 r5 r6 r7 r8], where r1 is the leftmost bit (i.e., the most significant bit) and r8 is the rightmost bit (i.e., the least significant bit); at each rising edge of the clock, all bits of the register are shifted one bit to the right, and the vacated most significant bit is filled by the feedback bit, that is, the register state is updated from: [r1 r2 r3 r4 r5 r6 r7 r8] to [f r1r2 r3 r4 r5 r6 r7]; in this embodiment, the feedback polynomial corresponding to the eight-bit primitive polynomial is x. 8 +x 5 +x 3 +x 1 +1, under the above bit order convention, the feedback bit f is the XOR of r8, r5, r3 and r1: f = r8⊕r5⊕r3⊕r1. In this specific example four, the linear feedback shift register takes a random seed (i.e., the initial state) of all 1s, i.e. [1 1 1 1 1 1 1 11]. The corresponding binary number is 11000000, which means that in the binary number x8, x7, x6, x5, x4, x3, x2, and x1 are 1, 1, 0, 0, 0, 0, 0, 0 respectively; A simulation experiment was conducted on the random number generator described in Example 4. The bit stream formed by the bits output by the random number generator in Example 4 in each clock cycle according to the timing sequence is as follows: 0100100000001000100000001001001000001001010000001010000010001010010010010010010010010010010010001001000100100010010001000101010100100010000100001000101010101001000100000100001010101 In the bitstream 000101010000000100000000101000010000100000100010010100100010010000101010100001000000, the number of "1" bits is 64 and the number of "0" bits is 191. (Number of "1" bits - Number of "0" bits) / Total length of bitstream = (64 - 191) / 255 = -0.49804, which is approximately equal to the bipolar target value x. * (x * =-0.5).

[0031] Example 4: The difference between Example 4 and Example 1 is that in Example 4, the linear feedback shift register is a nine-bit linear feedback shift register.

[0032] One specific example of using the random number generator output bitstream described in Example 4 is referred to as Example 5: the feedback polynomial of the nine-bit linear feedback shift register is a nine-bit primitive polynomial, P(x) = x 9 +x 4 +x 3 +x 1 +1, this polynomial enables the 9-bit linear shift register LFSR to produce a sequence of maximum length with a sequence period of 2. 9 -1=511, the linear shift register LFSR traverses 511 different states (excluding all zeros) within 511 clock cycles; in this embodiment, the register representation of the linear shift register LFSR is a vector reg=[r1 r2 r3 r4 r5 r6 r7 r8 r9], where r1 is the leftmost bit (i.e., the most significant bit) and r9 is the rightmost bit (i.e., the least significant bit); at each rising edge of the clock, all bits of the register are shifted one bit to the right, and the vacated most significant bit is filled by the feedback bit, that is, the register state is updated from [r1 r2 r3 r4 r5 r6 r7 r8 r9] to [f r1 r2 r3 r4 r5 r6 r7 r8]; in this embodiment, the feedback polynomial corresponding to the nine-bit primitive polynomial is x. 9 +x 4 +x 3 +x 1+1, under the above bit order convention, the feedback bit f is the XOR of r9, r4, r3 and r1, that is: f = r9⊕r4⊕r3⊕r1; in this specific example five, the random seed (i.e. the initial state) of the linear feedback shift register is all 1s, that is, [1 1 1 11 1 1 1 1]. The corresponding binary number is 110000000, which means that in the binary number x9, x8, x7, x6, x5, x4, x3, x2, and x1 are 1, 1, 0, 0, 0, 0, 0, 0, 0 respectively; A simulation experiment was conducted on the random number generator described in Example 5. The bit stream formed by the bits output by the random number generator in Example 5 in each clock cycle according to the timing sequence is as follows: 01000010100100100000000101000001000100100000100001010000100101010001000100101010010010010001000100100010000001001001001000000010010010010010010010010010010010 10010100100100100100000100001001000000001010101010000001000101010000001010000000101001001001010001010001000001000100000100000100010001000100010 01010001000001000000001000010010000010001000010010000100100100001010000101000010100000010100000001000100100100000010010000001001010100001010000001001001 In the bitstream 00010100010001010100100010000010100001000101000010010000100100000000, the number of "1" bits is 128 and the number of "0" bits is 383. The total length of the bitstream is (128 - 383) / 511 = -0.49902, which is approximately equal to the bipolar target value x. * (x * =-0.5).

[0033] Example 5: The difference between Example 5 and Example 1 is that in Example 5, the linear feedback shift register is a 10-bit linear feedback shift register.

[0034] One specific example of using the random number generator output bitstream described in Example 5 is referred to as Example 6: the feedback polynomial of the 10-bit linear feedback shift register is a 10-bit primitive polynomial, P(x) = x 10 +x 4 +x 3 +x 1 +1, this polynomial enables the 10-bit linear shift register LFSR to produce a sequence of maximum length with a sequence period of 2. 10 -1=1023, the linear shift register LFSR traverses 1023 different states (excluding all zeros) within 1023 clock cycles; in this embodiment, the register representation of the linear shift register LFSR is a vector reg=[r1 r2 r3 r4 r5 r6 r7 r8 r9r10], where r1 is the leftmost bit (i.e., the most significant bit) and r10 is the rightmost bit (i.e., the least significant bit); at each rising edge of the clock, all bits of the register are shifted one bit to the right, and the vacated most significant bit is filled by the feedback bit, that is, the register state is updated from: [r1 r2 r3 r4 r5r6 r7 r8 r9 r10] to [f r1 r2 r3 r4 r5 r6 r7 r8 r9]; in this embodiment, the feedback polynomial corresponding to the ten-bit primitive polynomial is x 10 +x 4 +x 3 +x 1 +1, under the above bit order convention, the feedback bit f is the XOR of r10, r4, r3 and r1: f = r10⊕r4⊕r3⊕r1; in this specific example six, the random seed (i.e. the initial state) of the linear feedback shift register is all 1s, i.e. [1 1 1 1 1 1 1 1 1 1]. Its corresponding binary number is 1100000000, that is, x in the binary number 10 x9, x8, x7, x6, x5, x4, x3, x2, and x1 are respectively 1, 1, 0, 0, 0, 0, 0, 0, 0, 0.

[0035] A simulation experiment was conducted on the random number generator described in Example 6. The bit stream formed by the bits output by the random number generator in Example 6 in each clock cycle according to the timing sequence is as follows: * (x * =-0.5).

[0036] Example 6: A random multiplication circuit having the above-mentioned bitstream random number generator, such as Figure 2 As shown, the circuit includes two bitstream random number generators. The outputs of the two bitstream random number generators are connected to the two inputs of an XNOR gate. The output of the XNOR gate is the output of the random multiplication circuit. The bitstream formed by arranging the bits output by the random multiplication circuit in the timing sequence throughout all clock cycles corresponds to the target value x. * and target value y * The bitstream representation of the product result; the random multiplication circuit described in this application can perform multiplication on x. * The numerical values ​​∈ [-1,1] and their relation to y * The values ​​∈ [-1,1] are used to generate bit streams, and then XOR logic operations are performed to obtain the multiplication result.

[0037] In this sixth embodiment, the linear feedback shift registers in the two bitstream random number generators are linear feedback shift registers with the same number of bits. The two linear feedback shift registers use different primitive polynomials as feedback polynomials, and the random seeds (i.e., initial states) of the two linear feedback shift registers are the same, both being all-1 states. This configuration effectively reduces the correlation between the bitstreams output by the two bitstream random number generators, thereby improving the accuracy of obtaining random multiplication results by performing an XOR operation on the bitstreams output by the two bitstream random number generators. The correlation SCC between the bitstreams output by the two bitstream random number generators is... X,Y The calculation method is shown in equation (1).

[0038] (1) In equation (1), X and Y represent the bitstreams output by two bitstream random number generators, where, P ( X =1) represents the probability value that a bit in bitstream X is 1. P ( Y =1) represents the probability value that a bit in bit stream Y is 1; In equation (1), δ ( X , Y The calculation method for ) is shown in equation (2): δ ( X , Y )= P ( X =1, Y=1)- P ( X =1) P ( Y =1) (2) In equation (2), P ( X =1, Y =1) represents the probability value that a bit in the output bit stream is 1 after performing a logical AND operation on bit streams X and Y; P ( X =1) represents the probability value that a bit in bitstream X is 1. P ( Y =1) represents the probability value that a bit in bit stream Y is 1; SCC( X,Y The value range of SCC is [-1, +1]. X , Y When )=0, it represents the bitstream output by the two bitstream random number generators. X and Y There is no correlation between them, when SCC( X , Y When )=1, it indicates the bitstream output by the two bitstream random number generators. X and Y The two are most positively correlated, when SCC( X , Y When )=-1, it represents the bitstream output by the two bitstream random number generators. X and Y The two have the strongest negative correlation. SCC( X,Y The smaller the absolute value of ), the better the bitstream output by the two bitstream random number generators. X and Y The lower the correlation between them.

[0039] Specifically, in Embodiment Six, the linear feedback shift registers in both bitstream random number generators are four-bit linear feedback shift registers.

[0040] The random multiplication circuit described in this application is suitable for inputting x using different bit depths. * In the generation of bitstreams, the mean square error (MSE) is also used as the accuracy indicator. MSE refers to the theoretical value... t The values ​​observed were obtained from the bitstream obtained through experiments. t The expected value of the square of the difference is calculated as shown in equation (3): (3) The method for calculating the mean square error (MSE) of the random multiplication circuit described in this application is as follows: 20,000 Monte Carlo experiments (i.e., N=20,000) are conducted using MATLAB, and in each Monte Carlo experiment, a target value x in the range of (-1,1) is randomly generated. * and y * Value, the target value x * ×y * The product of these values ​​is taken as the theoretical value; where, in the t-th Monte Carlo experiment, x is randomly generated within the range (-1, 1). * and y * Value, x * ×y * The product of the product is used as the theoretical value. t The value calculated from the bitstream of the output bits of the random multiplication circuit in all clock cycles in each experiment is taken as observed. Specifically, in the t-th Monte Carlo experiment, the value calculated from the bitstream of the output bits of the random multiplication circuit in all clock cycles is taken as observed. t ,observed t = (Number of "1" bits in the bitstream - Number of "0" bits in the bitstream) / Total length of the bitstream; Then, based on formula (3), N=20000, and the theoretical value in each experiment and the observed value calculated based on the bitstream in each experiment, the mean square error (MSE) is calculated; where the target value x * and y * The number of binary bits is consistent with the number of bits in the linear feedback shift register used.

[0041] Calculations show that the random multiplication circuit described in Example 6 uses 4 bits to input x. * and y * When generating a bitstream, the mean square error (MSE) is 0.047677.

[0042] One specific example of using the random multiplication circuit described in Example 6 to output a bit stream is referred to as Example 7: In Example 7, two four-bit linear feedback shift registers use different primitive polynomials as the feedback polynomials of the linear feedback shift registers. The random seeds (i.e. initial states) of the two linear feedback shift registers are the same, both being all-1 states. Both four-bit linear feedback shift registers use four-bit primitive polynomials for their feedback polynomials. The four-bit primitive polynomial of one of the four-bit linear feedback shift registers (hereinafter referred to as LFSR1) is P(x) = x. 4 +x3 +1, the four-bit primitive polynomial of another four-bit linear feedback shift register (hereinafter referred to as LFSR2) is P(x)=x 4 +x 1 +1; Among them, the primitive polynomials of LFSR1 can all enable the linear feedback shift register to generate the longest sequence with a sequence period of 2. 4 -1=15, LFSR1 traverses 15 different states (excluding all zeros) within 15 clock cycles; in this embodiment, the register of LFSR1 is represented as a vector reg=[r1 r2 r3 r4], where r1 is the leftmost bit (i.e., the most significant bit) and r4 is the rightmost bit (i.e., the least significant bit). At each rising edge of the clock, all bits of the register are shifted one bit to the right, and the vacated most significant bit is filled by the feedback bit, that is, the register state is updated from [r1 r2 r3 r4] to [f r1 r2 r3]; in this embodiment, the feedback polynomial corresponding to the four-bit primitive polynomial of LFSR1 is x. 4 +x 3 +1, under the above bit order convention, the feedback bit f of LFSR1 is the XOR of r4 and r3, that is: f=r4⊕r3; The primitive polynomials of LFSR2 can all enable the linear feedback shift register to produce the longest sequence with a period of 2. 4 -1=15, LFSR2 traverses 15 different states (excluding all zeros) within 15 clock cycles; in this embodiment, the register of LFSR2 is represented as a vector reg=[r1 r2 r3 r4], where r1 is the leftmost bit (i.e., the most significant bit) and r4 is the rightmost bit (i.e., the least significant bit). At each rising edge of the clock, all bits of the register are shifted one bit to the right, and the vacated most significant bit is filled by the feedback bit, that is, the register state is updated from [r1 r2 r3 r4] to [f r1 r2 r3]; in this embodiment, the feedback polynomial corresponding to the four-bit primitive polynomial of LFSR2 is x. 4 +x 1 +1, under the above bit order convention, the feedback bit f of LFSR2 is the XOR of r4 and r1, that is: f=r4⊕r1; In this specific example seven, the random seed (i.e., the initial state) of LFSR1 is [1 1 1 1], and the random seed (i.e., the initial state) of LFSR2 is [1 1 1 1]. , , The corresponding x4, x3, x2, and x1 are 0, 1, 0, and 0, respectively. The corresponding y4, y3, y2, and y1 are 1, 1, 0, and 0, respectively; In this specific example seven, one of the bitstream random number generators takes as input a target value x represented by a four-bit binary number. * The highest bit of the linear feedback shift register is a D flip-flop L. n The output signal Q is input to the NOR gate via its first input, and the sign bit x of the n-bit binary number (where n bits represent the target value) is... n The second input of the NOR gate is fed into the NOR gate, which then performs a NOR logic operation; the highest bit of the linear feedback shift register is a D flip-flop L. n The output signal Q is input to the NAND gate via its first input, and the sign bit x of the n-bit binary number is... n The input is passed to the second input terminal of the NAND gate, and the NAND gate performs a NAND logic operation; the amplitude bits of the n-bit binary number correspond to the bits. , … respectively through comparators , … The port inputs are compared to the comparator. The output of the comparator is input to the OR gate OR via the first input of the OR gate OR. The output of the NOR gate OR is input to the OR gate OR via the second input of the OR gate OR. The OR gate OR performs an OR operation on the output of the comparator and the output of the NOR gate OR. The output of the OR gate OR is input to the AND gate AND via the first input of the AND gate AND. The NAND gate NAND performs an AND operation on the output of the OR gate OR and the output of the NAND gate NAND, and then outputs the result. The other bitstream random number generator takes as input the target value y, represented by a four-bit binary number. * The highest bit of the linear feedback shift register is a D flip-flop L. n The output signal Q is input to the NOR gate via its first input, and the sign bit y of the n-bit binary number (where n bits represent the target value) is... n The second input of the NOR gate is fed into the NOR gate, which then performs a NOR logic operation; the highest bit of the linear feedback shift register is a D flip-flop L. n The output signal Q is input to the NAND gate via the first input of the NAND gate, and the sign bit y of the n-bit binary number is... n The input is passed to the second input terminal of the NAND gate, and the NAND gate performs a NAND logic operation; the amplitude bits of the n-bit binary number correspond to the bits. , … respectively through comparators , … The port inputs are compared to the comparator. The output of the comparator is input to the OR gate OR via the first input of the OR gate OR. The output of the NOR gate OR is input to the OR gate OR via the second input of the OR gate OR. The OR gate OR performs an OR operation on the output of the comparator and the output of the NOR gate OR. The output of the OR gate OR is input to the AND gate AND via the first input of the AND gate AND. The NAND gate NAND performs an AND operation on the output of the OR gate OR and the output of the NAND gate NAND, and then outputs the result. The outputs of the two bitstream random number generators are logically processed by an XNOR gate. By arranging the bits output by the XNOR gate in all time cycles according to their timing sequence, the target value x can be obtained. * and target value y * The bitstream resulting from the product of the two numbers; where, in the bitstream above, (the number of "1" bits - the number of "0" bits) / the total length of the bitstream is approximately equal to the target value x. * and target value y * The product result; A simulation experiment was conducted on the random multiplication circuit described in Example 7. The output results of the linear feedback shift register in Example 7 during each clock cycle are shown in Table 3. Based on the output results of the linear feedback shift register during each clock cycle, the corresponding case was selected from the four cases described in Case (I) to Case (IV) for operation. Finally, an XNOR gate logic operation was performed to obtain the output results of the random multiplication circuit described in Example 7 during each clock cycle, as shown in Table 3. Table 3 shows the output results of the random multiplication circuit described in Example 7 for each clock cycle.

[0043] As shown in Table 3, in Example 7, the bit stream formed by the bits output by the first random number generator in all clock cycles in the order of timing is: 011101110101111. The bit stream formed by the bits output by the second random number generator in all clock cycles arranged in time sequence is 010100010001000; In Example 7, the bitstream formed by the bits output from the first and second random number generators after being processed by an XNOR gate in all clock cycles, arranged in chronological order, is 110110011011000. The bitstream contains 8 "1" bits and 7 "0" bits. The total length of the bitstream is (8-7) / 15 = 1 / 15 = 0.0667. This value is approximately equal to the target value x.* ×y ∗ =-0.25.

[0044] Example 7: The difference between Example 7 and Example 6 is that both linear feedback shift registers used in Example 7 are seven-bit linear feedback shift registers.

[0045] Calculations show that the random multiplication circuit described in Example 7 uses 7 bits to input x. * and y * When generating a bitstream, the mean square error (MSE) is 38.101 × 10⁻⁶. -4 The mean square error (MSE) in Example 7 is calculated in the same way as in Example 6.

[0046] One specific example of using the random multiplication circuit described in Example 7 to output a bit stream is referred to as Example 8: In Example 8, the two linear feedback registers are referred to as LFSR1 and LFSR2, respectively. The feedback polynomial of LFSR1 is a seven-bit primitive polynomial P(x) = x. 7 +x 4 +x 3 +x 2 +1, The feedback polynomial of LFSR2 uses the seven-bit primitive polynomial P(x) = x 7 +x 5 +x 3 +x 1 +1; Among them, the primitive polynomials of LFSR1 can all enable the linear feedback shift register to generate the longest sequence with a sequence period of 2. 7 -1=127, LFSR1 traverses 127 different states (excluding all zeros) within 127 clock cycles; in this embodiment, the register of LFSR1 is represented as a vector reg=[r1 r2 r3 r4 r5 r6 r7], where r1 is the leftmost bit (i.e., the most significant bit) and r7 is the rightmost bit (i.e., the least significant bit). At each rising edge of the clock, all bits of the register are shifted one bit to the right, and the vacated most significant bit is filled by the feedback bit, that is, the register state is updated from [r1 r2 r3 r4 r5 r6 r7] to [f r1 r2 r3 r4 r5r6]; in this embodiment, the feedback polynomial corresponding to the seven-bit primitive polynomial of LFSR1 is x. 7 +x 4 +x 3 +x 2 +1, under the above bit order convention, the feedback bit f is the XOR of r7, r4, r3 and r2: f = r7⊕r4⊕r3⊕r2; The primitive polynomials of LFSR2 can all enable the linear feedback shift register to produce the longest sequence with a period of 2. 7 -1=127, LFSR2 traverses 127 different states (excluding all zeros) within 127 clock cycles; in this embodiment, the register of LFSR2 is represented as a vector reg=[r1 r2 r3 r4 r5 r6 r7], where r1 is the leftmost bit (i.e., the most significant bit) and r7 is the rightmost bit (i.e., the least significant bit). At each rising edge of the clock, all bits of the register are shifted one bit to the right, and the vacated most significant bit is filled by the feedback bit, that is, the register state is updated from [r1 r2 r3 r4 r5 r6 r7] to [f r1 r2 r3 r4 r5r6]; the feedback polynomial corresponding to the seven-bit primitive polynomial of LFSR2 is x. 7 +x 5 +x 3 +x 1 +1, under the above bit order convention, the feedback bit f is the XOR of r7, r5, r3 and r1: f = r7⊕r5⊕r3⊕r1; In this embodiment, the random seed (i.e., the initial state) of LFSR1 is [1 1 1 1 1 1 1], and the random seed (i.e., the initial state) of LFSR2 is [1 1 1 1 1 1 1].

[0047] , , The corresponding x7, x6, x5, x4, x3, x2, and x1 are 0, 1, 0, 0, 0, 0, and 0, respectively. The corresponding values ​​for y7, y6, y5, y4, y3, y2, and y1 are 1, 1, 0, 0, 0, 0, and 0, respectively.

[0048] A simulation experiment was conducted on the random multiplication circuit described in Example 8. The bit stream formed by the bits output by the random multiplication circuit in Example 8 in each clock cycle according to the timing sequence is: 1101100101110101010101110000000011100000100001100000010101010100000000000101000100000000100000010100010001100011000101001000000. In the bit stream, the number of bits "1" is 40 and the number of bits "0" is 87. (Number of bits "1" - Number of bits "0") / Total length of bit stream = (40 - 87) / 127 = -0.37008, which is approximately equal to the target value x. * and target value y * The product is -0.25.

[0049] Example 8: The difference between Example 8 and Example 6 is that both linear feedback shift registers used in Example 8 are eight-bit linear feedback shift registers.

[0050] Calculations show that the random multiplication circuit described in Example 8 uses 8 bits to input x. * and y * When generating a bitstream, the mean square error (MSE) is 18.438 × 10⁻⁶. -4 The mean square error (MSE) in Example 8 is calculated in the same way as in Example 6.

[0051] One specific example of using the random multiplication circuit described in Example 8 to output a bit stream is referred to as Example 9: In Example 9, the two linear feedback registers are referred to as LFSR1 and LFSR2, respectively. The feedback polynomial of LFSR1 is an 8-bit primitive polynomial P(x) = x. 8 +x 5 +x 3 +x 1 +1, The feedback polynomial of LFSR2 adopts the octet primitive polynomial P(x)=x 8 +x 4 +x 3 +x 2 +1; Among them, the primitive polynomials of LFSR1 can all enable the linear feedback shift register to generate the longest sequence with a sequence period of 2. 8 -1=255, LFSR1 traverses 255 different states (excluding all zeros) within 255 clock cycles; in this embodiment, the register of LFSR1 is represented as a vector reg=[r1 r2 r3 r4 r5 r6 r7 r8], where r1 is the leftmost bit (i.e., the most significant bit) and r8 is the rightmost bit (i.e., the least significant bit). At each rising edge of the clock, all bits of the register are shifted one bit to the right, and the vacated most significant bit is filled by the feedback bit, that is, the register state is updated from [r1 r2 r3 r4 r5 r6 r7 r8] to [f r1 r2 r3r4 r5 r6 r7]; in this embodiment, the feedback polynomial corresponding to the eight-bit primitive polynomial of LFSR1 is x. 8 +x 5 +x 3 +x 1 +1, under the above bit order convention, the feedback bit f is the XOR of r8, r5, r3 and r1: f = r8⊕r5⊕r3⊕r1; The primitive polynomials of LFSR2 can all enable the linear feedback shift register to produce the longest sequence with a period of 2. 8 -1=255, LFSR2 traverses 255 different states (excluding all zeros) within 255 clock cycles; in this embodiment, the LFSR2 register is represented as a vector reg=[r1 r2 r3 r4 r5 r6 r7 r8], where r1 is the leftmost bit (i.e., the most significant bit) and r8 is the rightmost bit (i.e., the least significant bit). At each rising edge of the clock, all bits of the register are shifted one bit to the right, and the vacated most significant bit is filled by the feedback bit, that is, the register state is updated from [r1 r2 r3 r4 r5 r6 r7 r8] to [f r1 r2 r3r4 r5 r6 r7]; the feedback polynomial corresponding to the nine-bit primitive polynomial of LFSR2 is x. 8 +x 4 +x 3 +x 2 +1, under the above bit order convention, the feedback bit f is the XOR of r8, r4, r3 and r2: f = r8⊕r4⊕r3⊕r2; In this embodiment, the random seed (i.e., the initial state) of LFSR1 is [1 1 1 1 1 1 1 1], and the random seed (i.e., the initial state) of LFSR2 is [1 1 1 1 1 1 1 1]. , , The corresponding x8, x7, x6, x5, x4, x3, x2, and x1 are 0, 1, 0, 0, 0, 0, 0, 0, respectively. The corresponding values ​​for y8, y7, y6, y5, y4, y3, y2, and y1 are 1, 1, 0, 0, 0, 0, 0, 0, respectively.

[0052] A simulation experiment was conducted on the random multiplication circuit described in Example 9. The bit stream formed by the bits output by the random multiplication circuit in Example 9 in each clock cycle according to the timing sequence is as follows: 1000010101001001000010101100010110000111110011000001001001100001101000010110000110100001011000011010000110100000110100000110011100011001001011010011101100 In the bitstream, the number of "1" bits is 90 and the number of "0" bits is 165. The total length of the bitstream is (90 - 165) / 255 = -0.29412, which is approximately equal to the bipolar target value. x * and bipolar target value y * The product is -0.25.

[0053] Example 9: The difference between Example 9 and Example 6 is that both linear feedback shift registers used in Example 9 are nine-bit linear feedback shift registers.

[0054] Calculations show that the random multiplication circuit described in Example 9 uses 9 bits to input x. * and y * When generating a bitstream, the mean square error (MSE) is 9.106 × 10⁻⁶. -4 The mean square error (MSE) in Example 9 is calculated in the same way as in Example 6.

[0055] One specific example of using the random multiplication circuit described in Example 9 to output a bit stream is referred to as Example 10: In Example 10, the two linear feedback registers are referred to as LFSR1 and LFSR2, respectively. The feedback polynomial of LFSR1 is a nine-bit primitive polynomial P(x) = x. 9 +x 4 +x 3 +x 1 +1, The feedback polynomial of LFSR2 adopts the nine-bit primitive polynomial P(x) = x 9 +x 5 +x 4 +x1 +1; Among them, the primitive polynomials of LFSR1 can all enable the linear feedback shift register to generate the longest sequence with a sequence period of 2. 9 -1=511, LFSR1 traverses 511 different states (excluding all zeros) within 511 clock cycles; in this embodiment, the register of LFSR1 is represented as a vector reg=[r1 r2 r3 r4 r5 r6 r7 r8 r9], where r1 is the leftmost bit (i.e., the most significant bit) and r9 is the rightmost bit (i.e., the least significant bit). At each rising edge of the clock, all bits of the register are shifted one bit to the right, and the vacated most significant bit is filled by the feedback bit, that is, the register state is updated from [r1 r2 r3 r4 r5 r6 r7 r8 r9] to [f r1 r2r3 r4 r5 r6 r7 r8]; the feedback polynomial corresponding to the 10-bit primitive polynomial of LFSR1 is x. 9 +x 4 +x 3 +x 1 +1, under the above bit order convention, the feedback bit f is the XOR of r9, r4, r3 and r1: f = r9⊕r4⊕r3⊕r1; Among them, the primitive polynomials of LFSR2 can all enable the linear feedback shift register to generate the longest sequence with a sequence period of 2. 9 -1=511, LFSR2 traverses 511 different states (excluding all zeros) within 511 clock cycles; in this embodiment, the register of LFSR2 is represented as a vector reg=[r1 r2 r3 r4 r5 r6 r7 r8 r9], where r1 is the leftmost bit (i.e., the most significant bit) and r9 is the rightmost bit (i.e., the least significant bit). At each rising edge of the clock, all bits of the register are shifted one bit to the right, and the vacated most significant bit is filled by the feedback bit, that is, the register state is updated from [r1 r2 r3 r4 r5 r6 r7 r8 r9] to [f r1 r2r3 r4 r5 r6 r7 r8]; the feedback polynomial corresponding to the 10-bit primitive polynomial of LFSR1 is x. 9 +x 5 +x 4 +x 1 +1, under the above bit order convention, the feedback bit f is the XOR of r9, r5, r4 and r1: f = r9⊕r5⊕r4⊕r1; In this embodiment, the random seed (i.e., the initial state) of LFSR1 is [1 1 1 1 1 1 1 1 1], and the random seed (i.e., the initial state) of LFSR2 is [1 1 1 1 1 1 1 1 1]. , , The corresponding x9, x8, x7, x6, x5, x4, x3, x2, and x1 are 0, 1, 0, 0, 0, 0, 0, 0, 0, respectively. The corresponding y9, y8, y7, y6, y5, y4, y3, y2, and y1 are 1, 1, 0, 0, 0, 0, 0, 0, 0, respectively.

[0056] A simulation experiment was conducted on the random multiplication circuit described in Example 10. The bit stream formed by the bits output by the random multiplication circuit in Example 10 in each clock cycle according to the timing sequence is as follows: 11110001011010010100100001100000000010101000000011000011101001000000111000110010110100001010000001000 10001010111000100110110001001100110110101111110100011010100001101101001010111110100110001010101111101001100010101000001000101101001100100110 10100010000110100100011010000000000010010100110001000011001001000010100000100011000001001110011011001111001000010110010001001100000001010000100111100001 In the bitstream, the number of "1" bits is 184 and the number of "0" bits is 327. The total length of the bitstream is (184 - 327) / 511 = -0.27984, which is approximately equal to the bipolar target value. x * and bipolar target value y * The product result.

[0057] Example 10: The difference between Example 10 and Example 6 is that both linear feedback shift registers used in Example 10 are 10-bit linear feedback shift registers.

[0058] Calculations show that the random multiplication circuit described in Example 10 uses 9 bits to input x. * and y * When generating a bitstream, the mean square error (MSE) is 4.566 × 10⁻⁶. -4 The mean square error (MSE) in Example 10 is calculated in the same way as the mean square error (MSE) in Example 6.

[0059] One specific example of using the random multiplication circuit described in Example 10 to output a bit stream is referred to as Example 11: In Example 11, the two linear feedback registers are referred to as LFSR1 and LFSR2, respectively. The feedback polynomial of LFSR1 is the ten-bit primitive polynomial P(x) = x. 10 +x 4 +x 3 +x 1 +1, The feedback polynomial of LFSR2 adopts the ten-digit primitive polynomial P(x) = x 10 +x 5 +x 3 +x 2 +1; Among them, the primitive polynomials of LFSR1 can all enable the linear feedback shift register to generate the longest sequence with a sequence period of 2. 10 -1=1023, LFSR1 traverses 1023 different states (excluding all zeros) within 1023 clock cycles; in this embodiment, the register of LFSR1 is represented as a vector reg=[r1 r2 r3 r4 r5 r6 r7 r8 r9 r10], where r1 is the leftmost bit (i.e., the most significant bit) and r10 is the rightmost bit (i.e., the least significant bit). At each rising edge of the clock, all bits of the register are shifted one bit to the right, and the vacated most significant bit is filled by the feedback bit, that is, the register state is updated from [r1 r2 r3 r4 r5 r6 r7 r8 r9 r10] to [f r1 r2 r3 r4 r5 r6 r7 r8 r9]; in this embodiment, the feedback polynomial corresponding to the 10-bit primitive polynomial of LFSR1 is x. 10 +x 4 +x 3 +x 1 +1, under the above bit order convention, the feedback bit f is the XOR of r10, r4, r3 and r1: f = r10⊕r4⊕r3⊕r1; The primitive polynomials of LFSR2 can all enable the linear feedback shift register to produce the longest sequence with a period of 2. 10-1=1023, LFSR2 traverses 1023 different states (excluding all zeros) within 1023 clock cycles; in this embodiment, the register of LFSR2 is represented as a vector reg=[r1 r2 r3 r4 r5 r6 r7 r8 r9 r10], where r1 is the leftmost bit (i.e., the most significant bit) and r10 is the rightmost bit (i.e., the least significant bit). At each rising edge of the clock, all bits of the register are shifted one bit to the right, and the vacated most significant bit is filled by the feedback bit, that is, the register state is updated from: [r1 r2 r3 r4 r5 r6 r7 r8 r9 r10] to [f r1 r2 r3 r4 r5 r6 r7 r8 r9]; in this embodiment, the feedback polynomial corresponding to the 10-bit primitive polynomial of LFSR2 is x. 10 +x 5 +x 3 +x 2 +1, under the above bit order convention, the feedback bit f is the XOR of r10, r5, r3 and r2: f = r10⊕r5⊕r3⊕r2; In this embodiment, the random seed (i.e., the initial state) of LFSR1 is [1 1 1 1 1 1 1 1 1 1], and the random seed (i.e., the initial state) of LFSR2 is [1 1 1 1 1 1 1 1 1 1 1]. , , The corresponding x 10 x9, x8, x7, x6, x5, x4, x3, x2, x1 are 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 respectively. Corresponding y 10 y9, y8, y7, y6, y5, y4, y3, y2, and y1 are respectively 1, 1, 0, 0, 0, 0, 0, 0, 0, 0.

[0060] x * and bipolar target value y * The product result.

[0061] The results above show that the higher the number of bits in the linear feedback shift register used in the random multiplication circuit with a bitstream random number generator described in this application, the more bits are corresponding to the target value. Therefore, the value represented by the bitstream output by the random multiplication circuit described in this application (the number of "1" bits in the bitstream - the number of "0" bits) / the total length of the bitstream is relative to the target value x. * and target value y * The smaller the mean square error (MSE) of the product result, the more significant the improvement in the calculation accuracy of the random multiplication circuit in this application becomes as the number of bits of the linear feedback shift register (LFSR) increases.

[0062] Test comparison: Comparison Method: Step S1: The target value x disclosed in "Gradient Descent Using Stochastic Circuits for Efficient Training of Learning Machines" is... * Existing methods for converting the target value x ∈ [-1,1] into a bitstream via mapping operations first convert the target value x ∈ [-1,1] into a bitstream. * Mapped to (x * +1) / 2, then (x * +1) / 2 is mapped to [0,1], and then converted into a random sequence using a random number generator SNG, which is the bit stream; Step S2: Based on the two target values, the bit streams corresponding to the two target values ​​are obtained using the steps described in step S1; Step S3: The two bit streams obtained in step S2 are XORed to obtain the bit stream corresponding to the product of the two target values.

[0063] When the above comparison method is used and two target values ​​are input using 4 bits to generate a bitstream, it is called Comparison Example 1; when the above comparison method is used and two target values ​​are input using 7 bits to generate a bitstream, it is called Comparison Example 2; when the above comparison method is used and two target values ​​are input using 8 bits to generate a bitstream, it is called Comparison Example 3; when the above comparison method is used and two target values ​​are input using 9 bits to generate a bitstream, it is called Comparison Example 4; when the above comparison method is used and two target values ​​are input using 10 bits to generate a bitstream, it is called Comparison Example 5.

[0064] Calculate the mean squared error (MSE) of the methods described in Comparative Examples 1 to 5. The methods for calculating the MSE of Comparative Examples 1 to 5 are the same as those used in Example 6. The calculated MSE results for Comparative Examples 1 to 5 are 501.821 × 10⁻⁶. -4 43.561×10 -4 20.522×10 -4 10.341×10 -4 5.331×10 -4 As mentioned above, the mean square error (MSE) of the multiplication circuits described in Examples 6 to 10 are 0.047677, 38.101 × 10⁻⁶, and 38.101 × 10⁻⁶, respectively. -4 18.438×10 -4 9.106×10 -4 4.566×10 -4 Clearly, when 4 bits are used to input two target values ​​to generate a bit stream, the mean square error (MSE) of the multiplication circuit described in Example 6 is reduced by (0.0501821 - 0.047677) / 0.0501821 × 100% = 4.99% compared to Comparative Example 1. Similarly, when 7 bits are used to input two target values ​​to generate a bit stream, the MSE of the multiplication circuit described in Example 7 is reduced by 12.53% compared to Comparative Example 2; when 8 bits are used to input two target values ​​to generate a bit stream, the MSE of the multiplication circuit described in Example 8 is reduced by 10.15% compared to Comparative Example 3; when 9 bits are used to input two target values ​​to generate a bit stream, the MSE of the multiplication circuit described in Example 9 is reduced by 11.94% compared to Comparative Example 4; and when 10 bits are used to input two target values ​​to generate a bit stream, the MSE of the multiplication circuit described in Example 10 is reduced by 14.35% compared to Comparative Example 5. In addition, this application also tested the average correlation of the two bitstreams generated before the XOR operation in Comparative Examples 1 to 5 and the average correlation of the two bitstreams generated before the XOR operation in Examples 6 to 10. The specific testing methods are as follows: MATLAB was used to conduct 20,000 Monte Carlo experiments (N=20,000), and in each Monte Carlo experiment, a target value x in the range of (-1,1) was randomly generated. * and y * The correlation SCC (value) of the two bitstreams generated before the XOR operation in each experiment is calculated using formulas (1) and (2). X,Y Then, the correlation SCC (Score Correlation Coefficient) was calculated from 20,000 Monte Carlo experiments. X,YThe absolute values ​​of the two bitstreams are taken, where the bitstream generated before the XOR operation refers to the bitstream composed of the bits output in all clock cycles before the XOR operation. Then, the average of the 20,000 absolute values ​​is obtained to get the average correlation result. The larger the average correlation result, the greater the correlation between the two bitstreams generated before the XOR operation; the smaller the average correlation result, the smaller the correlation between the two bitstreams generated before the XOR operation. In other words, the average correlation result reflects the correlation between the two bitstreams generated before the XOR operation in Comparative Examples 1 to 5, and the correlation between the two bitstreams generated before the XOR operation in Examples 6 to 10. In this application, since SCC ( X,Y The value of ) ranges from -1 to 1, where a positive value indicates a positive correlation and a negative value indicates a negative correlation. Regardless of whether it is a positive or negative correlation, it reflects the existence of a correlation between the two bitstreams. Therefore, in calculating the average correlation, this application uses SCC (from 20,000 experiments) as an example. X,Y The result is first taken as the absolute value and then averaged.

[0065] The above tests show that the average correlation of the two bitstreams generated before the XOR operation described in Examples 1 to 5 is 0.552, 0.284, 0.212, 0.155, and 0.115, respectively; the average correlation of the two bitstreams generated before the XOR operation described in Examples 6 to 10 is 0.524, 0.258, 0.189, 0.143, and 0.103, respectively. Clearly, when 4 bits are used to input two target values ​​to generate a bitstream, the average correlation of the two bitstreams generated before the XOR operation described in Example 6 is reduced by (0.552-0.524) / 0.552×100%=5.07% compared to Example 1. Similarly, when 7 bits are used to input two target values ​​to generate... When generating bitstreams, the average correlation calculation result of the two bitstreams generated before the XOR operation by the multiplication circuit described in Example 7 is reduced by 9.1% compared to Comparative Example 2; when using 8 bits to input two target values ​​to generate bitstreams, the average correlation calculation result of the two bitstreams generated before the XOR operation by the multiplication circuit described in Example 8 is reduced by 10.85% compared to Comparative Example 3; when using 9 bits to input two target values ​​to generate bitstreams, the average correlation calculation result of the two bitstreams generated before the XOR operation by the multiplication circuit described in Example 9 is reduced by 7.74% compared to Comparative Example 4; when using 10 bits to input two target values ​​to generate bitstreams, the average correlation calculation result of the two bitstreams generated before the XOR operation by the multiplication circuit described in Example 10 is reduced by 10.43% compared to Comparative Example 5.

[0066] In this application, the two bit streams generated by the multiplication circuits described in Embodiments 6 to 10 before performing the XOR operation are essentially bit streams generated by the two bit stream random number generators in each embodiment. As can be seen from the above, the correlation between the two bit streams generated by the multiplication circuits described in Embodiments 6 to 10 of this application before performing the XOR operation is significantly lower than the correlation between the two bit streams generated by the methods described in Comparative Examples 1 to 5 before performing the XOR operation. In the multiplication circuit described in this application, two bitstream random number generators can generate two bitstreams with low correlation, thereby making the value of the bitstream obtained by multiplying the two bitstreams (i.e., XOR operation) closer to the product of the two target values, thus reducing the error between the value of the bitstream obtained by multiplying the two bitstreams (i.e., XOR operation) and the product of the two target values. Moreover, judging from the test results, the mean square error (MSE) of the multiplication circuit described in Embodiments 6 to 10 of this application is indeed significantly lower than the mean square error (MSE) of the method described in Comparative Examples 1 to 5.

[0067] Those skilled in the art should understand that the above examples are intended to help understand the principles of the present invention and do not constitute a limitation on the scope of protection of the present invention. Based on the technical content disclosed in this invention, those skilled in the art can make various specific modifications and combinations without departing from its core ideas, and these modifications should also be included within the scope of protection of this invention.

Claims

1. A bitstream random number generator, characterized in that: The highest bit of the linear feedback shift register's D flip-flop L n Inverting signal terminal Connect the output signal terminals of the n-1 low-order flip-flops in the linear feedback shift register to the NOR gate and the NAND gate respectively. Each is connected to the comparator; the sign bit x of the corresponding n-bit binary number of the target value. n Input NOR gates and NAND gates respectively; the bits corresponding to the amplitude bits of an n-bit binary number. to Input to the comparator; the comparator and NOR gate are both connected to the OR gate; the OR gate and NAND gate are both connected to the AND gate.

2. The bitstream random number generator according to claim 1, characterized in that: The feedback polynomial of a linear feedback shift register uses a primitive polynomial.

3. A bitstream random number generator according to claim 1, characterized in that: The highest bit D flip-flop L n This refers to the nth D flip-flop; the (n-1)th low-order flip-flop refers to the (n-1)th D flip-flop. The (n-2)th D flip-flop Up to the first D flip-flop .

4. The bitstream random number generator according to claim 1, characterized in that: The sign bit refers to the highest bit of the n-bit binary number represented by the target value, and the amplitude bit refers to the other bits in the n-bit binary number represented by the target value, excluding the highest bit.

5. A method for calculating a random number generator, characterized in that: The random number generator is the bitstream random number generator as described in claim 1; the random number generator calculation method includes the following steps: decomposing the binary number corresponding to the target value into a sign bit and an amplitude bit, and the comparator outputs signals to the n-1 low-order flip-flops in the linear feedback shift register. The output result is compared with the corresponding bit of the amplitude bit to determine the numerical value; the NOR gate is used to connect the highest bit of the linear feedback shift register's D flip-flop L. n Inverting signal terminal The output result and the bit corresponding to the sign bit are subjected to a NOR operation. The NAND gate is used to invert the signal input of the highest-order D flip-flop Ln of the linear feedback shift register. The output result and the bit corresponding to the sign bit are subjected to NAND logic operation. The OR gate is subjected to OR logic operation on the output result of the NOR gate and the output result of the comparator. The AND gate is subjected to AND logic operation on the output result of the OR gate and the output result of the NAND gate. The output result of the AND gate is the output result of the bit stream random number generator. The bits output by the AND gate in all clock cycles are arranged in the timing order to form the bit stream.

6. An application of a bitstream random number generator in a multiplication circuit, wherein the bitstream random number generator is the bitstream random number generator as described in claim 1.

7. A random multiplication circuit based on a bitstream random number generator, characterized in that: It includes two bitstream random number generators as described in claim 1, both of which are bitstream random number generators as described in claim 1, and the output terminals of both bitstream random number generators are connected to an XNOR gate.

8. A random multiplication circuit based on a bitstream random number generator according to claim 7, characterized in that: The feedback polynomials of the linear feedback shift registers in the two bitstream random number generators are different.

9. A random multiplication circuit based on a bitstream random number generator according to claim 7, characterized in that: The linear feedback shift registers in the two bitstream random number generators have the same feedback polynomial, but the random seeds of the two linear feedback shift registers are different.

10. A calculation method for a random multiplication circuit, characterized in that: The random multiplication circuit is the random multiplication circuit based on a bitstream random number generator as described in claim 7; the calculation method of the random multiplication circuit includes the following steps: the output results of the two bitstream random number generators are logically operated through a XNOR gate; the bits output by the XNOR gate in all time periods are arranged in the timing order to obtain the value corresponding to the target value x. * and target value y * The bit stream of the product result.

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